1;; Scheduling description for PowerPC 603 processor. 2;; Copyright (C) 2003-2020 Free Software Foundation, Inc. 3;; 4;; This file is part of GCC. 5 6;; GCC is free software; you can redistribute it and/or modify it 7;; under the terms of the GNU General Public License as published 8;; by the Free Software Foundation; either version 3, or (at your 9;; option) any later version. 10 11;; GCC is distributed in the hope that it will be useful, but WITHOUT 12;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 14;; License for more details. 15 16;; You should have received a copy of the GNU General Public License 17;; along with GCC; see the file COPYING3. If not see 18;; <http://www.gnu.org/licenses/>. 19 20(define_automaton "ppc603,ppc603fp") 21(define_cpu_unit "iu_603" "ppc603") 22(define_cpu_unit "fpu_603" "ppc603fp") 23(define_cpu_unit "lsu_603,bpu_603,sru_603" "ppc603") 24 25;; PPC603/PPC603e 32-bit IU, LSU, FPU, BPU, SRU 26;; Max issue 3 insns/clock cycle (includes 1 branch) 27 28;; Branches go straight to the BPU. All other insns are handled 29;; by a dispatch unit which can issue a max of 2 insns per cycle. 30 31;; The PPC603e user's manual recommends that to reduce branch mispredictions, 32;; the insn that sets CR bits should be separated from the branch insn 33;; that evaluates them; separation by more than 9 insns ensures that the CR 34;; bits will be immediately available for execution. 35;; This could be artificially achieved by exaggerating the latency of 36;; compare insns but at the expense of a poorer schedule. 37 38;; CR insns get executed in the SRU. Not modelled. 39 40(define_insn_reservation "ppc603-load" 2 41 (and (eq_attr "type" "load,load_l") 42 (eq_attr "cpu" "ppc603")) 43 "lsu_603") 44 45(define_insn_reservation "ppc603-store" 2 46 (and (eq_attr "type" "store,fpstore") 47 (eq_attr "cpu" "ppc603")) 48 "lsu_603*2") 49 50(define_insn_reservation "ppc603-fpload" 2 51 (and (eq_attr "type" "fpload") 52 (eq_attr "cpu" "ppc603")) 53 "lsu_603") 54 55(define_insn_reservation "ppc603-storec" 8 56 (and (eq_attr "type" "store_c") 57 (eq_attr "cpu" "ppc603")) 58 "lsu_603") 59 60(define_insn_reservation "ppc603-integer" 1 61 (and (ior (eq_attr "type" "integer,insert,trap,cntlz,isel") 62 (and (eq_attr "type" "add,logical,shift,exts") 63 (eq_attr "dot" "no"))) 64 (eq_attr "cpu" "ppc603")) 65 "iu_603") 66 67(define_insn_reservation "ppc603-two" 1 68 (and (eq_attr "type" "two") 69 (eq_attr "cpu" "ppc603")) 70 "iu_603,iu_603") 71 72(define_insn_reservation "ppc603-three" 1 73 (and (eq_attr "type" "three") 74 (eq_attr "cpu" "ppc603")) 75 "iu_603,iu_603,iu_603") 76 77; This takes 2 or 3 cycles 78(define_insn_reservation "ppc603-imul" 3 79 (and (eq_attr "type" "mul") 80 (eq_attr "size" "32") 81 (eq_attr "cpu" "ppc603")) 82 "iu_603*2") 83 84(define_insn_reservation "ppc603-imul2" 2 85 (and (eq_attr "type" "mul") 86 (eq_attr "size" "8,16") 87 (eq_attr "cpu" "ppc603")) 88 "iu_603*2") 89 90(define_insn_reservation "ppc603-idiv" 37 91 (and (eq_attr "type" "div") 92 (eq_attr "cpu" "ppc603")) 93 "iu_603*37") 94 95(define_insn_reservation "ppc603-compare" 3 96 (and (ior (eq_attr "type" "cmp") 97 (and (eq_attr "type" "add,logical,shift,exts") 98 (eq_attr "dot" "yes"))) 99 (eq_attr "cpu" "ppc603")) 100 "iu_603,nothing,bpu_603") 101 102(define_insn_reservation "ppc603-fpcompare" 3 103 (and (eq_attr "type" "fpcompare") 104 (eq_attr "cpu" "ppc603")) 105 "(fpu_603+iu_603*2),bpu_603") 106 107(define_insn_reservation "ppc603-fp" 3 108 (and (eq_attr "type" "fp,fpsimple") 109 (eq_attr "cpu" "ppc603")) 110 "fpu_603") 111 112(define_insn_reservation "ppc603-dmul" 4 113 (and (eq_attr "type" "dmul") 114 (eq_attr "cpu" "ppc603")) 115 "fpu_603*2") 116 117; Divides are not pipelined 118(define_insn_reservation "ppc603-sdiv" 18 119 (and (eq_attr "type" "sdiv") 120 (eq_attr "cpu" "ppc603")) 121 "fpu_603*18") 122 123(define_insn_reservation "ppc603-ddiv" 33 124 (and (eq_attr "type" "ddiv") 125 (eq_attr "cpu" "ppc603")) 126 "fpu_603*33") 127 128(define_insn_reservation "ppc603-crlogical" 2 129 (and (eq_attr "type" "cr_logical,mfcr,mtcr") 130 (eq_attr "cpu" "ppc603")) 131 "sru_603") 132 133(define_insn_reservation "ppc603-mtjmpr" 4 134 (and (eq_attr "type" "mtjmpr") 135 (eq_attr "cpu" "ppc603")) 136 "sru_603") 137 138(define_insn_reservation "ppc603-mfjmpr" 2 139 (and (eq_attr "type" "mfjmpr,isync,sync") 140 (eq_attr "cpu" "ppc603")) 141 "sru_603") 142 143(define_insn_reservation "ppc603-jmpreg" 1 144 (and (eq_attr "type" "jmpreg,branch") 145 (eq_attr "cpu" "ppc603")) 146 "bpu_603") 147 148