riscv.opt revision 1.7
1; Options for the RISC-V port of the compiler 2; 3; Copyright (C) 2011-2018 Free Software Foundation, Inc. 4; 5; This file is part of GCC. 6; 7; GCC is free software; you can redistribute it and/or modify it under 8; the terms of the GNU General Public License as published by the Free 9; Software Foundation; either version 3, or (at your option) any later 10; version. 11; 12; GCC is distributed in the hope that it will be useful, but WITHOUT 13; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15; License for more details. 16; 17; You should have received a copy of the GNU General Public License 18; along with GCC; see the file COPYING3. If not see 19; <http://www.gnu.org/licenses/>. 20 21HeaderInclude 22config/riscv/riscv-opts.h 23 24mbranch-cost= 25Target RejectNegative Joined UInteger Var(riscv_branch_cost) 26-mbranch-cost=N Set the cost of branches to roughly N instructions. 27 28mplt 29Target Report Var(TARGET_PLT) Init(1) 30When generating -fpic code, allow the use of PLTs. Ignored for fno-pic. 31 32mabi= 33Target Report RejectNegative Joined Enum(abi_type) Var(riscv_abi) Init(ABI_ILP32) 34Specify integer and floating-point calling convention. 35 36mpreferred-stack-boundary= 37Target RejectNegative Joined UInteger Var(riscv_preferred_stack_boundary_arg) 38Attempt to keep stack aligned to this power of 2. 39 40Enum 41Name(abi_type) Type(enum riscv_abi_type) 42Supported ABIs (for use with the -mabi= option): 43 44EnumValue 45Enum(abi_type) String(ilp32) Value(ABI_ILP32) 46 47EnumValue 48Enum(abi_type) String(ilp32f) Value(ABI_ILP32F) 49 50EnumValue 51Enum(abi_type) String(ilp32d) Value(ABI_ILP32D) 52 53EnumValue 54Enum(abi_type) String(lp64) Value(ABI_LP64) 55 56EnumValue 57Enum(abi_type) String(lp64f) Value(ABI_LP64F) 58 59EnumValue 60Enum(abi_type) String(lp64d) Value(ABI_LP64D) 61 62mfdiv 63Target Report Mask(FDIV) 64Use hardware floating-point divide and square root instructions. 65 66mdiv 67Target Report Mask(DIV) 68Use hardware instructions for integer division. 69 70march= 71Target Report RejectNegative Joined 72-march= Generate code for given RISC-V ISA (e.g. RV64IM). ISA strings must be 73lower-case. 74 75mtune= 76Target RejectNegative Joined Var(riscv_tune_string) 77-mtune=PROCESSOR Optimize the output for PROCESSOR. 78 79msmall-data-limit= 80Target Joined Separate UInteger Var(g_switch_value) Init(8) 81-msmall-data-limit=N Put global and static data smaller than <number> bytes into a special section (on some targets). 82 83msave-restore 84Target Report Mask(SAVE_RESTORE) 85Use smaller but slower prologue and epilogue code. 86 87mcmodel= 88Target Report RejectNegative Joined Enum(code_model) Var(riscv_cmodel) Init(TARGET_DEFAULT_CMODEL) 89Specify the code model. 90 91mstrict-align 92Target Report Mask(STRICT_ALIGN) Save 93Do not generate unaligned memory accesses. 94 95Enum 96Name(code_model) Type(enum riscv_code_model) 97Known code models (for use with the -mcmodel= option): 98 99EnumValue 100Enum(code_model) String(medlow) Value(CM_MEDLOW) 101 102EnumValue 103Enum(code_model) String(medany) Value(CM_MEDANY) 104 105mexplicit-relocs 106Target Report Mask(EXPLICIT_RELOCS) 107Use %reloc() operators, rather than assembly macros, to load addresses. 108 109mrelax 110Target Bool Var(riscv_mrelax) Init(1) 111Take advantage of linker relaxations to reduce the number of instructions 112required to materialize symbol addresses. 113 114Mask(64BIT) 115 116Mask(MUL) 117 118Mask(ATOMIC) 119 120Mask(HARD_FLOAT) 121 122Mask(DOUBLE_FLOAT) 123 124Mask(RVC) 125