riscv.opt revision 1.1 
1; Options for the MIPS port of the compiler
2;
3; Copyright (C) 2005, 2007, 2008, 2010, 2011 Free Software Foundation, Inc.
4;
5; This file is part of GCC.
6;
7; GCC is free software; you can redistribute it and/or modify it under
8; the terms of the GNU General Public License as published by the Free
9; Software Foundation; either version 3, or (at your option) any later
10; version.
11;
12; GCC is distributed in the hope that it will be useful, but WITHOUT
13; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
15; License for more details.
16;
17; You should have received a copy of the GNU General Public License
18; along with GCC; see the file COPYING3.  If not see
19; <http://www.gnu.org/licenses/>.
20
21m32
22Target RejectNegative Mask(32BIT)
23Generate RV32 code
24
25m64
26Target RejectNegative InverseMask(32BIT, 64BIT)
27Generate RV64 code
28
29mbranch-cost=
30Target RejectNegative Joined UInteger Var(riscv_branch_cost)
31-mbranch-cost=COST	Set the cost of branches to roughly COST instructions
32
33mhard-float
34Target Report RejectNegative InverseMask(SOFT_FLOAT_ABI, HARD_FLOAT_ABI)
35Allow the use of hardware floating-point ABI and instructions
36
37mmemcpy
38Target Report Mask(MEMCPY)
39Don't optimize block moves
40
41mplt
42Target Report Var(TARGET_PLT) Init(1)
43When generating -fpic code, allow the use of PLTs. Ignored for fno-pic.
44
45msoft-float
46Target Report RejectNegative Mask(SOFT_FLOAT_ABI)
47Prevent the use of all hardware floating-point instructions
48
49mfdiv
50Target Report RejectNegative Mask(FDIV)
51Use hardware floating-point divide and square root instructions
52
53march=
54Target RejectNegative Joined Var(riscv_arch_string)
55-march=			Generate code for given RISC-V ISA (e.g. RV64IM)
56
57mtune=
58Target RejectNegative Joined Var(riscv_tune_string)
59-mtune=PROCESSOR	Optimize the output for PROCESSOR
60
61msmall-data-limit=
62Target Joined Separate UInteger Var(g_switch_value) Init(8)
63-msmall-data-limit=<number>	Put global and static data smaller than <number> bytes into a special section (on some targets)
64
65matomic
66Target Report Mask(ATOMIC)
67Use hardware atomic memory instructions.
68
69mmuldiv
70Target Report Mask(MULDIV)
71Use hardware instructions for integer multiplication and division.
72
73mlra
74Target Report Var(riscv_lra_flag) Init(0) Save
75Use LRA instead of reload
76
77mcmodel=
78Target RejectNegative Joined Var(riscv_cmodel_string)
79Use given RISC-V code model (medlow or medany)
80