riscv-c.c revision 1.1.1.1 
1/* RISC-V-specific code for C family languages.
2   Copyright (C) 2011-2017 Free Software Foundation, Inc.
3   Contributed by Andrew Waterman (andrew@sifive.com).
4
5This file is part of GCC.
6
7GCC is free software; you can redistribute it and/or modify
8it under the terms of the GNU General Public License as published by
9the Free Software Foundation; either version 3, or (at your option)
10any later version.
11
12GCC is distributed in the hope that it will be useful,
13but WITHOUT ANY WARRANTY; without even the implied warranty of
14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15GNU General Public License for more details.
16
17You should have received a copy of the GNU General Public License
18along with GCC; see the file COPYING3.  If not see
19<http://www.gnu.org/licenses/>.  */
20
21#include "config.h"
22#include "system.h"
23#include "coretypes.h"
24#include "tm.h"
25#include "c-family/c-common.h"
26#include "cpplib.h"
27
28#define builtin_define(TXT) cpp_define (pfile, TXT)
29
30/* Implement TARGET_CPU_CPP_BUILTINS.  */
31
32void
33riscv_cpu_cpp_builtins (cpp_reader *pfile)
34{
35  builtin_define ("__riscv");
36
37  if (TARGET_RVC)
38    builtin_define ("__riscv_compressed");
39
40  if (TARGET_ATOMIC)
41    builtin_define ("__riscv_atomic");
42
43  if (TARGET_MUL)
44    builtin_define ("__riscv_mul");
45  if (TARGET_DIV)
46    builtin_define ("__riscv_div");
47  if (TARGET_DIV && TARGET_MUL)
48    builtin_define ("__riscv_muldiv");
49
50  builtin_define_with_int_value ("__riscv_xlen", UNITS_PER_WORD * 8);
51  if (TARGET_HARD_FLOAT)
52    builtin_define_with_int_value ("__riscv_flen", UNITS_PER_FP_REG * 8);
53
54  if (TARGET_HARD_FLOAT && TARGET_FDIV)
55    {
56      builtin_define ("__riscv_fdiv");
57      builtin_define ("__riscv_fsqrt");
58    }
59
60  switch (riscv_abi)
61    {
62    case ABI_ILP32:
63    case ABI_LP64:
64      builtin_define ("__riscv_float_abi_soft");
65      break;
66
67    case ABI_ILP32F:
68    case ABI_LP64F:
69      builtin_define ("__riscv_float_abi_single");
70      break;
71
72    case ABI_ILP32D:
73    case ABI_LP64D:
74      builtin_define ("__riscv_float_abi_double");
75      break;
76    }
77
78  switch (riscv_cmodel)
79    {
80    case CM_MEDLOW:
81      builtin_define ("__riscv_cmodel_medlow");
82      break;
83
84    case CM_MEDANY:
85      builtin_define ("__riscv_cmodel_medany");
86      break;
87
88    case CM_PIC:
89      builtin_define ("__riscv_cmodel_pic");
90      break;
91    }
92}
93