pdp11.c revision 1.1.1.2
1/* Subroutines for gcc2 for pdp11. 2 Copyright (C) 1994-2013 Free Software Foundation, Inc. 3 Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at). 4 5This file is part of GCC. 6 7GCC is free software; you can redistribute it and/or modify 8it under the terms of the GNU General Public License as published by 9the Free Software Foundation; either version 3, or (at your option) 10any later version. 11 12GCC is distributed in the hope that it will be useful, 13but WITHOUT ANY WARRANTY; without even the implied warranty of 14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15GNU General Public License for more details. 16 17You should have received a copy of the GNU General Public License 18along with GCC; see the file COPYING3. If not see 19<http://www.gnu.org/licenses/>. */ 20 21#include "config.h" 22#include "system.h" 23#include "coretypes.h" 24#include "tm.h" 25#include "rtl.h" 26#include "regs.h" 27#include "hard-reg-set.h" 28#include "insn-config.h" 29#include "conditions.h" 30#include "function.h" 31#include "output.h" 32#include "insn-attr.h" 33#include "flags.h" 34#include "recog.h" 35#include "tree.h" 36#include "expr.h" 37#include "diagnostic-core.h" 38#include "tm_p.h" 39#include "target.h" 40#include "target-def.h" 41#include "df.h" 42#include "opts.h" 43 44/* this is the current value returned by the macro FIRST_PARM_OFFSET 45 defined in tm.h */ 46int current_first_parm_offset; 47 48/* Routines to encode/decode pdp11 floats */ 49static void encode_pdp11_f (const struct real_format *fmt, 50 long *, const REAL_VALUE_TYPE *); 51static void decode_pdp11_f (const struct real_format *, 52 REAL_VALUE_TYPE *, const long *); 53static void encode_pdp11_d (const struct real_format *fmt, 54 long *, const REAL_VALUE_TYPE *); 55static void decode_pdp11_d (const struct real_format *, 56 REAL_VALUE_TYPE *, const long *); 57 58/* These two are taken from the corresponding vax descriptors 59 in real.c, changing only the encode/decode routine pointers. */ 60const struct real_format pdp11_f_format = 61 { 62 encode_pdp11_f, 63 decode_pdp11_f, 64 2, 65 24, 66 24, 67 -127, 68 127, 69 15, 70 15, 71 false, 72 false, 73 false, 74 false, 75 false, 76 false, 77 false, 78 false 79 }; 80 81const struct real_format pdp11_d_format = 82 { 83 encode_pdp11_d, 84 decode_pdp11_d, 85 2, 86 56, 87 56, 88 -127, 89 127, 90 15, 91 15, 92 false, 93 false, 94 false, 95 false, 96 false, 97 false, 98 false, 99 false 100 }; 101 102static void 103encode_pdp11_f (const struct real_format *fmt ATTRIBUTE_UNUSED, long *buf, 104 const REAL_VALUE_TYPE *r) 105{ 106 (*vax_f_format.encode) (fmt, buf, r); 107 buf[0] = ((buf[0] >> 16) & 0xffff) | ((buf[0] & 0xffff) << 16); 108} 109 110static void 111decode_pdp11_f (const struct real_format *fmt ATTRIBUTE_UNUSED, 112 REAL_VALUE_TYPE *r, const long *buf) 113{ 114 long tbuf; 115 tbuf = ((buf[0] >> 16) & 0xffff) | ((buf[0] & 0xffff) << 16); 116 (*vax_f_format.decode) (fmt, r, &tbuf); 117} 118 119static void 120encode_pdp11_d (const struct real_format *fmt ATTRIBUTE_UNUSED, long *buf, 121 const REAL_VALUE_TYPE *r) 122{ 123 (*vax_d_format.encode) (fmt, buf, r); 124 buf[0] = ((buf[0] >> 16) & 0xffff) | ((buf[0] & 0xffff) << 16); 125 buf[1] = ((buf[1] >> 16) & 0xffff) | ((buf[1] & 0xffff) << 16); 126} 127 128static void 129decode_pdp11_d (const struct real_format *fmt ATTRIBUTE_UNUSED, 130 REAL_VALUE_TYPE *r, const long *buf) 131{ 132 long tbuf[2]; 133 tbuf[0] = ((buf[0] >> 16) & 0xffff) | ((buf[0] & 0xffff) << 16); 134 tbuf[1] = ((buf[1] >> 16) & 0xffff) | ((buf[1] & 0xffff) << 16); 135 (*vax_d_format.decode) (fmt, r, tbuf); 136} 137 138/* This is where the condition code register lives. */ 139/* rtx cc0_reg_rtx; - no longer needed? */ 140 141static const char *singlemove_string (rtx *); 142static bool pdp11_assemble_integer (rtx, unsigned int, int); 143static bool pdp11_rtx_costs (rtx, int, int, int, int *, bool); 144static bool pdp11_return_in_memory (const_tree, const_tree); 145static rtx pdp11_function_value (const_tree, const_tree, bool); 146static rtx pdp11_libcall_value (enum machine_mode, const_rtx); 147static bool pdp11_function_value_regno_p (const unsigned int); 148static void pdp11_trampoline_init (rtx, tree, rtx); 149static rtx pdp11_function_arg (cumulative_args_t, enum machine_mode, 150 const_tree, bool); 151static void pdp11_function_arg_advance (cumulative_args_t, 152 enum machine_mode, const_tree, bool); 153static void pdp11_conditional_register_usage (void); 154static bool pdp11_legitimate_constant_p (enum machine_mode, rtx); 155 156/* Initialize the GCC target structure. */ 157#undef TARGET_ASM_BYTE_OP 158#define TARGET_ASM_BYTE_OP NULL 159#undef TARGET_ASM_ALIGNED_HI_OP 160#define TARGET_ASM_ALIGNED_HI_OP NULL 161#undef TARGET_ASM_ALIGNED_SI_OP 162#define TARGET_ASM_ALIGNED_SI_OP NULL 163#undef TARGET_ASM_INTEGER 164#define TARGET_ASM_INTEGER pdp11_assemble_integer 165 166#undef TARGET_ASM_OPEN_PAREN 167#define TARGET_ASM_OPEN_PAREN "[" 168#undef TARGET_ASM_CLOSE_PAREN 169#define TARGET_ASM_CLOSE_PAREN "]" 170 171#undef TARGET_RTX_COSTS 172#define TARGET_RTX_COSTS pdp11_rtx_costs 173 174#undef TARGET_FUNCTION_ARG 175#define TARGET_FUNCTION_ARG pdp11_function_arg 176#undef TARGET_FUNCTION_ARG_ADVANCE 177#define TARGET_FUNCTION_ARG_ADVANCE pdp11_function_arg_advance 178 179#undef TARGET_RETURN_IN_MEMORY 180#define TARGET_RETURN_IN_MEMORY pdp11_return_in_memory 181 182#undef TARGET_FUNCTION_VALUE 183#define TARGET_FUNCTION_VALUE pdp11_function_value 184#undef TARGET_LIBCALL_VALUE 185#define TARGET_LIBCALL_VALUE pdp11_libcall_value 186#undef TARGET_FUNCTION_VALUE_REGNO_P 187#define TARGET_FUNCTION_VALUE_REGNO_P pdp11_function_value_regno_p 188 189#undef TARGET_TRAMPOLINE_INIT 190#define TARGET_TRAMPOLINE_INIT pdp11_trampoline_init 191 192#undef TARGET_SECONDARY_RELOAD 193#define TARGET_SECONDARY_RELOAD pdp11_secondary_reload 194 195#undef TARGET_REGISTER_MOVE_COST 196#define TARGET_REGISTER_MOVE_COST pdp11_register_move_cost 197 198#undef TARGET_PREFERRED_RELOAD_CLASS 199#define TARGET_PREFERRED_RELOAD_CLASS pdp11_preferred_reload_class 200 201#undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS 202#define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS pdp11_preferred_output_reload_class 203 204#undef TARGET_LEGITIMATE_ADDRESS_P 205#define TARGET_LEGITIMATE_ADDRESS_P pdp11_legitimate_address_p 206 207#undef TARGET_CONDITIONAL_REGISTER_USAGE 208#define TARGET_CONDITIONAL_REGISTER_USAGE pdp11_conditional_register_usage 209 210#undef TARGET_ASM_FUNCTION_SECTION 211#define TARGET_ASM_FUNCTION_SECTION pdp11_function_section 212 213#undef TARGET_PRINT_OPERAND 214#define TARGET_PRINT_OPERAND pdp11_asm_print_operand 215 216#undef TARGET_PRINT_OPERAND_PUNCT_VALID_P 217#define TARGET_PRINT_OPERAND_PUNCT_VALID_P pdp11_asm_print_operand_punct_valid_p 218 219#undef TARGET_LEGITIMATE_CONSTANT_P 220#define TARGET_LEGITIMATE_CONSTANT_P pdp11_legitimate_constant_p 221 222/* A helper function to determine if REGNO should be saved in the 223 current function's stack frame. */ 224 225static inline bool 226pdp11_saved_regno (unsigned regno) 227{ 228 return !call_used_regs[regno] && df_regs_ever_live_p (regno); 229} 230 231/* Expand the function prologue. */ 232 233void 234pdp11_expand_prologue (void) 235{ 236 HOST_WIDE_INT fsize = get_frame_size (); 237 unsigned regno; 238 rtx x, via_ac = NULL; 239 240 /* If we are outputting code for main, the switch FPU to the 241 right mode if TARGET_FPU. */ 242 if (MAIN_NAME_P (DECL_NAME (current_function_decl)) && TARGET_FPU) 243 { 244 emit_insn (gen_setd ()); 245 emit_insn (gen_seti ()); 246 } 247 248 if (frame_pointer_needed) 249 { 250 x = gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx); 251 x = gen_frame_mem (Pmode, x); 252 emit_move_insn (x, hard_frame_pointer_rtx); 253 254 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx); 255 } 256 257 /* Make frame. */ 258 if (fsize) 259 { 260 emit_insn (gen_addhi3 (stack_pointer_rtx, stack_pointer_rtx, 261 GEN_INT (-fsize))); 262 263 /* Prevent frame references via the frame pointer from being 264 scheduled before the frame is allocated. */ 265 if (frame_pointer_needed) 266 emit_insn (gen_blockage ()); 267 } 268 269 /* Save CPU registers. */ 270 for (regno = R0_REGNUM; regno <= PC_REGNUM; regno++) 271 if (pdp11_saved_regno (regno) 272 && (regno != HARD_FRAME_POINTER_REGNUM || !frame_pointer_needed)) 273 { 274 x = gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx); 275 x = gen_frame_mem (Pmode, x); 276 emit_move_insn (x, gen_rtx_REG (Pmode, regno)); 277 } 278 279 /* Save FPU registers. */ 280 for (regno = AC0_REGNUM; regno <= AC3_REGNUM; regno++) 281 if (pdp11_saved_regno (regno)) 282 { 283 x = gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx); 284 x = gen_frame_mem (DFmode, x); 285 via_ac = gen_rtx_REG (DFmode, regno); 286 emit_move_insn (x, via_ac); 287 } 288 289 /* ??? Maybe make ac4, ac5 call used regs?? */ 290 for (regno = AC4_REGNUM; regno <= AC5_REGNUM; regno++) 291 if (pdp11_saved_regno (regno)) 292 { 293 gcc_assert (via_ac != NULL); 294 emit_move_insn (via_ac, gen_rtx_REG (DFmode, regno)); 295 296 x = gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx); 297 x = gen_frame_mem (DFmode, x); 298 emit_move_insn (x, via_ac); 299 } 300} 301 302/* The function epilogue should not depend on the current stack pointer! 303 It should use the frame pointer only. This is mandatory because 304 of alloca; we also take advantage of it to omit stack adjustments 305 before returning. */ 306 307/* Maybe we can make leaf functions faster by switching to the 308 second register file - this way we don't have to save regs! 309 leaf functions are ~ 50% of all functions (dynamically!) 310 311 set/clear bit 11 (dec. 2048) of status word for switching register files - 312 but how can we do this? the pdp11/45 manual says bit may only 313 be set (p.24), but not cleared! 314 315 switching to kernel is probably more expensive, so we'll leave it 316 like this and not use the second set of registers... 317 318 maybe as option if you want to generate code for kernel mode? */ 319 320void 321pdp11_expand_epilogue (void) 322{ 323 HOST_WIDE_INT fsize = get_frame_size (); 324 unsigned regno; 325 rtx x, reg, via_ac = NULL; 326 327 if (pdp11_saved_regno (AC4_REGNUM) || pdp11_saved_regno (AC5_REGNUM)) 328 { 329 /* Find a temporary with which to restore AC4/5. */ 330 for (regno = AC0_REGNUM; regno <= AC3_REGNUM; regno++) 331 if (pdp11_saved_regno (regno)) 332 { 333 via_ac = gen_rtx_REG (DFmode, regno); 334 break; 335 } 336 } 337 338 /* If possible, restore registers via pops. */ 339 if (!frame_pointer_needed || crtl->sp_is_unchanging) 340 { 341 /* Restore registers via pops. */ 342 343 for (regno = AC5_REGNUM; regno >= AC0_REGNUM; regno--) 344 if (pdp11_saved_regno (regno)) 345 { 346 x = gen_rtx_POST_INC (Pmode, stack_pointer_rtx); 347 x = gen_frame_mem (DFmode, x); 348 reg = gen_rtx_REG (DFmode, regno); 349 350 if (LOAD_FPU_REG_P (regno)) 351 emit_move_insn (reg, x); 352 else 353 { 354 emit_move_insn (via_ac, x); 355 emit_move_insn (reg, via_ac); 356 } 357 } 358 359 for (regno = PC_REGNUM; regno >= R0_REGNUM + 2; regno--) 360 if (pdp11_saved_regno (regno) 361 && (regno != HARD_FRAME_POINTER_REGNUM || !frame_pointer_needed)) 362 { 363 x = gen_rtx_POST_INC (Pmode, stack_pointer_rtx); 364 x = gen_frame_mem (Pmode, x); 365 emit_move_insn (gen_rtx_REG (Pmode, regno), x); 366 } 367 } 368 else 369 { 370 /* Restore registers via moves. */ 371 /* ??? If more than a few registers need to be restored, it's smaller 372 to generate a pointer through which we can emit pops. Consider 373 that moves cost 2*NREG words and pops cost NREG+3 words. This 374 means that the crossover is NREG=3. 375 376 Possible registers to use are: 377 (1) The first call-saved general register. This register will 378 be restored with the last pop. 379 (2) R1, if it's not used as a return register. 380 (3) FP itself. This option may result in +4 words, since we 381 may need two add imm,rn instructions instead of just one. 382 This also has the downside that we're not representing 383 the unwind info in any way, so during the epilogue the 384 debugger may get lost. */ 385 386 HOST_WIDE_INT ofs = -pdp11_sp_frame_offset (); 387 388 for (regno = AC5_REGNUM; regno >= AC0_REGNUM; regno--) 389 if (pdp11_saved_regno (regno)) 390 { 391 x = plus_constant (Pmode, hard_frame_pointer_rtx, ofs); 392 x = gen_frame_mem (DFmode, x); 393 reg = gen_rtx_REG (DFmode, regno); 394 395 if (LOAD_FPU_REG_P (regno)) 396 emit_move_insn (reg, x); 397 else 398 { 399 emit_move_insn (via_ac, x); 400 emit_move_insn (reg, via_ac); 401 } 402 ofs += 8; 403 } 404 405 for (regno = PC_REGNUM; regno >= R0_REGNUM + 2; regno--) 406 if (pdp11_saved_regno (regno) 407 && (regno != HARD_FRAME_POINTER_REGNUM || !frame_pointer_needed)) 408 { 409 x = plus_constant (Pmode, hard_frame_pointer_rtx, ofs); 410 x = gen_frame_mem (Pmode, x); 411 emit_move_insn (gen_rtx_REG (Pmode, regno), x); 412 ofs += 2; 413 } 414 } 415 416 /* Deallocate the stack frame. */ 417 if (fsize) 418 { 419 /* Prevent frame references via any pointer from being 420 scheduled after the frame is deallocated. */ 421 emit_insn (gen_blockage ()); 422 423 if (frame_pointer_needed) 424 { 425 /* We can deallocate the frame with a single move. */ 426 emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx); 427 } 428 else 429 emit_insn (gen_addhi3 (stack_pointer_rtx, stack_pointer_rtx, 430 GEN_INT (fsize))); 431 } 432 433 if (frame_pointer_needed) 434 { 435 x = gen_rtx_POST_INC (Pmode, stack_pointer_rtx); 436 x = gen_frame_mem (Pmode, x); 437 emit_move_insn (hard_frame_pointer_rtx, x); 438 } 439 440 emit_jump_insn (gen_return ()); 441} 442 443/* Return the best assembler insn template 444 for moving operands[1] into operands[0] as a fullword. */ 445static const char * 446singlemove_string (rtx *operands) 447{ 448 if (operands[1] != const0_rtx) 449 return "mov %1,%0"; 450 451 return "clr %0"; 452} 453 454 455/* Expand multi-word operands (SImode or DImode) into the 2 or 4 456 corresponding HImode operands. The number of operands is given 457 as the third argument, and the required order of the parts as 458 the fourth argument. */ 459bool 460pdp11_expand_operands (rtx *operands, rtx exops[][2], int opcount, 461 pdp11_action *action, pdp11_partorder order) 462{ 463 int words, op, w, i, sh; 464 pdp11_partorder useorder; 465 bool sameoff = false; 466 enum { REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP } optype; 467 REAL_VALUE_TYPE r; 468 long sval[2]; 469 470 words = GET_MODE_BITSIZE (GET_MODE (operands[0])) / 16; 471 472 /* If either piece order is accepted and one is pre-decrement 473 while the other is post-increment, set order to be high order 474 word first. That will force the pre-decrement to be turned 475 into a pointer adjust, then offset addressing. 476 Otherwise, if either operand uses pre-decrement, that means 477 the order is low order first. 478 Otherwise, if both operands are registers and destination is 479 higher than source and they overlap, do low order word (highest 480 register number) first. */ 481 useorder = either; 482 if (opcount == 2) 483 { 484 if (!REG_P (operands[0]) && !REG_P (operands[1]) && 485 !(CONSTANT_P (operands[1]) || 486 GET_CODE (operands[1]) == CONST_DOUBLE) && 487 ((GET_CODE (XEXP (operands[0], 0)) == POST_INC && 488 GET_CODE (XEXP (operands[1], 0)) == PRE_DEC) || 489 (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC && 490 GET_CODE (XEXP (operands[1], 0)) == POST_INC))) 491 useorder = big; 492 else if ((!REG_P (operands[0]) && 493 GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) || 494 (!REG_P (operands[1]) && 495 !(CONSTANT_P (operands[1]) || 496 GET_CODE (operands[1]) == CONST_DOUBLE) && 497 GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)) 498 useorder = little; 499 else if (REG_P (operands[0]) && REG_P (operands[1]) && 500 REGNO (operands[0]) > REGNO (operands[1]) && 501 REGNO (operands[0]) < REGNO (operands[1]) + words) 502 useorder = little; 503 504 /* Check for source == offset from register and dest == push of 505 the same register. In that case, we have to use the same 506 offset (the one for the low order word) for all words, because 507 the push increases the offset to each source word. 508 In theory there are other cases like this, for example dest == pop, 509 but those don't occur in real life so ignore those. */ 510 if (GET_CODE (operands[0]) == MEM 511 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC 512 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM 513 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1])) 514 sameoff = true; 515 } 516 517 /* If the caller didn't specify order, use the one we computed, 518 or high word first if we don't care either. If the caller did 519 specify, verify we don't have a problem with that order. 520 (If it matters to the caller, constraints need to be used to 521 ensure this case doesn't occur). */ 522 if (order == either) 523 order = (useorder == either) ? big : useorder; 524 else 525 gcc_assert (useorder == either || useorder == order); 526 527 528 for (op = 0; op < opcount; op++) 529 { 530 /* First classify the operand. */ 531 if (REG_P (operands[op])) 532 optype = REGOP; 533 else if (CONSTANT_P (operands[op]) 534 || GET_CODE (operands[op]) == CONST_DOUBLE) 535 optype = CNSTOP; 536 else if (GET_CODE (XEXP (operands[op], 0)) == POST_INC) 537 optype = POPOP; 538 else if (GET_CODE (XEXP (operands[op], 0)) == PRE_DEC) 539 optype = PUSHOP; 540 else if (!reload_in_progress || offsettable_memref_p (operands[op])) 541 optype = OFFSOP; 542 else if (GET_CODE (operands[op]) == MEM) 543 optype = MEMOP; 544 else 545 optype = RNDOP; 546 547 /* Check for the cases that the operand constraints are not 548 supposed to allow to happen. Return failure for such cases. */ 549 if (optype == RNDOP) 550 return false; 551 552 if (action != NULL) 553 action[op] = no_action; 554 555 /* If the operand uses pre-decrement addressing but we 556 want to get the parts high order first, 557 decrement the former register explicitly 558 and change the operand into ordinary indexing. */ 559 if (optype == PUSHOP && order == big) 560 { 561 gcc_assert (action != NULL); 562 action[op] = dec_before; 563 operands[op] = gen_rtx_MEM (GET_MODE (operands[op]), 564 XEXP (XEXP (operands[op], 0), 0)); 565 optype = OFFSOP; 566 } 567 /* If the operand uses post-increment mode but we want 568 to get the parts low order first, change the operand 569 into ordinary indexing and remember to increment 570 the register explicitly when we're done. */ 571 else if (optype == POPOP && order == little) 572 { 573 gcc_assert (action != NULL); 574 action[op] = inc_after; 575 operands[op] = gen_rtx_MEM (GET_MODE (operands[op]), 576 XEXP (XEXP (operands[op], 0), 0)); 577 optype = OFFSOP; 578 } 579 580 if (GET_CODE (operands[op]) == CONST_DOUBLE) 581 { 582 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[op]); 583 REAL_VALUE_TO_TARGET_DOUBLE (r, sval); 584 } 585 586 for (i = 0; i < words; i++) 587 { 588 if (order == big) 589 w = i; 590 else if (sameoff) 591 w = words - 1; 592 else 593 w = words - 1 - i; 594 595 /* Set the output operand to be word "w" of the input. */ 596 if (optype == REGOP) 597 exops[i][op] = gen_rtx_REG (HImode, REGNO (operands[op]) + w); 598 else if (optype == OFFSOP) 599 exops[i][op] = adjust_address (operands[op], HImode, w * 2); 600 else if (optype == CNSTOP) 601 { 602 if (GET_CODE (operands[op]) == CONST_DOUBLE) 603 { 604 sh = 16 - (w & 1) * 16; 605 exops[i][op] = gen_rtx_CONST_INT (HImode, (sval[w / 2] >> sh) & 0xffff); 606 } 607 else 608 { 609 sh = ((words - 1 - w) * 16); 610 exops[i][op] = gen_rtx_CONST_INT (HImode, trunc_int_for_mode (INTVAL(operands[op]) >> sh, HImode)); 611 } 612 } 613 else 614 exops[i][op] = operands[op]; 615 } 616 } 617 return true; 618} 619 620/* Output assembler code to perform a multiple-word move insn 621 with operands OPERANDS. This moves 2 or 4 words depending 622 on the machine mode of the operands. */ 623 624const char * 625output_move_multiple (rtx *operands) 626{ 627 rtx exops[4][2]; 628 pdp11_action action[2]; 629 int i, words; 630 631 words = GET_MODE_BITSIZE (GET_MODE (operands[0])) / 16; 632 633 pdp11_expand_operands (operands, exops, 2, action, either); 634 635 /* Check for explicit decrement before. */ 636 if (action[0] == dec_before) 637 { 638 operands[0] = XEXP (operands[0], 0); 639 output_asm_insn ("sub $4,%0", operands); 640 } 641 if (action[1] == dec_before) 642 { 643 operands[1] = XEXP (operands[1], 0); 644 output_asm_insn ("sub $4,%1", operands); 645 } 646 647 /* Do the words. */ 648 for (i = 0; i < words; i++) 649 output_asm_insn (singlemove_string (exops[i]), exops[i]); 650 651 /* Check for increment after. */ 652 if (action[0] == inc_after) 653 { 654 operands[0] = XEXP (operands[0], 0); 655 output_asm_insn ("add $4,%0", operands); 656 } 657 if (action[1] == inc_after) 658 { 659 operands[1] = XEXP (operands[1], 0); 660 output_asm_insn ("add $4,%1", operands); 661 } 662 663 return ""; 664} 665 666/* Output an ascii string. */ 667void 668output_ascii (FILE *file, const char *p, int size) 669{ 670 int i; 671 672 /* This used to output .byte "string", which doesn't work with the UNIX 673 assembler and I think not with DEC ones either. */ 674 fprintf (file, "\t.byte "); 675 676 for (i = 0; i < size; i++) 677 { 678 register int c = p[i]; 679 if (c < 0) 680 c += 256; 681 fprintf (file, "%#o", c); 682 if (i < size - 1) 683 putc (',', file); 684 } 685 putc ('\n', file); 686} 687 688 689void 690pdp11_asm_output_var (FILE *file, const char *name, int size, 691 int align, bool global) 692{ 693 if (align > 8) 694 fprintf (file, "\n\t.even\n"); 695 if (global) 696 { 697 fprintf (file, ".globl "); 698 assemble_name (file, name); 699 } 700 fprintf (file, "\n"); 701 assemble_name (file, name); 702 fprintf (file, ": .=.+ %#ho\n", (unsigned short)size); 703} 704 705static void 706pdp11_asm_print_operand (FILE *file, rtx x, int code) 707{ 708 REAL_VALUE_TYPE r; 709 long sval[2]; 710 711 if (code == '#') 712 fprintf (file, "#"); 713 else if (code == '@') 714 { 715 if (TARGET_UNIX_ASM) 716 fprintf (file, "*"); 717 else 718 fprintf (file, "@"); 719 } 720 else if (GET_CODE (x) == REG) 721 fprintf (file, "%s", reg_names[REGNO (x)]); 722 else if (GET_CODE (x) == MEM) 723 output_address (XEXP (x, 0)); 724 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != SImode) 725 { 726 REAL_VALUE_FROM_CONST_DOUBLE (r, x); 727 REAL_VALUE_TO_TARGET_DOUBLE (r, sval); 728 fprintf (file, "$%#lo", sval[0] >> 16); 729 } 730 else 731 { 732 putc ('$', file); 733 output_addr_const_pdp11 (file, x); 734 } 735} 736 737static bool 738pdp11_asm_print_operand_punct_valid_p (unsigned char c) 739{ 740 return (c == '#' || c == '@'); 741} 742 743void 744print_operand_address (FILE *file, register rtx addr) 745{ 746 register rtx breg; 747 rtx offset; 748 int again = 0; 749 750 retry: 751 752 switch (GET_CODE (addr)) 753 { 754 case MEM: 755 if (TARGET_UNIX_ASM) 756 fprintf (file, "*"); 757 else 758 fprintf (file, "@"); 759 addr = XEXP (addr, 0); 760 again = 1; 761 goto retry; 762 763 case REG: 764 fprintf (file, "(%s)", reg_names[REGNO (addr)]); 765 break; 766 767 case PRE_MODIFY: 768 case PRE_DEC: 769 fprintf (file, "-(%s)", reg_names[REGNO (XEXP (addr, 0))]); 770 break; 771 772 case POST_MODIFY: 773 case POST_INC: 774 fprintf (file, "(%s)+", reg_names[REGNO (XEXP (addr, 0))]); 775 break; 776 777 case PLUS: 778 breg = 0; 779 offset = 0; 780 if (CONSTANT_ADDRESS_P (XEXP (addr, 0)) 781 || GET_CODE (XEXP (addr, 0)) == MEM) 782 { 783 offset = XEXP (addr, 0); 784 addr = XEXP (addr, 1); 785 } 786 else if (CONSTANT_ADDRESS_P (XEXP (addr, 1)) 787 || GET_CODE (XEXP (addr, 1)) == MEM) 788 { 789 offset = XEXP (addr, 1); 790 addr = XEXP (addr, 0); 791 } 792 if (GET_CODE (addr) != PLUS) 793 ; 794 else if (GET_CODE (XEXP (addr, 0)) == REG) 795 { 796 breg = XEXP (addr, 0); 797 addr = XEXP (addr, 1); 798 } 799 else if (GET_CODE (XEXP (addr, 1)) == REG) 800 { 801 breg = XEXP (addr, 1); 802 addr = XEXP (addr, 0); 803 } 804 if (GET_CODE (addr) == REG) 805 { 806 gcc_assert (breg == 0); 807 breg = addr; 808 addr = 0; 809 } 810 if (offset != 0) 811 { 812 gcc_assert (addr == 0); 813 addr = offset; 814 } 815 if (addr != 0) 816 output_addr_const_pdp11 (file, addr); 817 if (breg != 0) 818 { 819 gcc_assert (GET_CODE (breg) == REG); 820 fprintf (file, "(%s)", reg_names[REGNO (breg)]); 821 } 822 break; 823 824 default: 825 if (!again && GET_CODE (addr) == CONST_INT) 826 { 827 /* Absolute (integer number) address. */ 828 if (!TARGET_UNIX_ASM) 829 fprintf (file, "@$"); 830 } 831 output_addr_const_pdp11 (file, addr); 832 } 833} 834 835/* Target hook to assemble integer objects. We need to use the 836 pdp-specific version of output_addr_const. */ 837 838static bool 839pdp11_assemble_integer (rtx x, unsigned int size, int aligned_p) 840{ 841 if (aligned_p) 842 switch (size) 843 { 844 case 1: 845 fprintf (asm_out_file, "\t.byte\t"); 846 output_addr_const_pdp11 (asm_out_file, GEN_INT (INTVAL (x) & 0xff)); 847; 848 fprintf (asm_out_file, " /* char */\n"); 849 return true; 850 851 case 2: 852 fprintf (asm_out_file, TARGET_UNIX_ASM ? "\t" : "\t.word\t"); 853 output_addr_const_pdp11 (asm_out_file, x); 854 fprintf (asm_out_file, " /* short */\n"); 855 return true; 856 } 857 return default_assemble_integer (x, size, aligned_p); 858} 859 860 861/* register move costs, indexed by regs */ 862 863static const int move_costs[N_REG_CLASSES][N_REG_CLASSES] = 864{ 865 /* NO MUL GEN LFPU NLFPU FPU ALL */ 866 867/* NO */ { 0, 0, 0, 0, 0, 0, 0}, 868/* MUL */ { 0, 2, 2, 22, 22, 22, 22}, 869/* GEN */ { 0, 2, 2, 22, 22, 22, 22}, 870/* LFPU */ { 0, 22, 22, 2, 2, 2, 22}, 871/* NLFPU */ { 0, 22, 22, 2, 10, 10, 22}, 872/* FPU */ { 0, 22, 22, 2, 10, 10, 22}, 873/* ALL */ { 0, 22, 22, 22, 22, 22, 22} 874} ; 875 876 877/* -- note that some moves are tremendously expensive, 878 because they require lots of tricks! do we have to 879 charge the costs incurred by secondary reload class 880 -- as we do here with 10 -- or not ? */ 881 882static int 883pdp11_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED, 884 reg_class_t c1, reg_class_t c2) 885{ 886 return move_costs[(int)c1][(int)c2]; 887} 888 889static bool 890pdp11_rtx_costs (rtx x, int code, int outer_code ATTRIBUTE_UNUSED, 891 int opno ATTRIBUTE_UNUSED, int *total, 892 bool speed ATTRIBUTE_UNUSED) 893{ 894 switch (code) 895 { 896 case CONST_INT: 897 if (INTVAL (x) == 0 || INTVAL (x) == -1 || INTVAL (x) == 1) 898 { 899 *total = 0; 900 return true; 901 } 902 /* FALLTHRU */ 903 904 case CONST: 905 case LABEL_REF: 906 case SYMBOL_REF: 907 /* Twice as expensive as REG. */ 908 *total = 2; 909 return true; 910 911 case CONST_DOUBLE: 912 /* Twice (or 4 times) as expensive as 16 bit. */ 913 *total = 4; 914 return true; 915 916 case MULT: 917 /* ??? There is something wrong in MULT because MULT is not 918 as cheap as total = 2 even if we can shift! */ 919 /* If optimizing for size make mult etc cheap, but not 1, so when 920 in doubt the faster insn is chosen. */ 921 if (optimize_size) 922 *total = COSTS_N_INSNS (2); 923 else 924 *total = COSTS_N_INSNS (11); 925 return false; 926 927 case DIV: 928 if (optimize_size) 929 *total = COSTS_N_INSNS (2); 930 else 931 *total = COSTS_N_INSNS (25); 932 return false; 933 934 case MOD: 935 if (optimize_size) 936 *total = COSTS_N_INSNS (2); 937 else 938 *total = COSTS_N_INSNS (26); 939 return false; 940 941 case ABS: 942 /* Equivalent to length, so same for optimize_size. */ 943 *total = COSTS_N_INSNS (3); 944 return false; 945 946 case ZERO_EXTEND: 947 /* Only used for qi->hi. */ 948 *total = COSTS_N_INSNS (1); 949 return false; 950 951 case SIGN_EXTEND: 952 if (GET_MODE (x) == HImode) 953 *total = COSTS_N_INSNS (1); 954 else if (GET_MODE (x) == SImode) 955 *total = COSTS_N_INSNS (6); 956 else 957 *total = COSTS_N_INSNS (2); 958 return false; 959 960 case ASHIFT: 961 case LSHIFTRT: 962 case ASHIFTRT: 963 if (optimize_size) 964 *total = COSTS_N_INSNS (1); 965 else if (GET_MODE (x) == QImode) 966 { 967 if (GET_CODE (XEXP (x, 1)) != CONST_INT) 968 *total = COSTS_N_INSNS (8); /* worst case */ 969 else 970 *total = COSTS_N_INSNS (INTVAL (XEXP (x, 1))); 971 } 972 else if (GET_MODE (x) == HImode) 973 { 974 if (GET_CODE (XEXP (x, 1)) == CONST_INT) 975 { 976 if (abs (INTVAL (XEXP (x, 1))) == 1) 977 *total = COSTS_N_INSNS (1); 978 else 979 *total = COSTS_N_INSNS (2.5 + 0.5 * INTVAL (XEXP (x, 1))); 980 } 981 else 982 *total = COSTS_N_INSNS (10); /* worst case */ 983 } 984 else if (GET_MODE (x) == SImode) 985 { 986 if (GET_CODE (XEXP (x, 1)) == CONST_INT) 987 *total = COSTS_N_INSNS (2.5 + 0.5 * INTVAL (XEXP (x, 1))); 988 else /* worst case */ 989 *total = COSTS_N_INSNS (18); 990 } 991 return false; 992 993 default: 994 return false; 995 } 996} 997 998const char * 999output_jump (enum rtx_code code, int inv, int length) 1000{ 1001 static int x = 0; 1002 1003 static char buf[1000]; 1004 const char *pos, *neg; 1005 1006 if (cc_prev_status.flags & CC_NO_OVERFLOW) 1007 { 1008 switch (code) 1009 { 1010 case GTU: code = GT; break; 1011 case LTU: code = LT; break; 1012 case GEU: code = GE; break; 1013 case LEU: code = LE; break; 1014 default: ; 1015 } 1016 } 1017 switch (code) 1018 { 1019 case EQ: pos = "beq", neg = "bne"; break; 1020 case NE: pos = "bne", neg = "beq"; break; 1021 case GT: pos = "bgt", neg = "ble"; break; 1022 case GTU: pos = "bhi", neg = "blos"; break; 1023 case LT: pos = "blt", neg = "bge"; break; 1024 case LTU: pos = "blo", neg = "bhis"; break; 1025 case GE: pos = "bge", neg = "blt"; break; 1026 case GEU: pos = "bhis", neg = "blo"; break; 1027 case LE: pos = "ble", neg = "bgt"; break; 1028 case LEU: pos = "blos", neg = "bhi"; break; 1029 default: gcc_unreachable (); 1030 } 1031 1032#if 0 1033/* currently we don't need this, because the tstdf and cmpdf 1034 copy the condition code immediately, and other float operations are not 1035 yet recognized as changing the FCC - if so, then the length-cost of all 1036 jump insns increases by one, because we have to potentially copy the 1037 FCC! */ 1038 if (cc_status.flags & CC_IN_FPU) 1039 output_asm_insn("cfcc", NULL); 1040#endif 1041 1042 switch (length) 1043 { 1044 case 2: 1045 1046 sprintf(buf, "%s %%l1", inv ? neg : pos); 1047 1048 return buf; 1049 1050 case 6: 1051 1052 sprintf(buf, "%s JMP_%d\n\tjmp %%l1\nJMP_%d:", inv ? pos : neg, x, x); 1053 1054 x++; 1055 1056 return buf; 1057 1058 default: 1059 1060 gcc_unreachable (); 1061 } 1062 1063} 1064 1065void 1066notice_update_cc_on_set(rtx exp, rtx insn ATTRIBUTE_UNUSED) 1067{ 1068 if (GET_CODE (SET_DEST (exp)) == CC0) 1069 { 1070 cc_status.flags = 0; 1071 cc_status.value1 = SET_DEST (exp); 1072 cc_status.value2 = SET_SRC (exp); 1073 } 1074 else if (GET_CODE (SET_SRC (exp)) == CALL) 1075 { 1076 CC_STATUS_INIT; 1077 } 1078 else if (SET_DEST(exp) == pc_rtx) 1079 { 1080 /* jump */ 1081 } 1082 else if (GET_MODE (SET_DEST(exp)) == HImode 1083 || GET_MODE (SET_DEST(exp)) == QImode) 1084 { 1085 cc_status.flags = GET_CODE (SET_SRC(exp)) == MINUS ? 0 : CC_NO_OVERFLOW; 1086 cc_status.value1 = SET_SRC (exp); 1087 cc_status.value2 = SET_DEST (exp); 1088 1089 if (cc_status.value1 && GET_CODE (cc_status.value1) == REG 1090 && cc_status.value2 1091 && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2)) 1092 cc_status.value2 = 0; 1093 if (cc_status.value1 && GET_CODE (cc_status.value1) == MEM 1094 && cc_status.value2 1095 && GET_CODE (cc_status.value2) == MEM) 1096 cc_status.value2 = 0; 1097 } 1098 else 1099 { 1100 CC_STATUS_INIT; 1101 } 1102} 1103 1104 1105int 1106simple_memory_operand(rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 1107{ 1108 rtx addr; 1109 1110 /* Eliminate non-memory operations */ 1111 if (GET_CODE (op) != MEM) 1112 return FALSE; 1113 1114#if 0 1115 /* dword operations really put out 2 instructions, so eliminate them. */ 1116 if (GET_MODE_SIZE (GET_MODE (op)) > (HAVE_64BIT_P () ? 8 : 4)) 1117 return FALSE; 1118#endif 1119 1120 /* Decode the address now. */ 1121 1122 indirection: 1123 1124 addr = XEXP (op, 0); 1125 1126 switch (GET_CODE (addr)) 1127 { 1128 case REG: 1129 /* (R0) - no extra cost */ 1130 return 1; 1131 1132 case PRE_DEC: 1133 case POST_INC: 1134 /* -(R0), (R0)+ - cheap! */ 1135 return 0; 1136 1137 case MEM: 1138 /* cheap - is encoded in addressing mode info! 1139 1140 -- except for @(R0), which has to be @0(R0) !!! */ 1141 1142 if (GET_CODE (XEXP (addr, 0)) == REG) 1143 return 0; 1144 1145 op=addr; 1146 goto indirection; 1147 1148 case CONST_INT: 1149 case LABEL_REF: 1150 case CONST: 1151 case SYMBOL_REF: 1152 /* @#address - extra cost */ 1153 return 0; 1154 1155 case PLUS: 1156 /* X(R0) - extra cost */ 1157 return 0; 1158 1159 default: 1160 break; 1161 } 1162 1163 return FALSE; 1164} 1165 1166 1167/* 1168 * output a block move: 1169 * 1170 * operands[0] ... to 1171 * operands[1] ... from 1172 * operands[2] ... length 1173 * operands[3] ... alignment 1174 * operands[4] ... scratch register 1175 */ 1176 1177 1178const char * 1179output_block_move(rtx *operands) 1180{ 1181 static int count = 0; 1182 char buf[200]; 1183 int unroll; 1184 int lastbyte = 0; 1185 1186 /* Move of zero bytes is a NOP. */ 1187 if (operands[2] == const0_rtx) 1188 return ""; 1189 1190 /* Look for moves by small constant byte counts, those we'll 1191 expand to straight line code. */ 1192 if (CONSTANT_P (operands[2])) 1193 { 1194 if (INTVAL (operands[2]) < 16 1195 && (!optimize_size || INTVAL (operands[2]) < 5) 1196 && INTVAL (operands[3]) == 1) 1197 { 1198 register int i; 1199 1200 for (i = 1; i <= INTVAL (operands[2]); i++) 1201 output_asm_insn("movb (%1)+, (%0)+", operands); 1202 1203 return ""; 1204 } 1205 else if (INTVAL(operands[2]) < 32 1206 && (!optimize_size || INTVAL (operands[2]) < 9) 1207 && INTVAL (operands[3]) >= 2) 1208 { 1209 register int i; 1210 1211 for (i = 1; i <= INTVAL (operands[2]) / 2; i++) 1212 output_asm_insn ("mov (%1)+, (%0)+", operands); 1213 if (INTVAL (operands[2]) & 1) 1214 output_asm_insn ("movb (%1), (%0)", operands); 1215 1216 return ""; 1217 } 1218 } 1219 1220 /* Ideally we'd look for moves that are multiples of 4 or 8 1221 bytes and handle those by unrolling the move loop. That 1222 makes for a lot of code if done at run time, but it's ok 1223 for constant counts. Also, for variable counts we have 1224 to worry about odd byte count with even aligned pointers. 1225 On 11/40 and up we handle that case; on older machines 1226 we don't and just use byte-wise moves all the time. */ 1227 1228 if (CONSTANT_P (operands[2]) ) 1229 { 1230 if (INTVAL (operands[3]) < 2) 1231 unroll = 0; 1232 else 1233 { 1234 lastbyte = INTVAL (operands[2]) & 1; 1235 1236 if (optimize_size || INTVAL (operands[2]) & 2) 1237 unroll = 1; 1238 else if (INTVAL (operands[2]) & 4) 1239 unroll = 2; 1240 else 1241 unroll = 3; 1242 } 1243 1244 /* Loop count is byte count scaled by unroll. */ 1245 operands[2] = GEN_INT (INTVAL (operands[2]) >> unroll); 1246 output_asm_insn ("mov %2, %4", operands); 1247 } 1248 else 1249 { 1250 /* Variable byte count; use the input register 1251 as the scratch. */ 1252 operands[4] = operands[2]; 1253 1254 /* Decide whether to move by words, and check 1255 the byte count for zero. */ 1256 if (TARGET_40_PLUS && INTVAL (operands[3]) > 1) 1257 { 1258 unroll = 1; 1259 output_asm_insn ("asr %4", operands); 1260 } 1261 else 1262 { 1263 unroll = 0; 1264 output_asm_insn ("tst %4", operands); 1265 } 1266 sprintf (buf, "beq movestrhi%d", count + 1); 1267 output_asm_insn (buf, NULL); 1268 } 1269 1270 /* Output the loop label. */ 1271 sprintf (buf, "\nmovestrhi%d:", count); 1272 output_asm_insn (buf, NULL); 1273 1274 /* Output the appropriate move instructions. */ 1275 switch (unroll) 1276 { 1277 case 0: 1278 output_asm_insn ("movb (%1)+, (%0)+", operands); 1279 break; 1280 1281 case 1: 1282 output_asm_insn ("mov (%1)+, (%0)+", operands); 1283 break; 1284 1285 case 2: 1286 output_asm_insn ("mov (%1)+, (%0)+", operands); 1287 output_asm_insn ("mov (%1)+, (%0)+", operands); 1288 break; 1289 1290 default: 1291 output_asm_insn ("mov (%1)+, (%0)+", operands); 1292 output_asm_insn ("mov (%1)+, (%0)+", operands); 1293 output_asm_insn ("mov (%1)+, (%0)+", operands); 1294 output_asm_insn ("mov (%1)+, (%0)+", operands); 1295 break; 1296 } 1297 1298 /* Output the decrement and test. */ 1299 if (TARGET_40_PLUS) 1300 { 1301 sprintf (buf, "sob %%4, movestrhi%d", count); 1302 output_asm_insn (buf, operands); 1303 } 1304 else 1305 { 1306 output_asm_insn ("dec %4", operands); 1307 sprintf (buf, "bgt movestrhi%d", count); 1308 output_asm_insn (buf, NULL); 1309 } 1310 count ++; 1311 1312 /* If constant odd byte count, move the last byte. */ 1313 if (lastbyte) 1314 output_asm_insn ("movb (%1), (%0)", operands); 1315 else if (!CONSTANT_P (operands[2])) 1316 { 1317 /* Output the destination label for the zero byte count check. */ 1318 sprintf (buf, "\nmovestrhi%d:", count); 1319 output_asm_insn (buf, NULL); 1320 count++; 1321 1322 /* If we did word moves, check for trailing last byte. */ 1323 if (unroll) 1324 { 1325 sprintf (buf, "bcc movestrhi%d", count); 1326 output_asm_insn (buf, NULL); 1327 output_asm_insn ("movb (%1), (%0)", operands); 1328 sprintf (buf, "\nmovestrhi%d:", count); 1329 output_asm_insn (buf, NULL); 1330 count++; 1331 } 1332 } 1333 1334 return ""; 1335} 1336 1337/* This function checks whether a real value can be encoded as 1338 a literal, i.e., addressing mode 27. In that mode, real values 1339 are one word values, so the remaining 48 bits have to be zero. */ 1340int 1341legitimate_const_double_p (rtx address) 1342{ 1343 REAL_VALUE_TYPE r; 1344 long sval[2]; 1345 REAL_VALUE_FROM_CONST_DOUBLE (r, address); 1346 REAL_VALUE_TO_TARGET_DOUBLE (r, sval); 1347 if ((sval[0] & 0xffff) == 0 && sval[1] == 0) 1348 return 1; 1349 return 0; 1350} 1351 1352/* Implement CANNOT_CHANGE_MODE_CLASS. */ 1353bool 1354pdp11_cannot_change_mode_class (enum machine_mode from, 1355 enum machine_mode to, 1356 enum reg_class rclass) 1357{ 1358 /* Also, FPU registers contain a whole float value and the parts of 1359 it are not separately accessible. 1360 1361 So we disallow all mode changes involving FPRs. */ 1362 if (FLOAT_MODE_P (from) != FLOAT_MODE_P (to)) 1363 return true; 1364 1365 return reg_classes_intersect_p (FPU_REGS, rclass); 1366} 1367 1368/* TARGET_PREFERRED_RELOAD_CLASS 1369 1370 Given an rtx X being reloaded into a reg required to be 1371 in class CLASS, return the class of reg to actually use. 1372 In general this is just CLASS; but on some machines 1373 in some cases it is preferable to use a more restrictive class. 1374 1375loading is easier into LOAD_FPU_REGS than FPU_REGS! */ 1376 1377static reg_class_t 1378pdp11_preferred_reload_class (rtx x, reg_class_t rclass) 1379{ 1380 if (rclass == FPU_REGS) 1381 return LOAD_FPU_REGS; 1382 if (rclass == ALL_REGS) 1383 { 1384 if (FLOAT_MODE_P (GET_MODE (x))) 1385 return LOAD_FPU_REGS; 1386 else 1387 return GENERAL_REGS; 1388 } 1389 return rclass; 1390} 1391 1392/* TARGET_PREFERRED_OUTPUT_RELOAD_CLASS 1393 1394 Given an rtx X being reloaded into a reg required to be 1395 in class CLASS, return the class of reg to actually use. 1396 In general this is just CLASS; but on some machines 1397 in some cases it is preferable to use a more restrictive class. 1398 1399loading is easier into LOAD_FPU_REGS than FPU_REGS! */ 1400 1401static reg_class_t 1402pdp11_preferred_output_reload_class (rtx x, reg_class_t rclass) 1403{ 1404 if (rclass == FPU_REGS) 1405 return LOAD_FPU_REGS; 1406 if (rclass == ALL_REGS) 1407 { 1408 if (FLOAT_MODE_P (GET_MODE (x))) 1409 return LOAD_FPU_REGS; 1410 else 1411 return GENERAL_REGS; 1412 } 1413 return rclass; 1414} 1415 1416 1417/* TARGET_SECONDARY_RELOAD. 1418 1419 FPU registers AC4 and AC5 (class NO_LOAD_FPU_REGS) require an 1420 intermediate register (AC0-AC3: LOAD_FPU_REGS). Everything else 1421 can be loade/stored directly. */ 1422static reg_class_t 1423pdp11_secondary_reload (bool in_p ATTRIBUTE_UNUSED, 1424 rtx x, 1425 reg_class_t reload_class, 1426 enum machine_mode reload_mode ATTRIBUTE_UNUSED, 1427 secondary_reload_info *sri ATTRIBUTE_UNUSED) 1428{ 1429 if (reload_class != NO_LOAD_FPU_REGS || GET_CODE (x) != REG || 1430 REGNO_REG_CLASS (REGNO (x)) == LOAD_FPU_REGS) 1431 return NO_REGS; 1432 1433 return LOAD_FPU_REGS; 1434} 1435 1436/* Target routine to check if register to register move requires memory. 1437 1438 The answer is yes if we're going between general register and FPU 1439 registers. The mode doesn't matter in making this check. 1440*/ 1441bool 1442pdp11_secondary_memory_needed (reg_class_t c1, reg_class_t c2, 1443 enum machine_mode mode ATTRIBUTE_UNUSED) 1444{ 1445 int fromfloat = (c1 == LOAD_FPU_REGS || c1 == NO_LOAD_FPU_REGS || 1446 c1 == FPU_REGS); 1447 int tofloat = (c2 == LOAD_FPU_REGS || c2 == NO_LOAD_FPU_REGS || 1448 c2 == FPU_REGS); 1449 1450 return (fromfloat != tofloat); 1451} 1452 1453/* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression 1454 that is a valid memory address for an instruction. 1455 The MODE argument is the machine mode for the MEM expression 1456 that wants to use this address. 1457 1458*/ 1459 1460static bool 1461pdp11_legitimate_address_p (enum machine_mode mode, 1462 rtx operand, bool strict) 1463{ 1464 rtx xfoob; 1465 1466 /* accept @#address */ 1467 if (CONSTANT_ADDRESS_P (operand)) 1468 return true; 1469 1470 switch (GET_CODE (operand)) 1471 { 1472 case REG: 1473 /* accept (R0) */ 1474 return !strict || REGNO_OK_FOR_BASE_P (REGNO (operand)); 1475 1476 case PLUS: 1477 /* accept X(R0) */ 1478 return GET_CODE (XEXP (operand, 0)) == REG 1479 && (!strict || REGNO_OK_FOR_BASE_P (REGNO (XEXP (operand, 0)))) 1480 && CONSTANT_ADDRESS_P (XEXP (operand, 1)); 1481 1482 case PRE_DEC: 1483 /* accept -(R0) */ 1484 return GET_CODE (XEXP (operand, 0)) == REG 1485 && (!strict || REGNO_OK_FOR_BASE_P (REGNO (XEXP (operand, 0)))); 1486 1487 case POST_INC: 1488 /* accept (R0)+ */ 1489 return GET_CODE (XEXP (operand, 0)) == REG 1490 && (!strict || REGNO_OK_FOR_BASE_P (REGNO (XEXP (operand, 0)))); 1491 1492 case PRE_MODIFY: 1493 /* accept -(SP) -- which uses PRE_MODIFY for byte mode */ 1494 return GET_CODE (XEXP (operand, 0)) == REG 1495 && REGNO (XEXP (operand, 0)) == STACK_POINTER_REGNUM 1496 && GET_CODE ((xfoob = XEXP (operand, 1))) == PLUS 1497 && GET_CODE (XEXP (xfoob, 0)) == REG 1498 && REGNO (XEXP (xfoob, 0)) == STACK_POINTER_REGNUM 1499 && CONSTANT_P (XEXP (xfoob, 1)) 1500 && INTVAL (XEXP (xfoob,1)) == -2; 1501 1502 case POST_MODIFY: 1503 /* accept (SP)+ -- which uses POST_MODIFY for byte mode */ 1504 return GET_CODE (XEXP (operand, 0)) == REG 1505 && REGNO (XEXP (operand, 0)) == STACK_POINTER_REGNUM 1506 && GET_CODE ((xfoob = XEXP (operand, 1))) == PLUS 1507 && GET_CODE (XEXP (xfoob, 0)) == REG 1508 && REGNO (XEXP (xfoob, 0)) == STACK_POINTER_REGNUM 1509 && CONSTANT_P (XEXP (xfoob, 1)) 1510 && INTVAL (XEXP (xfoob,1)) == 2; 1511 1512 case MEM: 1513 /* handle another level of indirection ! */ 1514 xfoob = XEXP (operand, 0); 1515 1516 /* (MEM:xx (MEM:xx ())) is not valid for SI, DI and currently 1517 also forbidden for float, because we have to handle this 1518 in output_move_double and/or output_move_quad() - we could 1519 do it, but currently it's not worth it!!! 1520 now that DFmode cannot go into CPU register file, 1521 maybe I should allow float ... 1522 but then I have to handle memory-to-memory moves in movdf ?? */ 1523 if (GET_MODE_BITSIZE(mode) > 16) 1524 return false; 1525 1526 /* accept @address */ 1527 if (CONSTANT_ADDRESS_P (xfoob)) 1528 return true; 1529 1530 switch (GET_CODE (xfoob)) 1531 { 1532 case REG: 1533 /* accept @(R0) - which is @0(R0) */ 1534 return !strict || REGNO_OK_FOR_BASE_P(REGNO (xfoob)); 1535 1536 case PLUS: 1537 /* accept @X(R0) */ 1538 return GET_CODE (XEXP (xfoob, 0)) == REG 1539 && (!strict || REGNO_OK_FOR_BASE_P (REGNO (XEXP (xfoob, 0)))) 1540 && CONSTANT_ADDRESS_P (XEXP (xfoob, 1)); 1541 1542 case PRE_DEC: 1543 /* accept @-(R0) */ 1544 return GET_CODE (XEXP (xfoob, 0)) == REG 1545 && (!strict || REGNO_OK_FOR_BASE_P (REGNO (XEXP (xfoob, 0)))); 1546 1547 case POST_INC: 1548 /* accept @(R0)+ */ 1549 return GET_CODE (XEXP (xfoob, 0)) == REG 1550 && (!strict || REGNO_OK_FOR_BASE_P (REGNO (XEXP (xfoob, 0)))); 1551 1552 default: 1553 /* anything else is invalid */ 1554 return false; 1555 } 1556 1557 default: 1558 /* anything else is invalid */ 1559 return false; 1560 } 1561} 1562 1563/* Return the class number of the smallest class containing 1564 reg number REGNO. */ 1565enum reg_class 1566pdp11_regno_reg_class (int regno) 1567{ 1568 if (regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM) 1569 return GENERAL_REGS; 1570 else if (regno > AC3_REGNUM) 1571 return NO_LOAD_FPU_REGS; 1572 else if (regno >= AC0_REGNUM) 1573 return LOAD_FPU_REGS; 1574 else if (regno & 1) 1575 return MUL_REGS; 1576 else 1577 return GENERAL_REGS; 1578} 1579 1580 1581int 1582pdp11_sp_frame_offset (void) 1583{ 1584 int offset = 0, regno; 1585 offset = get_frame_size(); 1586 for (regno = 0; regno <= PC_REGNUM; regno++) 1587 if (pdp11_saved_regno (regno)) 1588 offset += 2; 1589 for (regno = AC0_REGNUM; regno <= AC5_REGNUM; regno++) 1590 if (pdp11_saved_regno (regno)) 1591 offset += 8; 1592 1593 return offset; 1594} 1595 1596/* Return the offset between two registers, one to be eliminated, and the other 1597 its replacement, at the start of a routine. */ 1598 1599int 1600pdp11_initial_elimination_offset (int from, int to) 1601{ 1602 int spoff; 1603 1604 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM) 1605 return 4; 1606 else if (from == FRAME_POINTER_REGNUM 1607 && to == HARD_FRAME_POINTER_REGNUM) 1608 return 0; 1609 else 1610 { 1611 gcc_assert (to == STACK_POINTER_REGNUM); 1612 1613 /* Get the size of the register save area. */ 1614 spoff = pdp11_sp_frame_offset (); 1615 if (from == FRAME_POINTER_REGNUM) 1616 return spoff; 1617 1618 gcc_assert (from == ARG_POINTER_REGNUM); 1619 1620 /* If there is a frame pointer, that is saved too. */ 1621 if (frame_pointer_needed) 1622 spoff += 2; 1623 1624 /* Account for the saved PC in the function call. */ 1625 return spoff + 2; 1626 } 1627} 1628 1629/* A copy of output_addr_const modified for pdp11 expression syntax. 1630 output_addr_const also gets called for %cDIGIT and %nDIGIT, which we don't 1631 use, and for debugging output, which we don't support with this port either. 1632 So this copy should get called whenever needed. 1633*/ 1634void 1635output_addr_const_pdp11 (FILE *file, rtx x) 1636{ 1637 char buf[256]; 1638 int i; 1639 1640 restart: 1641 switch (GET_CODE (x)) 1642 { 1643 case PC: 1644 gcc_assert (flag_pic); 1645 putc ('.', file); 1646 break; 1647 1648 case SYMBOL_REF: 1649 assemble_name (file, XSTR (x, 0)); 1650 break; 1651 1652 case LABEL_REF: 1653 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (x, 0))); 1654 assemble_name (file, buf); 1655 break; 1656 1657 case CODE_LABEL: 1658 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x)); 1659 assemble_name (file, buf); 1660 break; 1661 1662 case CONST_INT: 1663 i = INTVAL (x); 1664 if (i < 0) 1665 { 1666 i = -i; 1667 fprintf (file, "-"); 1668 } 1669 fprintf (file, "%#o", i & 0xffff); 1670 break; 1671 1672 case CONST: 1673 /* This used to output parentheses around the expression, 1674 but that does not work on the 386 (either ATT or BSD assembler). */ 1675 output_addr_const_pdp11 (file, XEXP (x, 0)); 1676 break; 1677 1678 case CONST_DOUBLE: 1679 if (GET_MODE (x) == VOIDmode) 1680 { 1681 /* We can use %o if the number is one word and positive. */ 1682 gcc_assert (!CONST_DOUBLE_HIGH (x)); 1683 fprintf (file, "%#ho", (unsigned short) CONST_DOUBLE_LOW (x)); 1684 } 1685 else 1686 /* We can't handle floating point constants; 1687 PRINT_OPERAND must handle them. */ 1688 output_operand_lossage ("floating constant misused"); 1689 break; 1690 1691 case PLUS: 1692 /* Some assemblers need integer constants to appear last (e.g. masm). */ 1693 if (GET_CODE (XEXP (x, 0)) == CONST_INT) 1694 { 1695 output_addr_const_pdp11 (file, XEXP (x, 1)); 1696 if (INTVAL (XEXP (x, 0)) >= 0) 1697 fprintf (file, "+"); 1698 output_addr_const_pdp11 (file, XEXP (x, 0)); 1699 } 1700 else 1701 { 1702 output_addr_const_pdp11 (file, XEXP (x, 0)); 1703 if (INTVAL (XEXP (x, 1)) >= 0) 1704 fprintf (file, "+"); 1705 output_addr_const_pdp11 (file, XEXP (x, 1)); 1706 } 1707 break; 1708 1709 case MINUS: 1710 /* Avoid outputting things like x-x or x+5-x, 1711 since some assemblers can't handle that. */ 1712 x = simplify_subtraction (x); 1713 if (GET_CODE (x) != MINUS) 1714 goto restart; 1715 1716 output_addr_const_pdp11 (file, XEXP (x, 0)); 1717 if (GET_CODE (XEXP (x, 1)) != CONST_INT 1718 || INTVAL (XEXP (x, 1)) >= 0) 1719 fprintf (file, "-"); 1720 output_addr_const_pdp11 (file, XEXP (x, 1)); 1721 break; 1722 1723 case ZERO_EXTEND: 1724 case SIGN_EXTEND: 1725 output_addr_const_pdp11 (file, XEXP (x, 0)); 1726 break; 1727 1728 default: 1729 output_operand_lossage ("invalid expression as operand"); 1730 } 1731} 1732 1733/* Worker function for TARGET_RETURN_IN_MEMORY. */ 1734 1735static bool 1736pdp11_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) 1737{ 1738 /* Integers 32 bits and under, and scalar floats (if FPU), are returned 1739 in registers. The rest go into memory. */ 1740 return (TYPE_MODE (type) == DImode 1741 || (FLOAT_MODE_P (TYPE_MODE (type)) && ! TARGET_AC0) 1742 || TREE_CODE (type) == VECTOR_TYPE 1743 || COMPLEX_MODE_P (TYPE_MODE (type))); 1744} 1745 1746/* Worker function for TARGET_FUNCTION_VALUE. 1747 1748 On the pdp11 the value is found in R0 (or ac0??? not without FPU!!!! ) */ 1749 1750static rtx 1751pdp11_function_value (const_tree valtype, 1752 const_tree fntype_or_decl ATTRIBUTE_UNUSED, 1753 bool outgoing ATTRIBUTE_UNUSED) 1754{ 1755 return gen_rtx_REG (TYPE_MODE (valtype), 1756 BASE_RETURN_VALUE_REG(TYPE_MODE(valtype))); 1757} 1758 1759/* Worker function for TARGET_LIBCALL_VALUE. */ 1760 1761static rtx 1762pdp11_libcall_value (enum machine_mode mode, 1763 const_rtx fun ATTRIBUTE_UNUSED) 1764{ 1765 return gen_rtx_REG (mode, BASE_RETURN_VALUE_REG(mode)); 1766} 1767 1768/* Worker function for TARGET_FUNCTION_VALUE_REGNO_P. 1769 1770 On the pdp, the first "output" reg is the only register thus used. 1771 1772 maybe ac0 ? - as option someday! */ 1773 1774static bool 1775pdp11_function_value_regno_p (const unsigned int regno) 1776{ 1777 return (regno == RETVAL_REGNUM) || (TARGET_AC0 && (regno == AC0_REGNUM)); 1778} 1779 1780/* Worker function for TARGET_TRAMPOLINE_INIT. 1781 1782 trampoline - how should i do it in separate i+d ? 1783 have some allocate_trampoline magic??? 1784 1785 the following should work for shared I/D: 1786 1787 MOV #STATIC, $4 01270Y 0x0000 <- STATIC; Y = STATIC_CHAIN_REGNUM 1788 JMP @#FUNCTION 000137 0x0000 <- FUNCTION 1789*/ 1790 1791static void 1792pdp11_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) 1793{ 1794 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0); 1795 rtx mem; 1796 1797 gcc_assert (!TARGET_SPLIT); 1798 1799 mem = adjust_address (m_tramp, HImode, 0); 1800 emit_move_insn (mem, GEN_INT (012700+STATIC_CHAIN_REGNUM)); 1801 mem = adjust_address (m_tramp, HImode, 2); 1802 emit_move_insn (mem, chain_value); 1803 mem = adjust_address (m_tramp, HImode, 4); 1804 emit_move_insn (mem, GEN_INT (000137)); 1805 emit_move_insn (mem, fnaddr); 1806} 1807 1808/* Worker function for TARGET_FUNCTION_ARG. 1809 1810 Determine where to put an argument to a function. 1811 Value is zero to push the argument on the stack, 1812 or a hard register in which to store the argument. 1813 1814 MODE is the argument's machine mode. 1815 TYPE is the data type of the argument (as a tree). 1816 This is null for libcalls where that information may 1817 not be available. 1818 CUM is a variable of type CUMULATIVE_ARGS which gives info about 1819 the preceding args and about the function being called. 1820 NAMED is nonzero if this argument is a named parameter 1821 (otherwise it is an extra parameter matching an ellipsis). */ 1822 1823static rtx 1824pdp11_function_arg (cumulative_args_t cum ATTRIBUTE_UNUSED, 1825 enum machine_mode mode ATTRIBUTE_UNUSED, 1826 const_tree type ATTRIBUTE_UNUSED, 1827 bool named ATTRIBUTE_UNUSED) 1828{ 1829 return NULL_RTX; 1830} 1831 1832/* Worker function for TARGET_FUNCTION_ARG_ADVANCE. 1833 1834 Update the data in CUM to advance over an argument of mode MODE and 1835 data type TYPE. (TYPE is null for libcalls where that information 1836 may not be available.) */ 1837 1838static void 1839pdp11_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode, 1840 const_tree type, bool named ATTRIBUTE_UNUSED) 1841{ 1842 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); 1843 1844 *cum += (mode != BLKmode 1845 ? GET_MODE_SIZE (mode) 1846 : int_size_in_bytes (type)); 1847} 1848 1849/* Make sure everything's fine if we *don't* have an FPU. 1850 This assumes that putting a register in fixed_regs will keep the 1851 compiler's mitts completely off it. We don't bother to zero it out 1852 of register classes. Also fix incompatible register naming with 1853 the UNIX assembler. */ 1854 1855static void 1856pdp11_conditional_register_usage (void) 1857{ 1858 int i; 1859 HARD_REG_SET x; 1860 if (!TARGET_FPU) 1861 { 1862 COPY_HARD_REG_SET (x, reg_class_contents[(int)FPU_REGS]); 1863 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) 1864 if (TEST_HARD_REG_BIT (x, i)) 1865 fixed_regs[i] = call_used_regs[i] = 1; 1866 } 1867 1868 if (TARGET_AC0) 1869 call_used_regs[AC0_REGNUM] = 1; 1870 if (TARGET_UNIX_ASM) 1871 { 1872 /* Change names of FPU registers for the UNIX assembler. */ 1873 reg_names[8] = "fr0"; 1874 reg_names[9] = "fr1"; 1875 reg_names[10] = "fr2"; 1876 reg_names[11] = "fr3"; 1877 reg_names[12] = "fr4"; 1878 reg_names[13] = "fr5"; 1879 } 1880} 1881 1882static section * 1883pdp11_function_section (tree decl ATTRIBUTE_UNUSED, 1884 enum node_frequency freq ATTRIBUTE_UNUSED, 1885 bool startup ATTRIBUTE_UNUSED, 1886 bool exit ATTRIBUTE_UNUSED) 1887{ 1888 return NULL; 1889} 1890 1891/* Implement TARGET_LEGITIMATE_CONSTANT_P. */ 1892 1893static bool 1894pdp11_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x) 1895{ 1896 return GET_CODE (x) != CONST_DOUBLE || legitimate_const_double_p (x); 1897} 1898 1899struct gcc_target targetm = TARGET_INITIALIZER; 1900