nds32.opt revision 1.4 
1; Options of Andes NDS32 cpu for GNU compiler
2; Copyright (C) 2012-2018 Free Software Foundation, Inc.
3; Contributed by Andes Technology Corporation.
4;
5; This file is part of GCC.
6;
7; GCC is free software; you can redistribute it and/or modify it
8; under the terms of the GNU General Public License as published
9; by the Free Software Foundation; either version 3, or (at your
10; option) any later version.
11;
12; GCC is distributed in the hope that it will be useful, but WITHOUT
13; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
15; License for more details.
16;
17; You should have received a copy of the GNU General Public License
18; along with GCC; see the file COPYING3.  If not see
19; <http://www.gnu.org/licenses/>.
20
21HeaderInclude
22config/nds32/nds32-opts.h
23
24; ---------------------------------------------------------------
25; The following options are designed for aliasing and compatibility options.
26
27EB
28Target RejectNegative Alias(mbig-endian)
29Generate code in big-endian mode.
30
31EL
32Target RejectNegative Alias(mlittle-endian)
33Generate code in little-endian mode.
34
35
36; ---------------------------------------------------------------
37
38mabi=
39Target RejectNegative Joined Enum(abi_type) Var(nds32_abi) Init(TARGET_DEFAULT_ABI)
40Specify which ABI type to generate code for: 2, 2fp+.
41
42Enum
43Name(abi_type) Type(enum abi_type)
44Known ABIs (for use with the -mabi= option):
45
46EnumValue
47Enum(abi_type) String(2) Value(NDS32_ABI_V2)
48
49EnumValue
50Enum(abi_type) String(2fp+) Value(NDS32_ABI_V2_FP_PLUS)
51
52mfloat-abi=soft
53Target RejectNegative Alias(mabi=, 2)
54Specify use soft floating point ABI which mean alias to -mabi=2.
55
56mfloat-abi=hard
57Target RejectNegative Alias(mabi=, 2fp+)
58Specify use soft floating point ABI which mean alias to -mabi=2fp+.
59
60; ---------------------------------------------------------------
61
62mreduced-regs
63Target Report RejectNegative Negative(mfull-regs) Mask(REDUCED_REGS)
64Use reduced-set registers for register allocation.
65
66mfull-regs
67Target Report RejectNegative Negative(mreduced-regs) InverseMask(REDUCED_REGS)
68Use full-set registers for register allocation.
69
70; ---------------------------------------------------------------
71
72malways-align
73Target Mask(ALWAYS_ALIGN)
74Always align function entry, jump target and return address.
75
76malign-functions
77Target Mask(ALIGN_FUNCTION)
78Align function entry to 4 byte.
79
80mbig-endian
81Target Undocumented RejectNegative Negative(mlittle-endian) Mask(BIG_ENDIAN)
82Generate code in big-endian mode.
83
84mlittle-endian
85Target Undocumented RejectNegative Negative(mbig-endian) InverseMask(BIG_ENDIAN)
86Generate code in little-endian mode.
87
88
89mcmov
90Target Report Mask(CMOV)
91Generate conditional move instructions.
92
93mext-perf
94Target Report Mask(EXT_PERF)
95Generate performance extension instructions.
96
97mext-perf2
98Target Report Mask(EXT_PERF2)
99Generate performance extension version 2 instructions.
100
101mext-string
102Target Report Mask(EXT_STRING)
103Generate string extension instructions.
104
105mv3push
106Target Report Mask(V3PUSH)
107Generate v3 push25/pop25 instructions.
108
109m16-bit
110Target Report Mask(16_BIT)
111Generate 16-bit instructions.
112
113mrelax-hint
114Target Report Mask(RELAX_HINT)
115Insert relax hint for linker to do relaxation.
116
117mvh
118Target Report Mask(VH)
119Enable Virtual Hosting support.
120
121misr-vector-size=
122Target RejectNegative Joined UInteger Var(nds32_isr_vector_size) Init(NDS32_DEFAULT_ISR_VECTOR_SIZE)
123Specify the size of each interrupt vector, which must be 4 or 16.
124
125mcache-block-size=
126Target RejectNegative Joined UInteger Var(nds32_cache_block_size) Init(NDS32_DEFAULT_CACHE_BLOCK_SIZE)
127Specify the size of each cache block, which must be a power of 2 between 4 and 512.
128
129march=
130Target RejectNegative Joined Enum(nds32_arch_type) Var(nds32_arch_option) Init(ARCH_V3)
131Specify the name of the target architecture.
132
133Enum
134Name(nds32_arch_type) Type(enum nds32_arch_type)
135Known arch types (for use with the -march= option):
136
137EnumValue
138Enum(nds32_arch_type) String(v2) Value(ARCH_V2)
139
140EnumValue
141Enum(nds32_arch_type) String(v3) Value(ARCH_V3)
142
143EnumValue
144Enum(nds32_arch_type) String(v3m) Value(ARCH_V3M)
145
146EnumValue
147Enum(nds32_arch_type) String(v3f) Value(ARCH_V3F)
148
149EnumValue
150Enum(nds32_arch_type) String(v3s) Value(ARCH_V3S)
151
152mcmodel=
153Target RejectNegative Joined Enum(nds32_cmodel_type) Var(nds32_cmodel_option) Init(CMODEL_LARGE)
154Specify the address generation strategy for code model.
155
156Enum
157Name(nds32_cmodel_type) Type(enum nds32_cmodel_type)
158Known cmodel types (for use with the -mcmodel= option):
159
160EnumValue
161Enum(nds32_cmodel_type) String(small) Value(CMODEL_SMALL)
162
163EnumValue
164Enum(nds32_cmodel_type) String(medium) Value(CMODEL_MEDIUM)
165
166EnumValue
167Enum(nds32_cmodel_type) String(large) Value(CMODEL_LARGE)
168
169mcpu=
170Target RejectNegative Joined Enum(nds32_cpu_type) Var(nds32_cpu_option) Init(CPU_N9)
171Specify the cpu for pipeline model.
172
173Enum
174Name(nds32_cpu_type) Type(enum nds32_cpu_type)
175Known cpu types (for use with the -mcpu= option):
176
177EnumValue
178Enum(nds32_cpu_type) String(n6) Value(CPU_N6)
179
180EnumValue
181Enum(nds32_cpu_type) String(n650) Value(CPU_N6)
182
183EnumValue
184Enum(nds32_cpu_type) String(n7) Value(CPU_N7)
185
186EnumValue
187Enum(nds32_cpu_type) String(n705) Value(CPU_N7)
188
189EnumValue
190Enum(nds32_cpu_type) String(n8) Value(CPU_N8)
191
192EnumValue
193Enum(nds32_cpu_type) String(n801) Value(CPU_N8)
194
195EnumValue
196Enum(nds32_cpu_type) String(sn8) Value(CPU_N8)
197
198EnumValue
199Enum(nds32_cpu_type) String(sn801) Value(CPU_N8)
200
201EnumValue
202Enum(nds32_cpu_type) String(s8) Value(CPU_N8)
203
204EnumValue
205Enum(nds32_cpu_type) String(s801) Value(CPU_N8)
206
207EnumValue
208Enum(nds32_cpu_type) String(e8) Value(CPU_E8)
209
210EnumValue
211Enum(nds32_cpu_type) String(e801) Value(CPU_E8)
212
213EnumValue
214Enum(nds32_cpu_type) String(n820) Value(CPU_E8)
215
216EnumValue
217Enum(nds32_cpu_type) String(s830) Value(CPU_E8)
218
219EnumValue
220Enum(nds32_cpu_type) String(e830) Value(CPU_E8)
221
222EnumValue
223Enum(nds32_cpu_type) String(n9) Value(CPU_N9)
224
225EnumValue
226Enum(nds32_cpu_type) String(n903) Value(CPU_N9)
227
228EnumValue
229Enum(nds32_cpu_type) String(n903a) Value(CPU_N9)
230
231EnumValue
232Enum(nds32_cpu_type) String(n968) Value(CPU_N9)
233
234EnumValue
235Enum(nds32_cpu_type) String(n968a) Value(CPU_N9)
236
237EnumValue
238Enum(nds32_cpu_type) String(simple) Value(CPU_SIMPLE)
239
240mconfig-fpu=
241Target RejectNegative Joined Enum(float_reg_number) Var(nds32_fp_regnum) Init(TARGET_CONFIG_FPU_DEFAULT)
242Specify a fpu configuration value from 0 to 7; 0-3 is as FPU spec says, and 4-7 is corresponding to 0-3.
243
244Enum
245Name(float_reg_number) Type(enum float_reg_number)
246Known floating-point number of registers (for use with the -mconfig-fpu= option):
247
248EnumValue
249Enum(float_reg_number) String(0) Value(NDS32_CONFIG_FPU_0)
250
251EnumValue
252Enum(float_reg_number) String(1) Value(NDS32_CONFIG_FPU_1)
253
254EnumValue
255Enum(float_reg_number) String(2) Value(NDS32_CONFIG_FPU_2)
256
257EnumValue
258Enum(float_reg_number) String(3) Value(NDS32_CONFIG_FPU_3)
259
260EnumValue
261Enum(float_reg_number) String(4) Value(NDS32_CONFIG_FPU_4)
262
263EnumValue
264Enum(float_reg_number) String(5) Value(NDS32_CONFIG_FPU_5)
265
266EnumValue
267Enum(float_reg_number) String(6) Value(NDS32_CONFIG_FPU_6)
268
269EnumValue
270Enum(float_reg_number) String(7) Value(NDS32_CONFIG_FPU_7)
271
272mconfig-mul=
273Target RejectNegative Joined Enum(nds32_mul_type) Var(nds32_mul_config) Init(MUL_TYPE_FAST_1)
274Specify configuration of instruction mul: fast1, fast2 or slow. The default is fast1.
275
276Enum
277Name(nds32_mul_type) Type(enum nds32_mul_type)
278
279EnumValue
280Enum(nds32_mul_type) String(fast) Value(MUL_TYPE_FAST_1)
281
282EnumValue
283Enum(nds32_mul_type) String(fast1) Value(MUL_TYPE_FAST_1)
284
285EnumValue
286Enum(nds32_mul_type) String(fast2) Value(MUL_TYPE_FAST_2)
287
288EnumValue
289Enum(nds32_mul_type) String(slow) Value(MUL_TYPE_SLOW)
290
291mconfig-register-ports=
292Target RejectNegative Joined Enum(nds32_register_ports) Var(nds32_register_ports_config) Init(REG_PORT_3R2W)
293Specify how many read/write ports for n9/n10 cores.  The value should be 3r2w or 2r1w.
294
295Enum
296Name(nds32_register_ports) Type(enum nds32_register_ports)
297
298EnumValue
299Enum(nds32_register_ports) String(3r2w) Value(REG_PORT_3R2W)
300
301EnumValue
302Enum(nds32_register_ports) String(2r1w) Value(REG_PORT_2R1W)
303
304mctor-dtor
305Target Report
306Enable constructor/destructor feature.
307
308mrelax
309Target Report
310Guide linker to relax instructions.
311
312mext-fpu-fma
313Target Report Mask(EXT_FPU_FMA)
314Generate floating-point multiply-accumulation instructions.
315
316mext-fpu-sp
317Target Report Mask(FPU_SINGLE)
318Generate single-precision floating-point instructions.
319
320mext-fpu-dp
321Target Report Mask(FPU_DOUBLE)
322Generate double-precision floating-point instructions.
323
324malways-save-lp
325Target Var(flag_always_save_lp) Init(0)
326Always save $lp in the stack.
327
328munaligned-access
329Target Report Var(flag_unaligned_access) Init(0)
330Enable unaligned word and halfword accesses to packed data.
331