mcore.h revision 1.1.1.2
1/* Definitions of target machine for GNU compiler, 2 for Motorola M*CORE Processor. 3 Copyright (C) 1993-2013 Free Software Foundation, Inc. 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify it 8 under the terms of the GNU General Public License as published 9 by the Free Software Foundation; either version 3, or (at your 10 option) any later version. 11 12 GCC is distributed in the hope that it will be useful, but WITHOUT 13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15 License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GCC; see the file COPYING3. If not see 19 <http://www.gnu.org/licenses/>. */ 20 21#ifndef GCC_MCORE_H 22#define GCC_MCORE_H 23 24/* RBE: need to move these elsewhere. */ 25#undef LIKE_PPC_ABI 26#define MCORE_STRUCT_ARGS 27/* RBE: end of "move elsewhere". */ 28 29/* Run-time Target Specification. */ 30#define TARGET_MCORE 31 32/* Get tree.c to declare a target-specific specialization of 33 merge_decl_attributes. */ 34#define TARGET_DLLIMPORT_DECL_ATTRIBUTES 1 35 36#define TARGET_CPU_CPP_BUILTINS() \ 37 do \ 38 { \ 39 builtin_define ("__mcore__"); \ 40 builtin_define ("__MCORE__"); \ 41 if (TARGET_LITTLE_END) \ 42 builtin_define ("__MCORELE__"); \ 43 else \ 44 builtin_define ("__MCOREBE__"); \ 45 if (TARGET_M340) \ 46 builtin_define ("__M340__"); \ 47 else \ 48 builtin_define ("__M210__"); \ 49 } \ 50 while (0) 51 52#undef CPP_SPEC 53#define CPP_SPEC "%{m210:%{mlittle-endian:%ethe m210 does not have little endian support}}" 54 55/* We don't have a -lg library, so don't put it in the list. */ 56#undef LIB_SPEC 57#define LIB_SPEC "%{!shared: %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}}" 58 59#undef ASM_SPEC 60#define ASM_SPEC "%{mbig-endian:-EB} %{m210:-cpu=210 -EB}" 61 62#undef LINK_SPEC 63#define LINK_SPEC "%{mbig-endian:-EB} %{m210:-EB} -X" 64 65#define TARGET_DEFAULT \ 66 (MASK_HARDLIT \ 67 | MASK_DIV \ 68 | MASK_RELAX_IMM \ 69 | MASK_M340 \ 70 | MASK_LITTLE_END) 71 72#ifndef MULTILIB_DEFAULTS 73#define MULTILIB_DEFAULTS { "mlittle-endian", "m340" } 74#endif 75 76/* The ability to have 4 byte alignment is being suppressed for now. 77 If this ability is reenabled, you must disable the definition below 78 *and* edit t-mcore to enable multilibs for 4 byte alignment code. */ 79#undef TARGET_8ALIGN 80#define TARGET_8ALIGN 1 81 82extern char * mcore_current_function_name; 83 84/* The MCore ABI says that bitfields are unsigned by default. */ 85#define CC1_SPEC "-funsigned-bitfields" 86 87/* Target machine storage Layout. */ 88 89#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ 90 if (GET_MODE_CLASS (MODE) == MODE_INT \ 91 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ 92 { \ 93 (MODE) = SImode; \ 94 (UNSIGNEDP) = 1; \ 95 } 96 97/* Define this if most significant bit is lowest numbered 98 in instructions that operate on numbered bit-fields. */ 99#define BITS_BIG_ENDIAN 0 100 101/* Define this if most significant byte of a word is the lowest numbered. */ 102#define BYTES_BIG_ENDIAN (! TARGET_LITTLE_END) 103 104/* Define this if most significant word of a multiword number is the lowest 105 numbered. */ 106#define WORDS_BIG_ENDIAN (! TARGET_LITTLE_END) 107 108#define MAX_BITS_PER_WORD 32 109 110/* Width of a word, in units (bytes). */ 111#define UNITS_PER_WORD 4 112 113/* A C expression for the size in bits of the type `long long' on the 114 target machine. If you don't define this, the default is two 115 words. */ 116#define LONG_LONG_TYPE_SIZE 64 117 118/* Allocation boundary (in *bits*) for storing arguments in argument list. */ 119#define PARM_BOUNDARY 32 120 121/* Boundary (in *bits*) on which stack pointer should be aligned. */ 122#define STACK_BOUNDARY (TARGET_8ALIGN ? 64 : 32) 123 124/* Largest increment in UNITS we allow the stack to grow in a single operation. */ 125#define STACK_UNITS_MAXSTEP 4096 126 127/* Allocation boundary (in *bits*) for the code of a function. */ 128#define FUNCTION_BOUNDARY ((TARGET_OVERALIGN_FUNC) ? 32 : 16) 129 130/* Alignment of field after `int : 0' in a structure. */ 131#define EMPTY_FIELD_BOUNDARY 32 132 133/* No data type wants to be aligned rounder than this. */ 134#define BIGGEST_ALIGNMENT (TARGET_8ALIGN ? 64 : 32) 135 136/* The best alignment to use in cases where we have a choice. */ 137#define FASTEST_ALIGNMENT 32 138 139/* Every structures size must be a multiple of 8 bits. */ 140#define STRUCTURE_SIZE_BOUNDARY 8 141 142/* Look at the fundamental type that is used for a bit-field and use 143 that to impose alignment on the enclosing structure. 144 struct s {int a:8}; should have same alignment as "int", not "char". */ 145#define PCC_BITFIELD_TYPE_MATTERS 1 146 147/* Largest integer machine mode for structures. If undefined, the default 148 is GET_MODE_SIZE(DImode). */ 149#define MAX_FIXED_MODE_SIZE 32 150 151/* Make strings word-aligned so strcpy from constants will be faster. */ 152#define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 153 ((TREE_CODE (EXP) == STRING_CST \ 154 && (ALIGN) < FASTEST_ALIGNMENT) \ 155 ? FASTEST_ALIGNMENT : (ALIGN)) 156 157/* Make arrays of chars word-aligned for the same reasons. */ 158#define DATA_ALIGNMENT(TYPE, ALIGN) \ 159 (TREE_CODE (TYPE) == ARRAY_TYPE \ 160 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ 161 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) 162 163/* Set this nonzero if move instructions will actually fail to work 164 when given unaligned data. */ 165#define STRICT_ALIGNMENT 1 166 167/* Standard register usage. */ 168 169/* Register allocation for our first guess 170 171 r0 stack pointer 172 r1 scratch, target reg for xtrb? 173 r2-r7 arguments. 174 r8-r14 call saved 175 r15 link register 176 ap arg pointer (doesn't really exist, always eliminated) 177 c c bit 178 fp frame pointer (doesn't really exist, always eliminated) 179 x19 two control registers. */ 180 181/* Number of actual hardware registers. 182 The hardware registers are assigned numbers for the compiler 183 from 0 to just below FIRST_PSEUDO_REGISTER. 184 All registers that the compiler knows about must be given numbers, 185 even those that are not normally considered general registers. 186 187 MCore has 16 integer registers and 2 control registers + the arg 188 pointer. */ 189 190#define FIRST_PSEUDO_REGISTER 20 191 192#define R1_REG 1 /* Where literals are forced. */ 193#define LK_REG 15 /* Overloaded on general register. */ 194#define AP_REG 16 /* Fake arg pointer register. */ 195/* RBE: mcore.md depends on CC_REG being set to 17. */ 196#define CC_REG 17 /* Can't name it C_REG. */ 197#define FP_REG 18 /* Fake frame pointer register. */ 198 199/* Specify the registers used for certain standard purposes. 200 The values of these macros are register numbers. */ 201 202 203#undef PC_REGNUM /* Define this if the program counter is overloaded on a register. */ 204#define STACK_POINTER_REGNUM 0 /* Register to use for pushing function arguments. */ 205#define FRAME_POINTER_REGNUM 8 /* When we need FP, use r8. */ 206 207/* The assembler's names for the registers. RFP need not always be used as 208 the Real framepointer; it can also be used as a normal general register. 209 Note that the name `fp' is horribly misleading since `fp' is in fact only 210 the argument-and-return-context pointer. */ 211#define REGISTER_NAMES \ 212{ \ 213 "sp", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ 214 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ 215 "apvirtual", "c", "fpvirtual", "x19" \ 216} 217 218/* 1 for registers that have pervasive standard uses 219 and are not available for the register allocator. */ 220#define FIXED_REGISTERS \ 221 /* r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 ap c fp x19 */ \ 222 { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1} 223 224/* 1 for registers not available across function calls. 225 These must include the FIXED_REGISTERS and also any 226 registers that can be used without being saved. 227 The latter must include the registers where values are returned 228 and the register where structure-value addresses are passed. 229 Aside from that, you can include as many other registers as you like. */ 230 231/* RBE: r15 {link register} not available across calls, 232 But we don't mark it that way here.... */ 233#define CALL_USED_REGISTERS \ 234 /* r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 ap c fp x19 */ \ 235 { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1} 236 237/* The order in which register should be allocated. */ 238#define REG_ALLOC_ORDER \ 239 /* r7 r6 r5 r4 r3 r2 r15 r14 r13 r12 r11 r10 r9 r8 r1 r0 ap c fp x19*/ \ 240 { 7, 6, 5, 4, 3, 2, 15, 14, 13, 12, 11, 10, 9, 8, 1, 0, 16, 17, 18, 19} 241 242/* Return number of consecutive hard regs needed starting at reg REGNO 243 to hold something of mode MODE. 244 This is ordinarily the length in words of a value of mode MODE 245 but can be less for certain modes in special long registers. 246 247 On the MCore regs are UNITS_PER_WORD bits wide; */ 248#define HARD_REGNO_NREGS(REGNO, MODE) \ 249 (((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 250 251/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. 252 We may keep double values in even registers. */ 253#define HARD_REGNO_MODE_OK(REGNO, MODE) \ 254 ((TARGET_8ALIGN && GET_MODE_SIZE (MODE) > UNITS_PER_WORD) ? (((REGNO) & 1) == 0) : (REGNO < 18)) 255 256/* Value is 1 if it is a good idea to tie two pseudo registers 257 when one has mode MODE1 and one has mode MODE2. 258 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 259 for any hard reg, then this must be 0 for correct output. */ 260#define MODES_TIEABLE_P(MODE1, MODE2) \ 261 ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2)) 262 263/* Definitions for register eliminations. 264 265 We have two registers that can be eliminated on the MCore. First, the 266 frame pointer register can often be eliminated in favor of the stack 267 pointer register. Secondly, the argument pointer register can always be 268 eliminated; it is replaced with either the stack or frame pointer. */ 269 270/* Base register for access to arguments of the function. */ 271#define ARG_POINTER_REGNUM 16 272 273/* Register in which the static-chain is passed to a function. */ 274#define STATIC_CHAIN_REGNUM 1 275 276/* This is an array of structures. Each structure initializes one pair 277 of eliminable registers. The "from" register number is given first, 278 followed by "to". Eliminations of the same "from" register are listed 279 in order of preference. */ 280#define ELIMINABLE_REGS \ 281{{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 282 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 283 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},} 284 285/* Define the offset between two registers, one to be eliminated, and the other 286 its replacement, at the start of a routine. */ 287#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 288 OFFSET = mcore_initial_elimination_offset (FROM, TO) 289 290/* Define the classes of registers for register constraints in the 291 machine description. Also define ranges of constants. 292 293 One of the classes must always be named ALL_REGS and include all hard regs. 294 If there is more than one class, another class must be named NO_REGS 295 and contain no registers. 296 297 The name GENERAL_REGS must be the name of a class (or an alias for 298 another name such as ALL_REGS). This is the class of registers 299 that is allowed by "g" or "r" in a register constraint. 300 Also, registers outside this class are allocated only when 301 instructions express preferences for them. 302 303 The classes must be numbered in nondecreasing order; that is, 304 a larger-numbered class must never be contained completely 305 in a smaller-numbered class. 306 307 For any two classes, it is very desirable that there be another 308 class that represents their union. */ 309 310/* The MCore has only general registers. There are 311 also some special purpose registers: the T bit register, the 312 procedure Link and the Count Registers. */ 313enum reg_class 314{ 315 NO_REGS, 316 ONLYR1_REGS, 317 LRW_REGS, 318 GENERAL_REGS, 319 C_REGS, 320 ALL_REGS, 321 LIM_REG_CLASSES 322}; 323 324#define N_REG_CLASSES (int) LIM_REG_CLASSES 325 326 327/* Give names of register classes as strings for dump file. */ 328#define REG_CLASS_NAMES \ 329{ \ 330 "NO_REGS", \ 331 "ONLYR1_REGS", \ 332 "LRW_REGS", \ 333 "GENERAL_REGS", \ 334 "C_REGS", \ 335 "ALL_REGS", \ 336} 337 338/* Define which registers fit in which classes. 339 This is an initializer for a vector of HARD_REG_SET 340 of length N_REG_CLASSES. */ 341 342/* ??? STACK_POINTER_REGNUM should be excluded from LRW_REGS. */ 343#define REG_CLASS_CONTENTS \ 344{ \ 345 {0x000000}, /* NO_REGS */ \ 346 {0x000002}, /* ONLYR1_REGS */ \ 347 {0x007FFE}, /* LRW_REGS */ \ 348 {0x01FFFF}, /* GENERAL_REGS */ \ 349 {0x020000}, /* C_REGS */ \ 350 {0x0FFFFF} /* ALL_REGS */ \ 351} 352 353/* The same information, inverted: 354 Return the class number of the smallest class containing 355 reg number REGNO. This could be a conditional expression 356 or could index an array. */ 357 358extern const enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER]; 359#define REGNO_REG_CLASS(REGNO) ((REGNO) < FIRST_PSEUDO_REGISTER ? regno_reg_class[REGNO] : NO_REGS) 360 361/* When this hook returns true for MODE, the compiler allows 362 registers explicitly used in the rtl to be used as spill registers 363 but prevents the compiler from extending the lifetime of these 364 registers. */ 365#define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true 366 367/* The class value for index registers, and the one for base regs. */ 368#define INDEX_REG_CLASS NO_REGS 369#define BASE_REG_CLASS GENERAL_REGS 370 371/* Convenience wrappers around insn_const_int_ok_for_constraint. */ 372#define CONST_OK_FOR_I(VALUE) \ 373 insn_const_int_ok_for_constraint (VALUE, CONSTRAINT_I) 374#define CONST_OK_FOR_J(VALUE) \ 375 insn_const_int_ok_for_constraint (VALUE, CONSTRAINT_J) 376#define CONST_OK_FOR_L(VALUE) \ 377 insn_const_int_ok_for_constraint (VALUE, CONSTRAINT_L) 378#define CONST_OK_FOR_K(VALUE) \ 379 insn_const_int_ok_for_constraint (VALUE, CONSTRAINT_K) 380#define CONST_OK_FOR_M(VALUE) \ 381 insn_const_int_ok_for_constraint (VALUE, CONSTRAINT_M) 382#define CONST_OK_FOR_N(VALUE) \ 383 insn_const_int_ok_for_constraint (VALUE, CONSTRAINT_N) 384#define CONST_OK_FOR_O(VALUE) \ 385 insn_const_int_ok_for_constraint (VALUE, CONSTRAINT_O) 386#define CONST_OK_FOR_P(VALUE) \ 387 insn_const_int_ok_for_constraint (VALUE, CONSTRAINT_P) 388 389/* Given an rtx X being reloaded into a reg required to be 390 in class CLASS, return the class of reg to actually use. 391 In general this is just CLASS; but on some machines 392 in some cases it is preferable to use a more restrictive class. */ 393#define PREFERRED_RELOAD_CLASS(X, CLASS) mcore_reload_class (X, CLASS) 394 395/* Return the register class of a scratch register needed to copy IN into 396 or out of a register in CLASS in MODE. If it can be done directly, 397 NO_REGS is returned. */ 398#define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \ 399 mcore_secondary_reload_class (CLASS, MODE, X) 400 401/* Return the maximum number of consecutive registers 402 needed to represent mode MODE in a register of class CLASS. 403 404 On MCore this is the size of MODE in words. */ 405#define CLASS_MAX_NREGS(CLASS, MODE) \ 406 (ROUND_ADVANCE (GET_MODE_SIZE (MODE))) 407 408/* Stack layout; function entry, exit and calling. */ 409 410/* Define the number of register that can hold parameters. 411 These two macros are used only in other macro definitions below. */ 412#define NPARM_REGS 6 413#define FIRST_PARM_REG 2 414#define FIRST_RET_REG 2 415 416/* Define this if pushing a word on the stack 417 makes the stack pointer a smaller address. */ 418#define STACK_GROWS_DOWNWARD 419 420/* Offset within stack frame to start allocating local variables at. 421 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 422 first local allocated. Otherwise, it is the offset to the BEGINNING 423 of the first local allocated. */ 424#define STARTING_FRAME_OFFSET 0 425 426/* If defined, the maximum amount of space required for outgoing arguments 427 will be computed and placed into the variable 428 `crtl->outgoing_args_size'. No space will be pushed 429 onto the stack for each call; instead, the function prologue should 430 increase the stack frame size by this amount. */ 431#define ACCUMULATE_OUTGOING_ARGS 1 432 433/* Offset of first parameter from the argument pointer register value. */ 434#define FIRST_PARM_OFFSET(FNDECL) 0 435 436/* Define how to find the value returned by a function. 437 VALTYPE is the data type of the value (as a tree). 438 If the precise function being called is known, FUNC is its FUNCTION_DECL; 439 otherwise, FUNC is 0. */ 440#define FUNCTION_VALUE(VALTYPE, FUNC) mcore_function_value (VALTYPE, FUNC) 441 442/* Don't default to pcc-struct-return, because gcc is the only compiler, and 443 we want to retain compatibility with older gcc versions. */ 444#define DEFAULT_PCC_STRUCT_RETURN 0 445 446/* Define how to find the value returned by a library function 447 assuming the value has mode MODE. */ 448#define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, FIRST_RET_REG) 449 450/* 1 if N is a possible register number for a function value. 451 On the MCore, only r4 can return results. */ 452#define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == FIRST_RET_REG) 453 454/* 1 if N is a possible register number for function argument passing. */ 455#define FUNCTION_ARG_REGNO_P(REGNO) \ 456 ((REGNO) >= FIRST_PARM_REG && (REGNO) < (NPARM_REGS + FIRST_PARM_REG)) 457 458/* Define a data type for recording info about an argument list 459 during the scan of that argument list. This data type should 460 hold all necessary information about the function itself 461 and about the args processed so far, enough to enable macros 462 such as FUNCTION_ARG to determine where the next arg should go. 463 464 On MCore, this is a single integer, which is a number of words 465 of arguments scanned so far (including the invisible argument, 466 if any, which holds the structure-value-address). 467 Thus NARGREGS or more means all following args should go on the stack. */ 468#define CUMULATIVE_ARGS int 469 470#define ROUND_ADVANCE(SIZE) \ 471 ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 472 473/* Round a register number up to a proper boundary for an arg of mode 474 MODE. 475 476 We round to an even reg for things larger than a word. */ 477#define ROUND_REG(X, MODE) \ 478 ((TARGET_8ALIGN \ 479 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \ 480 ? ((X) + ((X) & 1)) : (X)) 481 482 483/* Initialize a variable CUM of type CUMULATIVE_ARGS 484 for a call to a function whose data type is FNTYPE. 485 For a library call, FNTYPE is 0. 486 487 On MCore, the offset always starts at 0: the first parm reg is always 488 the same reg. */ 489#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ 490 ((CUM) = 0) 491 492/* Call the function profiler with a given profile label. */ 493#define FUNCTION_PROFILER(STREAM,LABELNO) \ 494{ \ 495 fprintf (STREAM, " trap 1\n"); \ 496 fprintf (STREAM, " .align 2\n"); \ 497 fprintf (STREAM, " .long LP%d\n", (LABELNO)); \ 498} 499 500/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 501 the stack pointer does not matter. The value is tested only in 502 functions that have frame pointers. 503 No definition is equivalent to always zero. */ 504#define EXIT_IGNORE_STACK 0 505 506/* Length in units of the trampoline for entering a nested function. */ 507#define TRAMPOLINE_SIZE 12 508 509/* Alignment required for a trampoline in bits. */ 510#define TRAMPOLINE_ALIGNMENT 32 511 512/* Macros to check register numbers against specific register classes. */ 513 514/* These assume that REGNO is a hard or pseudo reg number. 515 They give nonzero only if REGNO is a hard reg of the suitable class 516 or a pseudo reg currently allocated to a suitable hard reg. 517 Since they use reg_renumber, they are safe only once reg_renumber 518 has been allocated, which happens in reginfo.c during register 519 allocation. */ 520#define REGNO_OK_FOR_BASE_P(REGNO) \ 521 ((REGNO) < AP_REG || (unsigned) reg_renumber[(REGNO)] < AP_REG) 522 523#define REGNO_OK_FOR_INDEX_P(REGNO) 0 524 525/* Maximum number of registers that can appear in a valid memory 526 address. */ 527#define MAX_REGS_PER_ADDRESS 1 528 529/* Recognize any constant value that is a valid address. */ 530#define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF) 531 532/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 533 and check its validity for a certain class. 534 We have two alternate definitions for each of them. 535 The usual definition accepts all pseudo regs; the other rejects 536 them unless they have been allocated suitable hard regs. 537 The symbol REG_OK_STRICT causes the latter definition to be used. */ 538#ifndef REG_OK_STRICT 539 540/* Nonzero if X is a hard reg that can be used as a base reg 541 or if it is a pseudo reg. */ 542#define REG_OK_FOR_BASE_P(X) \ 543 (REGNO (X) <= 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 544 545/* Nonzero if X is a hard reg that can be used as an index 546 or if it is a pseudo reg. */ 547#define REG_OK_FOR_INDEX_P(X) 0 548 549#else 550 551/* Nonzero if X is a hard reg that can be used as a base reg. */ 552#define REG_OK_FOR_BASE_P(X) \ 553 REGNO_OK_FOR_BASE_P (REGNO (X)) 554 555/* Nonzero if X is a hard reg that can be used as an index. */ 556#define REG_OK_FOR_INDEX_P(X) 0 557 558#endif 559/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 560 that is a valid memory address for an instruction. 561 The MODE argument is the machine mode for the MEM expression 562 that wants to use this address. 563 564 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */ 565#define BASE_REGISTER_RTX_P(X) \ 566 (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) 567 568#define INDEX_REGISTER_RTX_P(X) \ 569 (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) 570 571 572/* Jump to LABEL if X is a valid address RTX. This must also take 573 REG_OK_STRICT into account when deciding about valid registers, but it uses 574 the above macros so we are in luck. 575 576 Allow REG 577 REG+disp 578 579 A legitimate index for a QI is 0..15, for HI is 0..30, for SI is 0..60, 580 and for DI is 0..56 because we use two SI loads, etc. */ 581#define GO_IF_LEGITIMATE_INDEX(MODE, REGNO, OP, LABEL) \ 582 do \ 583 { \ 584 if (GET_CODE (OP) == CONST_INT) \ 585 { \ 586 if (GET_MODE_SIZE (MODE) >= 4 \ 587 && (((unsigned HOST_WIDE_INT) INTVAL (OP)) % 4) == 0 \ 588 && ((unsigned HOST_WIDE_INT) INTVAL (OP)) \ 589 <= (unsigned HOST_WIDE_INT) 64 - GET_MODE_SIZE (MODE)) \ 590 goto LABEL; \ 591 if (GET_MODE_SIZE (MODE) == 2 \ 592 && (((unsigned HOST_WIDE_INT) INTVAL (OP)) % 2) == 0 \ 593 && ((unsigned HOST_WIDE_INT) INTVAL (OP)) <= 30) \ 594 goto LABEL; \ 595 if (GET_MODE_SIZE (MODE) == 1 \ 596 && ((unsigned HOST_WIDE_INT) INTVAL (OP)) <= 15) \ 597 goto LABEL; \ 598 } \ 599 } \ 600 while (0) 601 602#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \ 603{ \ 604 if (BASE_REGISTER_RTX_P (X)) \ 605 goto LABEL; \ 606 else if (GET_CODE (X) == PLUS || GET_CODE (X) == LO_SUM) \ 607 { \ 608 rtx xop0 = XEXP (X,0); \ 609 rtx xop1 = XEXP (X,1); \ 610 if (BASE_REGISTER_RTX_P (xop0)) \ 611 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \ 612 if (BASE_REGISTER_RTX_P (xop1)) \ 613 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \ 614 } \ 615} 616 617/* Specify the machine mode that this machine uses 618 for the index in the tablejump instruction. */ 619#define CASE_VECTOR_MODE SImode 620 621/* 'char' is signed by default. */ 622#define DEFAULT_SIGNED_CHAR 0 623 624#undef SIZE_TYPE 625#define SIZE_TYPE "unsigned int" 626 627#undef PTRDIFF_TYPE 628#define PTRDIFF_TYPE "int" 629 630#undef WCHAR_TYPE 631#define WCHAR_TYPE "long int" 632 633#undef WCHAR_TYPE_SIZE 634#define WCHAR_TYPE_SIZE BITS_PER_WORD 635 636/* Max number of bytes we can move from memory to memory 637 in one reasonably fast instruction. */ 638#define MOVE_MAX 4 639 640/* Define if operations between registers always perform the operation 641 on the full register even if a narrower mode is specified. */ 642#define WORD_REGISTER_OPERATIONS 643 644/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 645 will either zero-extend or sign-extend. The value of this macro should 646 be the code that says which one of the two operations is implicitly 647 done, UNKNOWN if none. */ 648#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 649 650/* Nonzero if access to memory by bytes is slow and undesirable. */ 651#define SLOW_BYTE_ACCESS TARGET_SLOW_BYTES 652 653/* Shift counts are truncated to 6-bits (0 to 63) instead of the expected 654 5-bits, so we can not define SHIFT_COUNT_TRUNCATED to true for this 655 target. */ 656#define SHIFT_COUNT_TRUNCATED 0 657 658/* All integers have the same format so truncation is easy. */ 659#define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1 660 661/* Define this if addresses of constant functions 662 shouldn't be put through pseudo regs where they can be cse'd. 663 Desirable on machines where ordinary constants are expensive 664 but a CALL with constant address is cheap. */ 665/* Why is this defined??? -- dac */ 666#define NO_FUNCTION_CSE 1 667 668/* The machine modes of pointers and functions. */ 669#define Pmode SImode 670#define FUNCTION_MODE Pmode 671 672/* Compute extra cost of moving data between one register class 673 and another. All register moves are cheap. */ 674#define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) 2 675 676#define WORD_REGISTER_OPERATIONS 677 678/* Assembler output control. */ 679#define ASM_COMMENT_START "\t//" 680 681#define ASM_APP_ON "// inline asm begin\n" 682#define ASM_APP_OFF "// inline asm end\n" 683 684#define FILE_ASM_OP "\t.file\n" 685 686/* Switch to the text or data segment. */ 687#define TEXT_SECTION_ASM_OP "\t.text" 688#define DATA_SECTION_ASM_OP "\t.data" 689 690/* Switch into a generic section. */ 691#undef TARGET_ASM_NAMED_SECTION 692#define TARGET_ASM_NAMED_SECTION mcore_asm_named_section 693 694#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (SImode, LK_REG) 695 696/* This is how to output an insn to push a register on the stack. 697 It need not be very fast code. */ 698#define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ 699 fprintf (FILE, "\tsubi\t %s,%d\n\tstw\t %s,(%s)\n", \ 700 reg_names[STACK_POINTER_REGNUM], \ 701 (STACK_BOUNDARY / BITS_PER_UNIT), \ 702 reg_names[REGNO], \ 703 reg_names[STACK_POINTER_REGNUM]) 704 705/* Length in instructions of the code output by ASM_OUTPUT_REG_PUSH. */ 706#define REG_PUSH_LENGTH 2 707 708/* This is how to output an insn to pop a register from the stack. */ 709#define ASM_OUTPUT_REG_POP(FILE,REGNO) \ 710 fprintf (FILE, "\tldw\t %s,(%s)\n\taddi\t %s,%d\n", \ 711 reg_names[REGNO], \ 712 reg_names[STACK_POINTER_REGNUM], \ 713 reg_names[STACK_POINTER_REGNUM], \ 714 (STACK_BOUNDARY / BITS_PER_UNIT)) 715 716 717/* Output a reference to a label. */ 718#undef ASM_OUTPUT_LABELREF 719#define ASM_OUTPUT_LABELREF(STREAM, NAME) \ 720 fprintf (STREAM, "%s%s", USER_LABEL_PREFIX, \ 721 (* targetm.strip_name_encoding) (NAME)) 722 723/* This is how to output an assembler line 724 that says to advance the location counter 725 to a multiple of 2**LOG bytes. */ 726#define ASM_OUTPUT_ALIGN(FILE,LOG) \ 727 if ((LOG) != 0) \ 728 fprintf (FILE, "\t.align\t%d\n", LOG) 729 730#ifndef ASM_DECLARE_RESULT 731#define ASM_DECLARE_RESULT(FILE, RESULT) 732#endif 733 734#define MULTIPLE_SYMBOL_SPACES 1 735 736#define SUPPORTS_ONE_ONLY 1 737 738/* A pair of macros to output things for the callgraph data. 739 VALUE means (to the tools that reads this info later): 740 0 a call from src to dst 741 1 the call is special (e.g. dst is "unknown" or "alloca") 742 2 the call is special (e.g., the src is a table instead of routine) 743 744 Frame sizes are augmented with timestamps to help later tools 745 differentiate between static entities with same names in different 746 files. */ 747extern long mcore_current_compilation_timestamp; 748#define ASM_OUTPUT_CG_NODE(FILE,SRCNAME,VALUE) \ 749 do \ 750 { \ 751 if (mcore_current_compilation_timestamp == 0) \ 752 mcore_current_compilation_timestamp = time (0); \ 753 fprintf ((FILE),"\t.equ\t__$frame$size$_%s_$_%08lx,%d\n", \ 754 (SRCNAME), mcore_current_compilation_timestamp, (VALUE)); \ 755 } \ 756 while (0) 757 758#define ASM_OUTPUT_CG_EDGE(FILE,SRCNAME,DSTNAME,VALUE) \ 759 do \ 760 { \ 761 fprintf ((FILE),"\t.equ\t__$function$call$_%s_$_%s,%d\n", \ 762 (SRCNAME), (DSTNAME), (VALUE)); \ 763 } \ 764 while (0) 765 766/* Globalizing directive for a label. */ 767#define GLOBAL_ASM_OP "\t.export\t" 768 769/* The prefix to add to user-visible assembler symbols. */ 770#undef USER_LABEL_PREFIX 771#define USER_LABEL_PREFIX "" 772 773/* Make an internal label into a string. */ 774#undef ASM_GENERATE_INTERNAL_LABEL 775#define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \ 776 sprintf (STRING, "*.%s%ld", PREFIX, (long) NUM) 777 778/* Jump tables must be 32 bit aligned. */ 779#undef ASM_OUTPUT_CASE_LABEL 780#define ASM_OUTPUT_CASE_LABEL(STREAM,PREFIX,NUM,TABLE) \ 781 fprintf (STREAM, "\t.align 2\n.%s%d:\n", PREFIX, NUM); 782 783/* Output a relative address. Not needed since jump tables are absolute 784 but we must define it anyway. */ 785#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \ 786 fputs ("- - - ASM_OUTPUT_ADDR_DIFF_ELT called!\n", STREAM) 787 788/* Output an element of a dispatch table. */ 789#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \ 790 fprintf (STREAM, "\t.long\t.L%d\n", VALUE) 791 792/* Output various types of constants. */ 793 794/* This is how to output an assembler line 795 that says to advance the location counter by SIZE bytes. */ 796#undef ASM_OUTPUT_SKIP 797#define ASM_OUTPUT_SKIP(FILE,SIZE) \ 798 fprintf (FILE, "\t.fill %d, 1\n", (int)(SIZE)) 799 800/* This says how to output an assembler line 801 to define a global common symbol, with alignment information. */ 802/* XXX - for now we ignore the alignment. */ 803#undef ASM_OUTPUT_ALIGNED_COMMON 804#define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \ 805 do \ 806 { \ 807 if (mcore_dllexport_name_p (NAME)) \ 808 MCORE_EXPORT_NAME (FILE, NAME) \ 809 if (! mcore_dllimport_name_p (NAME)) \ 810 { \ 811 fputs ("\t.comm\t", FILE); \ 812 assemble_name (FILE, NAME); \ 813 fprintf (FILE, ",%lu\n", (unsigned long)(SIZE)); \ 814 } \ 815 } \ 816 while (0) 817 818/* This says how to output an assembler line 819 to define a local common symbol.... */ 820#undef ASM_OUTPUT_LOCAL 821#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ 822 (fputs ("\t.lcomm\t", FILE), \ 823 assemble_name (FILE, NAME), \ 824 fprintf (FILE, ",%d\n", (int)SIZE)) 825 826/* ... and how to define a local common symbol whose alignment 827 we wish to specify. ALIGN comes in as bits, we have to turn 828 it into bytes. */ 829#undef ASM_OUTPUT_ALIGNED_LOCAL 830#define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \ 831 do \ 832 { \ 833 fputs ("\t.bss\t", (FILE)); \ 834 assemble_name ((FILE), (NAME)); \ 835 fprintf ((FILE), ",%d,%d\n", (int)(SIZE), (ALIGN) / BITS_PER_UNIT);\ 836 } \ 837 while (0) 838 839#endif /* ! GCC_MCORE_H */ 840