i386.opt revision 1.1.1.2
1; Options for the IA-32 and AMD64 ports of the compiler. 2 3; Copyright (C) 2005-2013 Free Software Foundation, Inc. 4; 5; This file is part of GCC. 6; 7; GCC is free software; you can redistribute it and/or modify it under 8; the terms of the GNU General Public License as published by the Free 9; Software Foundation; either version 3, or (at your option) any later 10; version. 11; 12; GCC is distributed in the hope that it will be useful, but WITHOUT ANY 13; WARRANTY; without even the implied warranty of MERCHANTABILITY or 14; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15; for more details. 16; 17; You should have received a copy of the GNU General Public License 18; along with GCC; see the file COPYING3. If not see 19; <http://www.gnu.org/licenses/>. 20 21HeaderInclude 22config/i386/i386-opts.h 23 24; Bit flags that specify the ISA we are compiling for. 25Variable 26HOST_WIDE_INT ix86_isa_flags = TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_ISA_DEFAULT 27 28; A mask of ix86_isa_flags that includes bit X if X was set or cleared 29; on the command line. 30Variable 31HOST_WIDE_INT ix86_isa_flags_explicit 32 33TargetVariable 34int recip_mask = RECIP_MASK_DEFAULT 35 36Variable 37int recip_mask_explicit 38 39TargetSave 40int x_recip_mask_explicit 41 42;; Definitions to add to the cl_target_option structure 43;; -march= processor 44TargetSave 45unsigned char arch 46 47;; -mtune= processor 48TargetSave 49unsigned char tune 50 51;; CPU schedule model 52TargetSave 53unsigned char schedule 54 55;; branch cost 56TargetSave 57unsigned char branch_cost 58 59;; which flags were passed by the user 60TargetSave 61HOST_WIDE_INT x_ix86_isa_flags_explicit 62 63;; which flags were passed by the user 64TargetSave 65int ix86_target_flags_explicit 66 67;; whether -mtune was not specified 68TargetSave 69unsigned char tune_defaulted 70 71;; whether -march was specified 72TargetSave 73unsigned char arch_specified 74 75;; x86 options 76m128bit-long-double 77Target RejectNegative Report Mask(128BIT_LONG_DOUBLE) Save 78sizeof(long double) is 16 79 80m80387 81Target Report Mask(80387) Save 82Use hardware fp 83 84m96bit-long-double 85Target RejectNegative Report InverseMask(128BIT_LONG_DOUBLE) Save 86sizeof(long double) is 12 87 88mlong-double-80 89Target Report RejectNegative InverseMask(LONG_DOUBLE_64) Save 90Use 80-bit long double 91 92mlong-double-64 93Target Report RejectNegative Mask(LONG_DOUBLE_64) Save 94Use 64-bit long double 95 96maccumulate-outgoing-args 97Target Report Mask(ACCUMULATE_OUTGOING_ARGS) Save 98Reserve space for outgoing arguments in the function prologue 99 100malign-double 101Target Report Mask(ALIGN_DOUBLE) Save 102Align some doubles on dword boundary 103 104malign-functions= 105Target RejectNegative Joined UInteger 106Function starts are aligned to this power of 2 107 108malign-jumps= 109Target RejectNegative Joined UInteger 110Jump targets are aligned to this power of 2 111 112malign-loops= 113Target RejectNegative Joined UInteger 114Loop code aligned to this power of 2 115 116malign-stringops 117Target RejectNegative Report InverseMask(NO_ALIGN_STRINGOPS, ALIGN_STRINGOPS) Save 118Align destination of the string operations 119 120march= 121Target RejectNegative Joined Var(ix86_arch_string) 122Generate code for given CPU 123 124masm= 125Target RejectNegative Joined Enum(asm_dialect) Var(ix86_asm_dialect) Init(ASM_ATT) 126Use given assembler dialect 127 128Enum 129Name(asm_dialect) Type(enum asm_dialect) 130Known assembler dialects (for use with the -masm-dialect= option): 131 132EnumValue 133Enum(asm_dialect) String(intel) Value(ASM_INTEL) 134 135EnumValue 136Enum(asm_dialect) String(att) Value(ASM_ATT) 137 138mbranch-cost= 139Target RejectNegative Joined UInteger Var(ix86_branch_cost) 140Branches are this expensive (1-5, arbitrary units) 141 142mlarge-data-threshold= 143Target RejectNegative Joined UInteger Var(ix86_section_threshold) Init(DEFAULT_LARGE_SECTION_THRESHOLD) 144Data greater than given threshold will go into .ldata section in x86-64 medium model 145 146mcmodel= 147Target RejectNegative Joined Enum(cmodel) Var(ix86_cmodel) Init(CM_32) 148Use given x86-64 code model 149 150Enum 151Name(cmodel) Type(enum cmodel) 152Known code models (for use with the -mcmodel= option): 153 154EnumValue 155Enum(cmodel) String(small) Value(CM_SMALL) 156 157EnumValue 158Enum(cmodel) String(medium) Value(CM_MEDIUM) 159 160EnumValue 161Enum(cmodel) String(large) Value(CM_LARGE) 162 163EnumValue 164Enum(cmodel) String(32) Value(CM_32) 165 166EnumValue 167Enum(cmodel) String(kernel) Value(CM_KERNEL) 168 169maddress-mode= 170Target RejectNegative Joined Enum(pmode) Var(ix86_pmode) Init(PMODE_SI) 171Use given address mode 172 173Enum 174Name(pmode) Type(enum pmode) 175Known address mode (for use with the -maddress-mode= option): 176 177EnumValue 178Enum(pmode) String(short) Value(PMODE_SI) 179 180EnumValue 181Enum(pmode) String(long) Value(PMODE_DI) 182 183mcpu= 184Target RejectNegative Joined Undocumented Alias(mtune=) Warn(%<-mcpu=%> is deprecated; use %<-mtune=%> or %<-march=%> instead) 185 186mfancy-math-387 187Target RejectNegative Report InverseMask(NO_FANCY_MATH_387, USE_FANCY_MATH_387) Save 188Generate sin, cos, sqrt for FPU 189 190mforce-drap 191Target Report Var(ix86_force_drap) 192Always use Dynamic Realigned Argument Pointer (DRAP) to realign stack 193 194mfp-ret-in-387 195Target Report Mask(FLOAT_RETURNS) Save 196Return values of functions in FPU registers 197 198mfpmath= 199Target RejectNegative Joined Var(ix86_fpmath) Enum(fpmath_unit) Init(FPMATH_387) Save 200Generate floating point mathematics using given instruction set 201 202Enum 203Name(fpmath_unit) Type(enum fpmath_unit) 204Valid arguments to -mfpmath=: 205 206EnumValue 207Enum(fpmath_unit) String(387) Value(FPMATH_387) 208 209EnumValue 210Enum(fpmath_unit) String(sse) Value(FPMATH_SSE) 211 212EnumValue 213Enum(fpmath_unit) String(387,sse) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)}) 214 215EnumValue 216Enum(fpmath_unit) String(387+sse) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)}) 217 218EnumValue 219Enum(fpmath_unit) String(sse,387) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)}) 220 221EnumValue 222Enum(fpmath_unit) String(sse+387) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)}) 223 224EnumValue 225Enum(fpmath_unit) String(both) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)}) 226 227mhard-float 228Target RejectNegative Mask(80387) Save 229Use hardware fp 230 231mieee-fp 232Target Report Mask(IEEE_FP) Save 233Use IEEE math for fp comparisons 234 235minline-all-stringops 236Target Report Mask(INLINE_ALL_STRINGOPS) Save 237Inline all known string operations 238 239minline-stringops-dynamically 240Target Report Mask(INLINE_STRINGOPS_DYNAMICALLY) Save 241Inline memset/memcpy string operations, but perform inline version only for small blocks 242 243mintel-syntax 244Target Undocumented Alias(masm=, intel, att) Warn(%<-mintel-syntax%> and %<-mno-intel-syntax%> are deprecated; use %<-masm=intel%> and %<-masm=att%> instead) 245;; Deprecated 246 247mms-bitfields 248Target Report Mask(MS_BITFIELD_LAYOUT) Save 249Use native (MS) bitfield layout 250 251mno-align-stringops 252Target RejectNegative Report Mask(NO_ALIGN_STRINGOPS) Undocumented Save 253 254mno-fancy-math-387 255Target RejectNegative Report Mask(NO_FANCY_MATH_387) Undocumented Save 256 257mno-push-args 258Target RejectNegative Report Mask(NO_PUSH_ARGS) Undocumented Save 259 260mno-red-zone 261Target RejectNegative Report Mask(NO_RED_ZONE) Undocumented Save 262 263momit-leaf-frame-pointer 264Target Report Mask(OMIT_LEAF_FRAME_POINTER) Save 265Omit the frame pointer in leaf functions 266 267mpc32 268Target RejectNegative Report 269Set 80387 floating-point precision to 32-bit 270 271mpc64 272Target RejectNegative Report 273Set 80387 floating-point precision to 64-bit 274 275mpc80 276Target RejectNegative Report 277Set 80387 floating-point precision to 80-bit 278 279mpreferred-stack-boundary= 280Target RejectNegative Joined UInteger Var(ix86_preferred_stack_boundary_arg) 281Attempt to keep stack aligned to this power of 2 282 283mincoming-stack-boundary= 284Target RejectNegative Joined UInteger Var(ix86_incoming_stack_boundary_arg) 285Assume incoming stack aligned to this power of 2 286 287mpush-args 288Target Report InverseMask(NO_PUSH_ARGS, PUSH_ARGS) Save 289Use push instructions to save outgoing arguments 290 291mred-zone 292Target RejectNegative Report InverseMask(NO_RED_ZONE, RED_ZONE) Save 293Use red-zone in the x86-64 code 294 295mregparm= 296Target RejectNegative Joined UInteger Var(ix86_regparm) 297Number of registers used to pass integer arguments 298 299mrtd 300Target Report Mask(RTD) Save 301Alternate calling convention 302 303msoft-float 304Target InverseMask(80387) Save 305Do not use hardware fp 306 307msseregparm 308Target RejectNegative Mask(SSEREGPARM) Save 309Use SSE register passing conventions for SF and DF mode 310 311mstackrealign 312Target Report Var(ix86_force_align_arg_pointer) Init(-1) 313Realign stack in prologue 314 315mstack-arg-probe 316Target Report Mask(STACK_PROBE) Save 317Enable stack probing 318 319mstringop-strategy= 320Target RejectNegative Joined Enum(stringop_alg) Var(ix86_stringop_alg) Init(no_stringop) 321Chose strategy to generate stringop using 322 323Enum 324Name(stringop_alg) Type(enum stringop_alg) 325Valid arguments to -mstringop-strategy=: 326 327EnumValue 328Enum(stringop_alg) String(rep_byte) Value(rep_prefix_1_byte) 329 330EnumValue 331Enum(stringop_alg) String(libcall) Value(libcall) 332 333EnumValue 334Enum(stringop_alg) String(rep_4byte) Value(rep_prefix_4_byte) 335 336EnumValue 337Enum(stringop_alg) String(rep_8byte) Value(rep_prefix_8_byte) 338 339EnumValue 340Enum(stringop_alg) String(byte_loop) Value(loop_1_byte) 341 342EnumValue 343Enum(stringop_alg) String(loop) Value(loop) 344 345EnumValue 346Enum(stringop_alg) String(unrolled_loop) Value(unrolled_loop) 347 348mtls-dialect= 349Target RejectNegative Joined Var(ix86_tls_dialect) Enum(tls_dialect) Init(TLS_DIALECT_GNU) 350Use given thread-local storage dialect 351 352Enum 353Name(tls_dialect) Type(enum tls_dialect) 354Known TLS dialects (for use with the -mtls-dialect= option): 355 356EnumValue 357Enum(tls_dialect) String(gnu) Value(TLS_DIALECT_GNU) 358 359EnumValue 360Enum(tls_dialect) String(gnu2) Value(TLS_DIALECT_GNU2) 361 362mtls-direct-seg-refs 363Target Report Mask(TLS_DIRECT_SEG_REFS) 364Use direct references against %gs when accessing tls data 365 366mtune= 367Target RejectNegative Joined Var(ix86_tune_string) 368Schedule code for given CPU 369 370mabi= 371Target RejectNegative Joined Var(ix86_abi) Enum(calling_abi) Init(SYSV_ABI) 372Generate code that conforms to the given ABI 373 374Enum 375Name(calling_abi) Type(enum calling_abi) 376Known ABIs (for use with the -mabi= option): 377 378EnumValue 379Enum(calling_abi) String(sysv) Value(SYSV_ABI) 380 381EnumValue 382Enum(calling_abi) String(ms) Value(MS_ABI) 383 384mveclibabi= 385Target RejectNegative Joined Var(ix86_veclibabi_type) Enum(ix86_veclibabi) Init(ix86_veclibabi_type_none) 386Vector library ABI to use 387 388Enum 389Name(ix86_veclibabi) Type(enum ix86_veclibabi) 390Known vectorization library ABIs (for use with the -mveclibabi= option): 391 392EnumValue 393Enum(ix86_veclibabi) String(svml) Value(ix86_veclibabi_type_svml) 394 395EnumValue 396Enum(ix86_veclibabi) String(acml) Value(ix86_veclibabi_type_acml) 397 398mvect8-ret-in-mem 399Target Report Mask(VECT8_RETURNS) Save 400Return 8-byte vectors in memory 401 402mrecip 403Target Report Mask(RECIP) Save 404Generate reciprocals instead of divss and sqrtss. 405 406mrecip= 407Target Report RejectNegative Joined Var(ix86_recip_name) 408Control generation of reciprocal estimates. 409 410mcld 411Target Report Mask(CLD) Save 412Generate cld instruction in the function prologue. 413 414mvzeroupper 415Target Report Mask(VZEROUPPER) Save 416Generate vzeroupper instruction before a transfer of control flow out of 417the function. 418 419mdispatch-scheduler 420Target RejectNegative Var(flag_dispatch_scheduler) 421Do dispatch scheduling if processor is bdver1 or bdver2 or bdver3 and Haifa scheduling 422is selected. 423 424mprefer-avx128 425Target Report Mask(PREFER_AVX128) SAVE 426Use 128-bit AVX instructions instead of 256-bit AVX instructions in the auto-vectorizer. 427 428;; ISA support 429 430m32 431Target RejectNegative Negative(m64) Report InverseMask(ISA_64BIT) Var(ix86_isa_flags) Save 432Generate 32bit i386 code 433 434m64 435Target RejectNegative Negative(mx32) Report Mask(ABI_64) Var(ix86_isa_flags) Save 436Generate 64bit x86-64 code 437 438mx32 439Target RejectNegative Negative(m32) Report Mask(ABI_X32) Var(ix86_isa_flags) Save 440Generate 32bit x86-64 code 441 442mmmx 443Target Report Mask(ISA_MMX) Var(ix86_isa_flags) Save 444Support MMX built-in functions 445 446m3dnow 447Target Report Mask(ISA_3DNOW) Var(ix86_isa_flags) Save 448Support 3DNow! built-in functions 449 450m3dnowa 451Target Undocumented Mask(ISA_3DNOW_A) Var(ix86_isa_flags) Save 452Support Athlon 3Dnow! built-in functions 453 454msse 455Target Report Mask(ISA_SSE) Var(ix86_isa_flags) Save 456Support MMX and SSE built-in functions and code generation 457 458msse2 459Target Report Mask(ISA_SSE2) Var(ix86_isa_flags) Save 460Support MMX, SSE and SSE2 built-in functions and code generation 461 462msse3 463Target Report Mask(ISA_SSE3) Var(ix86_isa_flags) Save 464Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation 465 466mssse3 467Target Report Mask(ISA_SSSE3) Var(ix86_isa_flags) Save 468Support MMX, SSE, SSE2, SSE3 and SSSE3 built-in functions and code generation 469 470msse4.1 471Target Report Mask(ISA_SSE4_1) Var(ix86_isa_flags) Save 472Support MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 built-in functions and code generation 473 474msse4.2 475Target Report Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save 476Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation 477 478msse4 479Target RejectNegative Report Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save 480Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation 481 482mno-sse4 483Target RejectNegative Report InverseMask(ISA_SSE4_1) Var(ix86_isa_flags) Save 484Do not support SSE4.1 and SSE4.2 built-in functions and code generation 485 486msse5 487Target Undocumented Alias(mavx) Warn(%<-msse5%> was removed) 488;; Deprecated 489 490mavx 491Target Report Mask(ISA_AVX) Var(ix86_isa_flags) Save 492Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 and AVX built-in functions and code generation 493 494mavx2 495Target Report Mask(ISA_AVX2) Var(ix86_isa_flags) Save 496Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and AVX2 built-in functions and code generation 497 498mfma 499Target Report Mask(ISA_FMA) Var(ix86_isa_flags) Save 500Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and FMA built-in functions and code generation 501 502msse4a 503Target Report Mask(ISA_SSE4A) Var(ix86_isa_flags) Save 504Support MMX, SSE, SSE2, SSE3 and SSE4A built-in functions and code generation 505 506mfma4 507Target Report Mask(ISA_FMA4) Var(ix86_isa_flags) Save 508Support FMA4 built-in functions and code generation 509 510mxop 511Target Report Mask(ISA_XOP) Var(ix86_isa_flags) Save 512Support XOP built-in functions and code generation 513 514mlwp 515Target Report Mask(ISA_LWP) Var(ix86_isa_flags) Save 516Support LWP built-in functions and code generation 517 518mabm 519Target Report Mask(ISA_ABM) Var(ix86_isa_flags) Save 520Support code generation of Advanced Bit Manipulation (ABM) instructions. 521 522mpopcnt 523Target Report Mask(ISA_POPCNT) Var(ix86_isa_flags) Save 524Support code generation of popcnt instruction. 525 526mbmi 527Target Report Mask(ISA_BMI) Var(ix86_isa_flags) Save 528Support BMI built-in functions and code generation 529 530mbmi2 531Target Report Mask(ISA_BMI2) Var(ix86_isa_flags) Save 532Support BMI2 built-in functions and code generation 533 534mlzcnt 535Target Report Mask(ISA_LZCNT) Var(ix86_isa_flags) Save 536Support LZCNT built-in function and code generation 537 538mhle 539Target Report Mask(ISA_HLE) Var(ix86_isa_flags) Save 540Support Hardware Lock Elision prefixes 541 542mrdseed 543Target Report Mask(ISA_RDSEED) Var(ix86_isa_flags) Save 544Support RDSEED instruction 545 546mprfchw 547Target Report Mask(ISA_PRFCHW) Var(ix86_isa_flags) Save 548Support PREFETCHW instruction 549 550madx 551Target Report Mask(ISA_ADX) Var(ix86_isa_flags) Save 552Support flag-preserving add-carry instructions 553 554mfxsr 555Target Report Mask(ISA_FXSR) Var(ix86_isa_flags) Save 556Support FXSAVE and FXRSTOR instructions 557 558mxsave 559Target Report Mask(ISA_XSAVE) Var(ix86_isa_flags) Save 560Support XSAVE and XRSTOR instructions 561 562mxsaveopt 563Target Report Mask(ISA_XSAVEOPT) Var(ix86_isa_flags) Save 564Support XSAVEOPT instruction 565 566mtbm 567Target Report Mask(ISA_TBM) Var(ix86_isa_flags) Save 568Support TBM built-in functions and code generation 569 570mcx16 571Target Report Mask(ISA_CX16) Var(ix86_isa_flags) Save 572Support code generation of cmpxchg16b instruction. 573 574msahf 575Target Report Mask(ISA_SAHF) Var(ix86_isa_flags) Save 576Support code generation of sahf instruction in 64bit x86-64 code. 577 578mmovbe 579Target Report Mask(ISA_MOVBE) Var(ix86_isa_flags) Save 580Support code generation of movbe instruction. 581 582mcrc32 583Target Report Mask(ISA_CRC32) Var(ix86_isa_flags) Save 584Support code generation of crc32 instruction. 585 586maes 587Target Report Mask(ISA_AES) Var(ix86_isa_flags) Save 588Support AES built-in functions and code generation 589 590mpclmul 591Target Report Mask(ISA_PCLMUL) Var(ix86_isa_flags) Save 592Support PCLMUL built-in functions and code generation 593 594msse2avx 595Target Report Var(ix86_sse2avx) 596Encode SSE instructions with VEX prefix 597 598mfsgsbase 599Target Report Mask(ISA_FSGSBASE) Var(ix86_isa_flags) Save 600Support FSGSBASE built-in functions and code generation 601 602mrdrnd 603Target Report Mask(ISA_RDRND) Var(ix86_isa_flags) Save 604Support RDRND built-in functions and code generation 605 606mf16c 607Target Report Mask(ISA_F16C) Var(ix86_isa_flags) Save 608Support F16C built-in functions and code generation 609 610mfentry 611Target Report Var(flag_fentry) Init(-1) 612Emit profiling counter call at function entry before prologue. 613 614m8bit-idiv 615Target Report Mask(USE_8BIT_IDIV) Save 616Expand 32bit/64bit integer divide into 8bit unsigned integer divide with run-time check 617 618mavx256-split-unaligned-load 619Target Report Mask(AVX256_SPLIT_UNALIGNED_LOAD) Save 620Split 32-byte AVX unaligned load 621 622mavx256-split-unaligned-store 623Target Report Mask(AVX256_SPLIT_UNALIGNED_STORE) Save 624Split 32-byte AVX unaligned store 625 626mrtm 627Target Report Mask(ISA_RTM) Var(ix86_isa_flags) Save 628Support RTM built-in functions and code generation 629