i386.opt revision 1.1.1.1.8.2 
1; Options for the IA-32 and AMD64 ports of the compiler.
2
3; Copyright (C) 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
4;
5; This file is part of GCC.
6;
7; GCC is free software; you can redistribute it and/or modify it under
8; the terms of the GNU General Public License as published by the Free
9; Software Foundation; either version 3, or (at your option) any later
10; version.
11;
12; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13; WARRANTY; without even the implied warranty of MERCHANTABILITY or
14; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
15; for more details.
16;
17; You should have received a copy of the GNU General Public License
18; along with GCC; see the file COPYING3.  If not see
19; <http://www.gnu.org/licenses/>.
20
21;; Definitions to add to the cl_target_option structure
22;; -march= processor
23TargetSave
24unsigned char arch
25
26;; -mtune= processor
27TargetSave
28unsigned char tune
29
30;; -mfpath=
31TargetSave
32unsigned char fpmath
33
34;; CPU schedule model
35TargetSave
36unsigned char schedule
37
38;; branch cost
39TargetSave
40unsigned char branch_cost
41
42;; which flags were passed by the user
43TargetSave
44int ix86_isa_flags_explicit
45
46;; which flags were passed by the user
47TargetSave
48int target_flags_explicit
49
50;; whether -mtune was not specified
51TargetSave
52unsigned char tune_defaulted
53
54;; whether -march was specified
55TargetSave
56unsigned char arch_specified
57
58;; x86 options
59m128bit-long-double
60Target RejectNegative Report Mask(128BIT_LONG_DOUBLE) Save
61sizeof(long double) is 16
62
63m80387
64Target Report Mask(80387) Save
65Use hardware fp
66
67m96bit-long-double
68Target RejectNegative Report InverseMask(128BIT_LONG_DOUBLE) Save
69sizeof(long double) is 12
70
71maccumulate-outgoing-args
72Target Report Mask(ACCUMULATE_OUTGOING_ARGS) Save
73Reserve space for outgoing arguments in the function prologue
74
75malign-double
76Target Report Mask(ALIGN_DOUBLE) Save
77Align some doubles on dword boundary
78
79malign-functions=
80Target RejectNegative Joined Var(ix86_align_funcs_string)
81Function starts are aligned to this power of 2
82
83malign-jumps=
84Target RejectNegative Joined Var(ix86_align_jumps_string)
85Jump targets are aligned to this power of 2
86
87malign-loops=
88Target RejectNegative Joined Var(ix86_align_loops_string)
89Loop code aligned to this power of 2
90
91malign-stringops
92Target RejectNegative Report InverseMask(NO_ALIGN_STRINGOPS, ALIGN_STRINGOPS) Save
93Align destination of the string operations
94
95march=
96Target RejectNegative Joined Var(ix86_arch_string)
97Generate code for given CPU
98
99masm=
100Target RejectNegative Joined Var(ix86_asm_string)
101Use given assembler dialect
102
103mbranch-cost=
104Target RejectNegative Joined Var(ix86_branch_cost_string)
105Branches are this expensive (1-5, arbitrary units)
106
107mlarge-data-threshold=
108Target RejectNegative Joined Var(ix86_section_threshold_string)
109Data greater than given threshold will go into .ldata section in x86-64 medium model
110
111mcmodel=
112Target RejectNegative Joined Var(ix86_cmodel_string)
113Use given x86-64 code model
114
115mfancy-math-387
116Target RejectNegative Report InverseMask(NO_FANCY_MATH_387, USE_FANCY_MATH_387) Save
117Generate sin, cos, sqrt for FPU
118
119mforce-drap
120Target Report Var(ix86_force_drap)
121Always use Dynamic Realigned Argument Pointer (DRAP) to realign stack
122
123mfp-ret-in-387
124Target Report Mask(FLOAT_RETURNS) Save
125Return values of functions in FPU registers
126
127mfpmath=
128Target RejectNegative Joined Var(ix86_fpmath_string)
129Generate floating point mathematics using given instruction set
130
131mhard-float
132Target RejectNegative Mask(80387) MaskExists Save
133Use hardware fp
134
135mieee-fp
136Target Report Mask(IEEE_FP) Save
137Use IEEE math for fp comparisons
138
139minline-all-stringops
140Target Report Mask(INLINE_ALL_STRINGOPS) Save
141Inline all known string operations
142
143minline-stringops-dynamically
144Target Report Mask(INLINE_STRINGOPS_DYNAMICALLY) Save
145Inline memset/memcpy string operations, but perform inline version only for small blocks
146
147mintel-syntax
148Target Undocumented
149;; Deprecated
150
151mms-bitfields
152Target Report Mask(MS_BITFIELD_LAYOUT) Save
153Use native (MS) bitfield layout
154
155mno-align-stringops
156Target RejectNegative Report Mask(NO_ALIGN_STRINGOPS) Undocumented Save
157
158mno-fancy-math-387
159Target RejectNegative Report Mask(NO_FANCY_MATH_387) Undocumented Save
160
161mno-push-args
162Target RejectNegative Report Mask(NO_PUSH_ARGS) Undocumented Save
163
164mno-red-zone
165Target RejectNegative Report Mask(NO_RED_ZONE) Undocumented Save
166
167momit-leaf-frame-pointer
168Target Report Mask(OMIT_LEAF_FRAME_POINTER) Save
169Omit the frame pointer in leaf functions
170
171mpc
172Target RejectNegative Report Joined Var(ix87_precision_string)
173Set 80387 floating-point precision (-mpc32, -mpc64, -mpc80)
174
175mpreferred-stack-boundary=
176Target RejectNegative Joined Var(ix86_preferred_stack_boundary_string)
177Attempt to keep stack aligned to this power of 2
178
179mincoming-stack-boundary=
180Target RejectNegative Joined Var(ix86_incoming_stack_boundary_string)
181Assume incoming stack aligned to this power of 2
182
183mpush-args
184Target Report InverseMask(NO_PUSH_ARGS, PUSH_ARGS) Save
185Use push instructions to save outgoing arguments
186
187mred-zone
188Target RejectNegative Report InverseMask(NO_RED_ZONE, RED_ZONE) Save
189Use red-zone in the x86-64 code
190
191mregparm=
192Target RejectNegative Joined Var(ix86_regparm_string)
193Number of registers used to pass integer arguments
194
195mrtd
196Target Report Mask(RTD) Save
197Alternate calling convention
198
199msoft-float
200Target InverseMask(80387) Save
201Do not use hardware fp
202
203msseregparm
204Target RejectNegative Mask(SSEREGPARM) Save
205Use SSE register passing conventions for SF and DF mode
206
207mstackrealign
208Target Report Var(ix86_force_align_arg_pointer) Init(-1)
209Realign stack in prologue
210
211mstack-arg-probe
212Target Report Mask(STACK_PROBE) Save
213Enable stack probing
214
215mstringop-strategy=
216Target RejectNegative Joined Var(ix86_stringop_string)
217Chose strategy to generate stringop using
218
219mtls-dialect=
220Target RejectNegative Joined Var(ix86_tls_dialect_string)
221Use given thread-local storage dialect
222
223mtls-direct-seg-refs
224Target Report Mask(TLS_DIRECT_SEG_REFS)
225Use direct references against %gs when accessing tls data
226
227mtune=
228Target RejectNegative Joined Var(ix86_tune_string)
229Schedule code for given CPU
230
231mabi=
232Target RejectNegative Joined Var(ix86_abi_string)
233Generate code that conforms to the given ABI
234
235mveclibabi=
236Target RejectNegative Joined Var(ix86_veclibabi_string)
237Vector library ABI to use
238
239mrecip
240Target Report Mask(RECIP) Save
241Generate reciprocals instead of divss and sqrtss.
242
243mcld
244Target Report Mask(CLD) Save
245Generate cld instruction in the function prologue.
246
247mfused-madd
248Target Report Mask(FUSED_MADD) Save
249Enable automatic generation of fused floating point multiply-add instructions
250if the ISA supports such instructions.  The -mfused-madd option is on by
251default.
252
253;; ISA support
254
255m32
256Target RejectNegative Negative(m64) Report InverseMask(ISA_64BIT) Var(ix86_isa_flags) VarExists Save
257Generate 32bit i386 code
258
259m64
260Target RejectNegative Negative(m32) Report Mask(ISA_64BIT) Var(ix86_isa_flags) VarExists Save
261Generate 64bit x86-64 code
262
263mmmx
264Target Report Mask(ISA_MMX) Var(ix86_isa_flags) VarExists Save
265Support MMX built-in functions
266
267m3dnow
268Target Report Mask(ISA_3DNOW) Var(ix86_isa_flags) VarExists Save
269Support 3DNow! built-in functions
270
271m3dnowa
272Target Undocumented Mask(ISA_3DNOW_A) Var(ix86_isa_flags) VarExists Save
273Support Athlon 3Dnow! built-in functions
274
275msse
276Target Report Mask(ISA_SSE) Var(ix86_isa_flags) VarExists Save
277Support MMX and SSE built-in functions and code generation
278
279msse2
280Target Report Mask(ISA_SSE2) Var(ix86_isa_flags) VarExists Save
281Support MMX, SSE and SSE2 built-in functions and code generation
282
283msse3
284Target Report Mask(ISA_SSE3) Var(ix86_isa_flags) VarExists Save
285Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation
286
287mssse3
288Target Report Mask(ISA_SSSE3) Var(ix86_isa_flags) VarExists Save
289Support MMX, SSE, SSE2, SSE3 and SSSE3 built-in functions and code generation
290
291msse4.1
292Target Report Mask(ISA_SSE4_1) Var(ix86_isa_flags) VarExists Save
293Support MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 built-in functions and code generation
294
295msse4.2
296Target Report Mask(ISA_SSE4_2) Var(ix86_isa_flags) VarExists Save
297Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation
298
299msse4
300Target RejectNegative Report Mask(ISA_SSE4_2) MaskExists Var(ix86_isa_flags) VarExists Save
301Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation
302
303mno-sse4
304Target RejectNegative Report InverseMask(ISA_SSE4_1) MaskExists Var(ix86_isa_flags) VarExists Save
305Do not support SSE4.1 and SSE4.2 built-in functions and code generation
306
307mavx
308Target Report Mask(ISA_AVX) Var(ix86_isa_flags) VarExists Save
309Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 and AVX built-in functions and code generation
310
311mfma
312Target Report Mask(ISA_FMA) Var(ix86_isa_flags) VarExists Save
313Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and FMA built-in functions and code generation
314
315msse4a
316Target Report Mask(ISA_SSE4A) Var(ix86_isa_flags) VarExists Save
317Support MMX, SSE, SSE2, SSE3 and SSE4A built-in functions and code generation
318
319mfma4
320Target Report Mask(ISA_FMA4) Var(ix86_isa_flags) VarExists Save
321Support FMA4 built-in functions and code generation 
322
323mxop
324Target Report Mask(ISA_XOP) Var(ix86_isa_flags) VarExists Save
325Support XOP built-in functions and code generation 
326
327mlwp
328Target Report Mask(ISA_LWP) Var(ix86_isa_flags) VarExists Save
329Support LWP built-in functions and code generation 
330
331mabm
332Target Report Mask(ISA_ABM) Var(ix86_isa_flags) VarExists Save
333Support code generation of Advanced Bit Manipulation (ABM) instructions.
334
335mpopcnt
336Target Report Mask(ISA_POPCNT) Var(ix86_isa_flags) VarExists Save
337Support code generation of popcnt instruction.
338
339mcx16
340Target Report Mask(ISA_CX16) Var(ix86_isa_flags) VarExists Save
341Support code generation of cmpxchg16b instruction.
342
343msahf
344Target Report Mask(ISA_SAHF) Var(ix86_isa_flags) VarExists Save
345Support code generation of sahf instruction in 64bit x86-64 code.
346
347mmovbe
348Target Report Mask(ISA_MOVBE) Var(ix86_isa_flags) VarExists Save
349Support code generation of movbe instruction.
350
351mcrc32
352Target Report Mask(ISA_CRC32) Var(ix86_isa_flags) VarExists Save
353Support code generation of crc32 instruction.
354
355maes
356Target Report Mask(ISA_AES) Var(ix86_isa_flags) VarExists Save
357Support AES built-in functions and code generation
358
359mpclmul
360Target Report Mask(ISA_PCLMUL) Var(ix86_isa_flags) VarExists Save
361Support PCLMUL built-in functions and code generation
362
363msse2avx
364Target Report Var(ix86_sse2avx)
365Encode SSE instructions with VEX prefix
366