1/* Definitions of target machine for GCC for IA-32. 2 Copyright (C) 1988-2020 Free Software Foundation, Inc. 3 4This file is part of GCC. 5 6GCC is free software; you can redistribute it and/or modify 7it under the terms of the GNU General Public License as published by 8the Free Software Foundation; either version 3, or (at your option) 9any later version. 10 11GCC is distributed in the hope that it will be useful, 12but WITHOUT ANY WARRANTY; without even the implied warranty of 13MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14GNU General Public License for more details. 15 16Under Section 7 of GPL version 3, you are granted additional 17permissions described in the GCC Runtime Library Exception, version 183.1, as published by the Free Software Foundation. 19 20You should have received a copy of the GNU General Public License and 21a copy of the GCC Runtime Library Exception along with this program; 22see the files COPYING3 and COPYING.RUNTIME respectively. If not, see 23<http://www.gnu.org/licenses/>. */ 24 25/* The purpose of this file is to define the characteristics of the i386, 26 independent of assembler syntax or operating system. 27 28 Three other files build on this one to describe a specific assembler syntax: 29 bsd386.h, att386.h, and sun386.h. 30 31 The actual tm.h file for a particular system should include 32 this file, and then the file for the appropriate assembler syntax. 33 34 Many macros that specify assembler syntax are omitted entirely from 35 this file because they really belong in the files for particular 36 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR, 37 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many 38 that start with ASM_ or end in ASM_OP. */ 39 40/* Redefines for option macros. */ 41 42#define TARGET_64BIT TARGET_ISA_64BIT 43#define TARGET_64BIT_P(x) TARGET_ISA_64BIT_P(x) 44#define TARGET_MMX TARGET_ISA_MMX 45#define TARGET_MMX_P(x) TARGET_ISA_MMX_P(x) 46#define TARGET_3DNOW TARGET_ISA_3DNOW 47#define TARGET_3DNOW_P(x) TARGET_ISA_3DNOW_P(x) 48#define TARGET_3DNOW_A TARGET_ISA_3DNOW_A 49#define TARGET_3DNOW_A_P(x) TARGET_ISA_3DNOW_A_P(x) 50#define TARGET_SSE TARGET_ISA_SSE 51#define TARGET_SSE_P(x) TARGET_ISA_SSE_P(x) 52#define TARGET_SSE2 TARGET_ISA_SSE2 53#define TARGET_SSE2_P(x) TARGET_ISA_SSE2_P(x) 54#define TARGET_SSE3 TARGET_ISA_SSE3 55#define TARGET_SSE3_P(x) TARGET_ISA_SSE3_P(x) 56#define TARGET_SSSE3 TARGET_ISA_SSSE3 57#define TARGET_SSSE3_P(x) TARGET_ISA_SSSE3_P(x) 58#define TARGET_SSE4_1 TARGET_ISA_SSE4_1 59#define TARGET_SSE4_1_P(x) TARGET_ISA_SSE4_1_P(x) 60#define TARGET_SSE4_2 TARGET_ISA_SSE4_2 61#define TARGET_SSE4_2_P(x) TARGET_ISA_SSE4_2_P(x) 62#define TARGET_AVX TARGET_ISA_AVX 63#define TARGET_AVX_P(x) TARGET_ISA_AVX_P(x) 64#define TARGET_AVX2 TARGET_ISA_AVX2 65#define TARGET_AVX2_P(x) TARGET_ISA_AVX2_P(x) 66#define TARGET_AVX512F TARGET_ISA_AVX512F 67#define TARGET_AVX512F_P(x) TARGET_ISA_AVX512F_P(x) 68#define TARGET_AVX512PF TARGET_ISA_AVX512PF 69#define TARGET_AVX512PF_P(x) TARGET_ISA_AVX512PF_P(x) 70#define TARGET_AVX512ER TARGET_ISA_AVX512ER 71#define TARGET_AVX512ER_P(x) TARGET_ISA_AVX512ER_P(x) 72#define TARGET_AVX512CD TARGET_ISA_AVX512CD 73#define TARGET_AVX512CD_P(x) TARGET_ISA_AVX512CD_P(x) 74#define TARGET_AVX512DQ TARGET_ISA_AVX512DQ 75#define TARGET_AVX512DQ_P(x) TARGET_ISA_AVX512DQ_P(x) 76#define TARGET_AVX512BW TARGET_ISA_AVX512BW 77#define TARGET_AVX512BW_P(x) TARGET_ISA_AVX512BW_P(x) 78#define TARGET_AVX512VL TARGET_ISA_AVX512VL 79#define TARGET_AVX512VL_P(x) TARGET_ISA_AVX512VL_P(x) 80#define TARGET_AVX512VBMI TARGET_ISA_AVX512VBMI 81#define TARGET_AVX512VBMI_P(x) TARGET_ISA_AVX512VBMI_P(x) 82#define TARGET_AVX512IFMA TARGET_ISA_AVX512IFMA 83#define TARGET_AVX512IFMA_P(x) TARGET_ISA_AVX512IFMA_P(x) 84#define TARGET_AVX5124FMAPS TARGET_ISA2_AVX5124FMAPS 85#define TARGET_AVX5124FMAPS_P(x) TARGET_ISA2_AVX5124FMAPS_P(x) 86#define TARGET_AVX5124VNNIW TARGET_ISA2_AVX5124VNNIW 87#define TARGET_AVX5124VNNIW_P(x) TARGET_ISA2_AVX5124VNNIW_P(x) 88#define TARGET_AVX512VBMI2 TARGET_ISA_AVX512VBMI2 89#define TARGET_AVX512VBMI2_P(x) TARGET_ISA_AVX512VBMI2_P(x) 90#define TARGET_AVX512VPOPCNTDQ TARGET_ISA_AVX512VPOPCNTDQ 91#define TARGET_AVX512VPOPCNTDQ_P(x) TARGET_ISA_AVX512VPOPCNTDQ_P(x) 92#define TARGET_AVX512VNNI TARGET_ISA_AVX512VNNI 93#define TARGET_AVX512VNNI_P(x) TARGET_ISA_AVX512VNNI_P(x) 94#define TARGET_AVX512BITALG TARGET_ISA_AVX512BITALG 95#define TARGET_AVX512BITALG_P(x) TARGET_ISA_AVX512BITALG_P(x) 96#define TARGET_AVX512VP2INTERSECT TARGET_ISA2_AVX512VP2INTERSECT 97#define TARGET_AVX512VP2INTERSECT_P(x) TARGET_ISA2_AVX512VP2INTERSECT_P(x) 98#define TARGET_FMA TARGET_ISA_FMA 99#define TARGET_FMA_P(x) TARGET_ISA_FMA_P(x) 100#define TARGET_SSE4A TARGET_ISA_SSE4A 101#define TARGET_SSE4A_P(x) TARGET_ISA_SSE4A_P(x) 102#define TARGET_FMA4 TARGET_ISA_FMA4 103#define TARGET_FMA4_P(x) TARGET_ISA_FMA4_P(x) 104#define TARGET_XOP TARGET_ISA_XOP 105#define TARGET_XOP_P(x) TARGET_ISA_XOP_P(x) 106#define TARGET_LWP TARGET_ISA_LWP 107#define TARGET_LWP_P(x) TARGET_ISA_LWP_P(x) 108#define TARGET_ABM TARGET_ISA_ABM 109#define TARGET_ABM_P(x) TARGET_ISA_ABM_P(x) 110#define TARGET_PCONFIG TARGET_ISA2_PCONFIG 111#define TARGET_PCONFIG_P(x) TARGET_ISA2_PCONFIG_P(x) 112#define TARGET_WBNOINVD TARGET_ISA2_WBNOINVD 113#define TARGET_WBNOINVD_P(x) TARGET_ISA2_WBNOINVD_P(x) 114#define TARGET_SGX TARGET_ISA2_SGX 115#define TARGET_SGX_P(x) TARGET_ISA2_SGX_P(x) 116#define TARGET_RDPID TARGET_ISA2_RDPID 117#define TARGET_RDPID_P(x) TARGET_ISA2_RDPID_P(x) 118#define TARGET_GFNI TARGET_ISA_GFNI 119#define TARGET_GFNI_P(x) TARGET_ISA_GFNI_P(x) 120#define TARGET_VAES TARGET_ISA2_VAES 121#define TARGET_VAES_P(x) TARGET_ISA2_VAES_P(x) 122#define TARGET_VPCLMULQDQ TARGET_ISA_VPCLMULQDQ 123#define TARGET_VPCLMULQDQ_P(x) TARGET_ISA_VPCLMULQDQ_P(x) 124#define TARGET_BMI TARGET_ISA_BMI 125#define TARGET_BMI_P(x) TARGET_ISA_BMI_P(x) 126#define TARGET_BMI2 TARGET_ISA_BMI2 127#define TARGET_BMI2_P(x) TARGET_ISA_BMI2_P(x) 128#define TARGET_LZCNT TARGET_ISA_LZCNT 129#define TARGET_LZCNT_P(x) TARGET_ISA_LZCNT_P(x) 130#define TARGET_TBM TARGET_ISA_TBM 131#define TARGET_TBM_P(x) TARGET_ISA_TBM_P(x) 132#define TARGET_POPCNT TARGET_ISA_POPCNT 133#define TARGET_POPCNT_P(x) TARGET_ISA_POPCNT_P(x) 134#define TARGET_SAHF TARGET_ISA_SAHF 135#define TARGET_SAHF_P(x) TARGET_ISA_SAHF_P(x) 136#define TARGET_MOVBE TARGET_ISA2_MOVBE 137#define TARGET_MOVBE_P(x) TARGET_ISA2_MOVBE_P(x) 138#define TARGET_CRC32 TARGET_ISA_CRC32 139#define TARGET_CRC32_P(x) TARGET_ISA_CRC32_P(x) 140#define TARGET_AES TARGET_ISA_AES 141#define TARGET_AES_P(x) TARGET_ISA_AES_P(x) 142#define TARGET_SHA TARGET_ISA_SHA 143#define TARGET_SHA_P(x) TARGET_ISA_SHA_P(x) 144#define TARGET_CLFLUSHOPT TARGET_ISA_CLFLUSHOPT 145#define TARGET_CLFLUSHOPT_P(x) TARGET_ISA_CLFLUSHOPT_P(x) 146#define TARGET_CLZERO TARGET_ISA2_CLZERO 147#define TARGET_CLZERO_P(x) TARGET_ISA2_CLZERO_P(x) 148#define TARGET_XSAVEC TARGET_ISA_XSAVEC 149#define TARGET_XSAVEC_P(x) TARGET_ISA_XSAVEC_P(x) 150#define TARGET_XSAVES TARGET_ISA_XSAVES 151#define TARGET_XSAVES_P(x) TARGET_ISA_XSAVES_P(x) 152#define TARGET_PCLMUL TARGET_ISA_PCLMUL 153#define TARGET_PCLMUL_P(x) TARGET_ISA_PCLMUL_P(x) 154#define TARGET_CMPXCHG16B TARGET_ISA2_CX16 155#define TARGET_CMPXCHG16B_P(x) TARGET_ISA2_CX16_P(x) 156#define TARGET_FSGSBASE TARGET_ISA_FSGSBASE 157#define TARGET_FSGSBASE_P(x) TARGET_ISA_FSGSBASE_P(x) 158#define TARGET_RDRND TARGET_ISA_RDRND 159#define TARGET_RDRND_P(x) TARGET_ISA_RDRND_P(x) 160#define TARGET_F16C TARGET_ISA_F16C 161#define TARGET_F16C_P(x) TARGET_ISA_F16C_P(x) 162#define TARGET_RTM TARGET_ISA_RTM 163#define TARGET_RTM_P(x) TARGET_ISA_RTM_P(x) 164#define TARGET_HLE TARGET_ISA2_HLE 165#define TARGET_HLE_P(x) TARGET_ISA2_HLE_P(x) 166#define TARGET_RDSEED TARGET_ISA_RDSEED 167#define TARGET_RDSEED_P(x) TARGET_ISA_RDSEED_P(x) 168#define TARGET_PRFCHW TARGET_ISA_PRFCHW 169#define TARGET_PRFCHW_P(x) TARGET_ISA_PRFCHW_P(x) 170#define TARGET_ADX TARGET_ISA_ADX 171#define TARGET_ADX_P(x) TARGET_ISA_ADX_P(x) 172#define TARGET_FXSR TARGET_ISA_FXSR 173#define TARGET_FXSR_P(x) TARGET_ISA_FXSR_P(x) 174#define TARGET_XSAVE TARGET_ISA_XSAVE 175#define TARGET_XSAVE_P(x) TARGET_ISA_XSAVE_P(x) 176#define TARGET_XSAVEOPT TARGET_ISA_XSAVEOPT 177#define TARGET_XSAVEOPT_P(x) TARGET_ISA_XSAVEOPT_P(x) 178#define TARGET_PREFETCHWT1 TARGET_ISA_PREFETCHWT1 179#define TARGET_PREFETCHWT1_P(x) TARGET_ISA_PREFETCHWT1_P(x) 180#define TARGET_CLWB TARGET_ISA_CLWB 181#define TARGET_CLWB_P(x) TARGET_ISA_CLWB_P(x) 182#define TARGET_MWAITX TARGET_ISA2_MWAITX 183#define TARGET_MWAITX_P(x) TARGET_ISA2_MWAITX_P(x) 184#define TARGET_PKU TARGET_ISA_PKU 185#define TARGET_PKU_P(x) TARGET_ISA_PKU_P(x) 186#define TARGET_SHSTK TARGET_ISA_SHSTK 187#define TARGET_SHSTK_P(x) TARGET_ISA_SHSTK_P(x) 188#define TARGET_MOVDIRI TARGET_ISA_MOVDIRI 189#define TARGET_MOVDIRI_P(x) TARGET_ISA_MOVDIRI_P(x) 190#define TARGET_MOVDIR64B TARGET_ISA2_MOVDIR64B 191#define TARGET_MOVDIR64B_P(x) TARGET_ISA2_MOVDIR64B_P(x) 192#define TARGET_WAITPKG TARGET_ISA2_WAITPKG 193#define TARGET_WAITPKG_P(x) TARGET_ISA2_WAITPKG_P(x) 194#define TARGET_CLDEMOTE TARGET_ISA2_CLDEMOTE 195#define TARGET_CLDEMOTE_P(x) TARGET_ISA2_CLDEMOTE_P(x) 196#define TARGET_PTWRITE TARGET_ISA2_PTWRITE 197#define TARGET_PTWRITE_P(x) TARGET_ISA2_PTWRITE_P(x) 198#define TARGET_AVX512BF16 TARGET_ISA2_AVX512BF16 199#define TARGET_AVX512BF16_P(x) TARGET_ISA2_AVX512BF16_P(x) 200#define TARGET_ENQCMD TARGET_ISA2_ENQCMD 201#define TARGET_ENQCMD_P(x) TARGET_ISA2_ENQCMD_P(x) 202 203#define TARGET_LP64 TARGET_ABI_64 204#define TARGET_LP64_P(x) TARGET_ABI_64_P(x) 205#define TARGET_X32 TARGET_ABI_X32 206#define TARGET_X32_P(x) TARGET_ABI_X32_P(x) 207#define TARGET_16BIT TARGET_CODE16 208#define TARGET_16BIT_P(x) TARGET_CODE16_P(x) 209 210#define TARGET_MMX_WITH_SSE (TARGET_64BIT && TARGET_SSE2) 211 212#include "config/vxworks-dummy.h" 213 214#include "config/i386/i386-opts.h" 215 216#define MAX_STRINGOP_ALGS 4 217 218/* Specify what algorithm to use for stringops on known size. 219 When size is unknown, the UNKNOWN_SIZE alg is used. When size is 220 known at compile time or estimated via feedback, the SIZE array 221 is walked in order until MAX is greater then the estimate (or -1 222 means infinity). Corresponding ALG is used then. 223 When NOALIGN is true the code guaranting the alignment of the memory 224 block is skipped. 225 226 For example initializer: 227 {{256, loop}, {-1, rep_prefix_4_byte}} 228 will use loop for blocks smaller or equal to 256 bytes, rep prefix will 229 be used otherwise. */ 230struct stringop_algs 231{ 232 const enum stringop_alg unknown_size; 233 const struct stringop_strategy { 234 const int max; 235 const enum stringop_alg alg; 236 int noalign; 237 } size [MAX_STRINGOP_ALGS]; 238}; 239 240/* Define the specific costs for a given cpu. NB: hard_register is used 241 by TARGET_REGISTER_MOVE_COST and TARGET_MEMORY_MOVE_COST to compute 242 hard register move costs by register allocator. Relative costs of 243 pseudo register load and store versus pseudo register moves in RTL 244 expressions for TARGET_RTX_COSTS can be different from relative 245 costs of hard registers to get the most efficient operations with 246 pseudo registers. */ 247 248struct processor_costs { 249 /* Costs used by register allocator. integer->integer register move 250 cost is 2. */ 251 struct 252 { 253 const int movzbl_load; /* cost of loading using movzbl */ 254 const int int_load[3]; /* cost of loading integer registers 255 in QImode, HImode and SImode relative 256 to reg-reg move (2). */ 257 const int int_store[3]; /* cost of storing integer register 258 in QImode, HImode and SImode */ 259 const int fp_move; /* cost of reg,reg fld/fst */ 260 const int fp_load[3]; /* cost of loading FP register 261 in SFmode, DFmode and XFmode */ 262 const int fp_store[3]; /* cost of storing FP register 263 in SFmode, DFmode and XFmode */ 264 const int mmx_move; /* cost of moving MMX register. */ 265 const int mmx_load[2]; /* cost of loading MMX register 266 in SImode and DImode */ 267 const int mmx_store[2]; /* cost of storing MMX register 268 in SImode and DImode */ 269 const int xmm_move; /* cost of moving XMM register. */ 270 const int ymm_move; /* cost of moving XMM register. */ 271 const int zmm_move; /* cost of moving XMM register. */ 272 const int sse_load[5]; /* cost of loading SSE register 273 in 32bit, 64bit, 128bit, 256bit and 512bit */ 274 const int sse_store[5]; /* cost of storing SSE register 275 in SImode, DImode and TImode. */ 276 const int sse_to_integer; /* cost of moving SSE register to integer. */ 277 const int integer_to_sse; /* cost of moving integer register to SSE. */ 278 } hard_register; 279 280 const int add; /* cost of an add instruction */ 281 const int lea; /* cost of a lea instruction */ 282 const int shift_var; /* variable shift costs */ 283 const int shift_const; /* constant shift costs */ 284 const int mult_init[5]; /* cost of starting a multiply 285 in QImode, HImode, SImode, DImode, TImode*/ 286 const int mult_bit; /* cost of multiply per each bit set */ 287 const int divide[5]; /* cost of a divide/mod 288 in QImode, HImode, SImode, DImode, TImode*/ 289 int movsx; /* The cost of movsx operation. */ 290 int movzx; /* The cost of movzx operation. */ 291 const int large_insn; /* insns larger than this cost more */ 292 const int move_ratio; /* The threshold of number of scalar 293 memory-to-memory move insns. */ 294 const int clear_ratio; /* The threshold of number of scalar 295 memory clearing insns. */ 296 const int int_load[3]; /* cost of loading integer registers 297 in QImode, HImode and SImode relative 298 to reg-reg move (2). */ 299 const int int_store[3]; /* cost of storing integer register 300 in QImode, HImode and SImode */ 301 const int sse_load[5]; /* cost of loading SSE register 302 in 32bit, 64bit, 128bit, 256bit and 512bit */ 303 const int sse_store[5]; /* cost of storing SSE register 304 in 32bit, 64bit, 128bit, 256bit and 512bit */ 305 const int sse_unaligned_load[5];/* cost of unaligned load. */ 306 const int sse_unaligned_store[5];/* cost of unaligned store. */ 307 const int xmm_move, ymm_move, /* cost of moving XMM and YMM register. */ 308 zmm_move; 309 const int sse_to_integer; /* cost of moving SSE register to integer. */ 310 const int gather_static, gather_per_elt; /* Cost of gather load is computed 311 as static + per_item * nelts. */ 312 const int scatter_static, scatter_per_elt; /* Cost of gather store is 313 computed as static + per_item * nelts. */ 314 const int l1_cache_size; /* size of l1 cache, in kilobytes. */ 315 const int l2_cache_size; /* size of l2 cache, in kilobytes. */ 316 const int prefetch_block; /* bytes moved to cache for prefetch. */ 317 const int simultaneous_prefetches; /* number of parallel prefetch 318 operations. */ 319 const int branch_cost; /* Default value for BRANCH_COST. */ 320 const int fadd; /* cost of FADD and FSUB instructions. */ 321 const int fmul; /* cost of FMUL instruction. */ 322 const int fdiv; /* cost of FDIV instruction. */ 323 const int fabs; /* cost of FABS instruction. */ 324 const int fchs; /* cost of FCHS instruction. */ 325 const int fsqrt; /* cost of FSQRT instruction. */ 326 /* Specify what algorithm 327 to use for stringops on unknown size. */ 328 const int sse_op; /* cost of cheap SSE instruction. */ 329 const int addss; /* cost of ADDSS/SD SUBSS/SD instructions. */ 330 const int mulss; /* cost of MULSS instructions. */ 331 const int mulsd; /* cost of MULSD instructions. */ 332 const int fmass; /* cost of FMASS instructions. */ 333 const int fmasd; /* cost of FMASD instructions. */ 334 const int divss; /* cost of DIVSS instructions. */ 335 const int divsd; /* cost of DIVSD instructions. */ 336 const int sqrtss; /* cost of SQRTSS instructions. */ 337 const int sqrtsd; /* cost of SQRTSD instructions. */ 338 const int reassoc_int, reassoc_fp, reassoc_vec_int, reassoc_vec_fp; 339 /* Specify reassociation width for integer, 340 fp, vector integer and vector fp 341 operations. Generally should correspond 342 to number of instructions executed in 343 parallel. See also 344 ix86_reassociation_width. */ 345 struct stringop_algs *memcpy, *memset; 346 const int cond_taken_branch_cost; /* Cost of taken branch for vectorizer 347 cost model. */ 348 const int cond_not_taken_branch_cost;/* Cost of not taken branch for 349 vectorizer cost model. */ 350 351 /* The "0:0:8" label alignment specified for some processors generates 352 secondary 8-byte alignment only for those label/jump/loop targets 353 which have primary alignment. */ 354 const char *const align_loop; /* Loop alignment. */ 355 const char *const align_jump; /* Jump alignment. */ 356 const char *const align_label; /* Label alignment. */ 357 const char *const align_func; /* Function alignment. */ 358}; 359 360extern const struct processor_costs *ix86_cost; 361extern const struct processor_costs ix86_size_cost; 362 363#define ix86_cur_cost() \ 364 (optimize_insn_for_size_p () ? &ix86_size_cost: ix86_cost) 365 366/* Macros used in the machine description to test the flags. */ 367 368/* configure can arrange to change it. */ 369 370#ifndef TARGET_CPU_DEFAULT 371#define TARGET_CPU_DEFAULT PROCESSOR_GENERIC 372#endif 373 374#ifndef TARGET_FPMATH_DEFAULT 375#define TARGET_FPMATH_DEFAULT \ 376 (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387) 377#endif 378 379#ifndef TARGET_FPMATH_DEFAULT_P 380#define TARGET_FPMATH_DEFAULT_P(x) \ 381 (TARGET_64BIT_P(x) && TARGET_SSE_P(x) ? FPMATH_SSE : FPMATH_387) 382#endif 383 384/* If the i387 is disabled or -miamcu is used , then do not return 385 values in it. */ 386#define TARGET_FLOAT_RETURNS_IN_80387 \ 387 (TARGET_FLOAT_RETURNS && TARGET_80387 && !TARGET_IAMCU) 388#define TARGET_FLOAT_RETURNS_IN_80387_P(x) \ 389 (TARGET_FLOAT_RETURNS_P(x) && TARGET_80387_P(x) && !TARGET_IAMCU_P(x)) 390 391/* 64bit Sledgehammer mode. For libgcc2 we make sure this is a 392 compile-time constant. */ 393#ifdef IN_LIBGCC2 394#undef TARGET_64BIT 395#ifdef __x86_64__ 396#define TARGET_64BIT 1 397#else 398#define TARGET_64BIT 0 399#endif 400#else 401#ifndef TARGET_BI_ARCH 402#undef TARGET_64BIT 403#undef TARGET_64BIT_P 404#if TARGET_64BIT_DEFAULT 405#define TARGET_64BIT 1 406#define TARGET_64BIT_P(x) 1 407#else 408#define TARGET_64BIT 0 409#define TARGET_64BIT_P(x) 0 410#endif 411#endif 412#endif 413 414#define HAS_LONG_COND_BRANCH 1 415#define HAS_LONG_UNCOND_BRANCH 1 416 417#define TARGET_386 (ix86_tune == PROCESSOR_I386) 418#define TARGET_486 (ix86_tune == PROCESSOR_I486) 419#define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM) 420#define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO) 421#define TARGET_GEODE (ix86_tune == PROCESSOR_GEODE) 422#define TARGET_K6 (ix86_tune == PROCESSOR_K6) 423#define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON) 424#define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4) 425#define TARGET_K8 (ix86_tune == PROCESSOR_K8) 426#define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON) 427#define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA) 428#define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2) 429#define TARGET_NEHALEM (ix86_tune == PROCESSOR_NEHALEM) 430#define TARGET_SANDYBRIDGE (ix86_tune == PROCESSOR_SANDYBRIDGE) 431#define TARGET_HASWELL (ix86_tune == PROCESSOR_HASWELL) 432#define TARGET_BONNELL (ix86_tune == PROCESSOR_BONNELL) 433#define TARGET_SILVERMONT (ix86_tune == PROCESSOR_SILVERMONT) 434#define TARGET_GOLDMONT (ix86_tune == PROCESSOR_GOLDMONT) 435#define TARGET_GOLDMONT_PLUS (ix86_tune == PROCESSOR_GOLDMONT_PLUS) 436#define TARGET_TREMONT (ix86_tune == PROCESSOR_TREMONT) 437#define TARGET_KNL (ix86_tune == PROCESSOR_KNL) 438#define TARGET_KNM (ix86_tune == PROCESSOR_KNM) 439#define TARGET_SKYLAKE (ix86_tune == PROCESSOR_SKYLAKE) 440#define TARGET_SKYLAKE_AVX512 (ix86_tune == PROCESSOR_SKYLAKE_AVX512) 441#define TARGET_CANNONLAKE (ix86_tune == PROCESSOR_CANNONLAKE) 442#define TARGET_ICELAKE_CLIENT (ix86_tune == PROCESSOR_ICELAKE_CLIENT) 443#define TARGET_ICELAKE_SERVER (ix86_tune == PROCESSOR_ICELAKE_SERVER) 444#define TARGET_CASCADELAKE (ix86_tune == PROCESSOR_CASCADELAKE) 445#define TARGET_TIGERLAKE (ix86_tune == PROCESSOR_TIGERLAKE) 446#define TARGET_COOPERLAKE (ix86_tune == PROCESSOR_COOPERLAKE) 447#define TARGET_INTEL (ix86_tune == PROCESSOR_INTEL) 448#define TARGET_GENERIC (ix86_tune == PROCESSOR_GENERIC) 449#define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10) 450#define TARGET_BDVER1 (ix86_tune == PROCESSOR_BDVER1) 451#define TARGET_BDVER2 (ix86_tune == PROCESSOR_BDVER2) 452#define TARGET_BDVER3 (ix86_tune == PROCESSOR_BDVER3) 453#define TARGET_BDVER4 (ix86_tune == PROCESSOR_BDVER4) 454#define TARGET_BTVER1 (ix86_tune == PROCESSOR_BTVER1) 455#define TARGET_BTVER2 (ix86_tune == PROCESSOR_BTVER2) 456#define TARGET_ZNVER1 (ix86_tune == PROCESSOR_ZNVER1) 457#define TARGET_ZNVER2 (ix86_tune == PROCESSOR_ZNVER2) 458#define TARGET_ZNVER3 (ix86_tune == PROCESSOR_ZNVER3) 459 460/* Feature tests against the various tunings. */ 461enum ix86_tune_indices { 462#undef DEF_TUNE 463#define DEF_TUNE(tune, name, selector) tune, 464#include "x86-tune.def" 465#undef DEF_TUNE 466X86_TUNE_LAST 467}; 468 469extern unsigned char ix86_tune_features[X86_TUNE_LAST]; 470 471#define TARGET_USE_LEAVE ix86_tune_features[X86_TUNE_USE_LEAVE] 472#define TARGET_PUSH_MEMORY ix86_tune_features[X86_TUNE_PUSH_MEMORY] 473#define TARGET_ZERO_EXTEND_WITH_AND \ 474 ix86_tune_features[X86_TUNE_ZERO_EXTEND_WITH_AND] 475#define TARGET_UNROLL_STRLEN ix86_tune_features[X86_TUNE_UNROLL_STRLEN] 476#define TARGET_BRANCH_PREDICTION_HINTS \ 477 ix86_tune_features[X86_TUNE_BRANCH_PREDICTION_HINTS] 478#define TARGET_DOUBLE_WITH_ADD ix86_tune_features[X86_TUNE_DOUBLE_WITH_ADD] 479#define TARGET_USE_SAHF ix86_tune_features[X86_TUNE_USE_SAHF] 480#define TARGET_MOVX ix86_tune_features[X86_TUNE_MOVX] 481#define TARGET_PARTIAL_REG_STALL ix86_tune_features[X86_TUNE_PARTIAL_REG_STALL] 482#define TARGET_PARTIAL_FLAG_REG_STALL \ 483 ix86_tune_features[X86_TUNE_PARTIAL_FLAG_REG_STALL] 484#define TARGET_LCP_STALL \ 485 ix86_tune_features[X86_TUNE_LCP_STALL] 486#define TARGET_USE_HIMODE_FIOP ix86_tune_features[X86_TUNE_USE_HIMODE_FIOP] 487#define TARGET_USE_SIMODE_FIOP ix86_tune_features[X86_TUNE_USE_SIMODE_FIOP] 488#define TARGET_USE_MOV0 ix86_tune_features[X86_TUNE_USE_MOV0] 489#define TARGET_USE_CLTD ix86_tune_features[X86_TUNE_USE_CLTD] 490#define TARGET_USE_XCHGB ix86_tune_features[X86_TUNE_USE_XCHGB] 491#define TARGET_SPLIT_LONG_MOVES ix86_tune_features[X86_TUNE_SPLIT_LONG_MOVES] 492#define TARGET_READ_MODIFY_WRITE ix86_tune_features[X86_TUNE_READ_MODIFY_WRITE] 493#define TARGET_READ_MODIFY ix86_tune_features[X86_TUNE_READ_MODIFY] 494#define TARGET_PROMOTE_QImode ix86_tune_features[X86_TUNE_PROMOTE_QIMODE] 495#define TARGET_FAST_PREFIX ix86_tune_features[X86_TUNE_FAST_PREFIX] 496#define TARGET_SINGLE_STRINGOP ix86_tune_features[X86_TUNE_SINGLE_STRINGOP] 497#define TARGET_MISALIGNED_MOVE_STRING_PRO_EPILOGUES \ 498 ix86_tune_features[X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES] 499#define TARGET_QIMODE_MATH ix86_tune_features[X86_TUNE_QIMODE_MATH] 500#define TARGET_HIMODE_MATH ix86_tune_features[X86_TUNE_HIMODE_MATH] 501#define TARGET_PROMOTE_QI_REGS ix86_tune_features[X86_TUNE_PROMOTE_QI_REGS] 502#define TARGET_PROMOTE_HI_REGS ix86_tune_features[X86_TUNE_PROMOTE_HI_REGS] 503#define TARGET_SINGLE_POP ix86_tune_features[X86_TUNE_SINGLE_POP] 504#define TARGET_DOUBLE_POP ix86_tune_features[X86_TUNE_DOUBLE_POP] 505#define TARGET_SINGLE_PUSH ix86_tune_features[X86_TUNE_SINGLE_PUSH] 506#define TARGET_DOUBLE_PUSH ix86_tune_features[X86_TUNE_DOUBLE_PUSH] 507#define TARGET_INTEGER_DFMODE_MOVES \ 508 ix86_tune_features[X86_TUNE_INTEGER_DFMODE_MOVES] 509#define TARGET_PARTIAL_REG_DEPENDENCY \ 510 ix86_tune_features[X86_TUNE_PARTIAL_REG_DEPENDENCY] 511#define TARGET_SSE_PARTIAL_REG_DEPENDENCY \ 512 ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY] 513#define TARGET_SSE_UNALIGNED_LOAD_OPTIMAL \ 514 ix86_tune_features[X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL] 515#define TARGET_SSE_UNALIGNED_STORE_OPTIMAL \ 516 ix86_tune_features[X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL] 517#define TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL \ 518 ix86_tune_features[X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL] 519#define TARGET_SSE_SPLIT_REGS ix86_tune_features[X86_TUNE_SSE_SPLIT_REGS] 520#define TARGET_SSE_TYPELESS_STORES \ 521 ix86_tune_features[X86_TUNE_SSE_TYPELESS_STORES] 522#define TARGET_SSE_LOAD0_BY_PXOR ix86_tune_features[X86_TUNE_SSE_LOAD0_BY_PXOR] 523#define TARGET_MEMORY_MISMATCH_STALL \ 524 ix86_tune_features[X86_TUNE_MEMORY_MISMATCH_STALL] 525#define TARGET_PROLOGUE_USING_MOVE \ 526 ix86_tune_features[X86_TUNE_PROLOGUE_USING_MOVE] 527#define TARGET_EPILOGUE_USING_MOVE \ 528 ix86_tune_features[X86_TUNE_EPILOGUE_USING_MOVE] 529#define TARGET_SHIFT1 ix86_tune_features[X86_TUNE_SHIFT1] 530#define TARGET_USE_FFREEP ix86_tune_features[X86_TUNE_USE_FFREEP] 531#define TARGET_INTER_UNIT_MOVES_TO_VEC \ 532 ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES_TO_VEC] 533#define TARGET_INTER_UNIT_MOVES_FROM_VEC \ 534 ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES_FROM_VEC] 535#define TARGET_INTER_UNIT_CONVERSIONS \ 536 ix86_tune_features[X86_TUNE_INTER_UNIT_CONVERSIONS] 537#define TARGET_FOUR_JUMP_LIMIT ix86_tune_features[X86_TUNE_FOUR_JUMP_LIMIT] 538#define TARGET_SCHEDULE ix86_tune_features[X86_TUNE_SCHEDULE] 539#define TARGET_USE_BT ix86_tune_features[X86_TUNE_USE_BT] 540#define TARGET_USE_INCDEC ix86_tune_features[X86_TUNE_USE_INCDEC] 541#define TARGET_PAD_RETURNS ix86_tune_features[X86_TUNE_PAD_RETURNS] 542#define TARGET_PAD_SHORT_FUNCTION \ 543 ix86_tune_features[X86_TUNE_PAD_SHORT_FUNCTION] 544#define TARGET_EXT_80387_CONSTANTS \ 545 ix86_tune_features[X86_TUNE_EXT_80387_CONSTANTS] 546#define TARGET_AVOID_VECTOR_DECODE \ 547 ix86_tune_features[X86_TUNE_AVOID_VECTOR_DECODE] 548#define TARGET_TUNE_PROMOTE_HIMODE_IMUL \ 549 ix86_tune_features[X86_TUNE_PROMOTE_HIMODE_IMUL] 550#define TARGET_SLOW_IMUL_IMM32_MEM \ 551 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM32_MEM] 552#define TARGET_SLOW_IMUL_IMM8 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM8] 553#define TARGET_MOVE_M1_VIA_OR ix86_tune_features[X86_TUNE_MOVE_M1_VIA_OR] 554#define TARGET_NOT_UNPAIRABLE ix86_tune_features[X86_TUNE_NOT_UNPAIRABLE] 555#define TARGET_NOT_VECTORMODE ix86_tune_features[X86_TUNE_NOT_VECTORMODE] 556#define TARGET_USE_VECTOR_FP_CONVERTS \ 557 ix86_tune_features[X86_TUNE_USE_VECTOR_FP_CONVERTS] 558#define TARGET_USE_VECTOR_CONVERTS \ 559 ix86_tune_features[X86_TUNE_USE_VECTOR_CONVERTS] 560#define TARGET_SLOW_PSHUFB \ 561 ix86_tune_features[X86_TUNE_SLOW_PSHUFB] 562#define TARGET_AVOID_4BYTE_PREFIXES \ 563 ix86_tune_features[X86_TUNE_AVOID_4BYTE_PREFIXES] 564#define TARGET_USE_GATHER \ 565 ix86_tune_features[X86_TUNE_USE_GATHER] 566#define TARGET_FUSE_CMP_AND_BRANCH_32 \ 567 ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_32] 568#define TARGET_FUSE_CMP_AND_BRANCH_64 \ 569 ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_64] 570#define TARGET_FUSE_CMP_AND_BRANCH \ 571 (TARGET_64BIT ? TARGET_FUSE_CMP_AND_BRANCH_64 \ 572 : TARGET_FUSE_CMP_AND_BRANCH_32) 573#define TARGET_FUSE_CMP_AND_BRANCH_SOFLAGS \ 574 ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS] 575#define TARGET_FUSE_ALU_AND_BRANCH \ 576 ix86_tune_features[X86_TUNE_FUSE_ALU_AND_BRANCH] 577#define TARGET_OPT_AGU ix86_tune_features[X86_TUNE_OPT_AGU] 578#define TARGET_AVOID_LEA_FOR_ADDR \ 579 ix86_tune_features[X86_TUNE_AVOID_LEA_FOR_ADDR] 580#define TARGET_SOFTWARE_PREFETCHING_BENEFICIAL \ 581 ix86_tune_features[X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL] 582#define TARGET_AVX256_SPLIT_REGS \ 583 ix86_tune_features[X86_TUNE_AVX256_SPLIT_REGS] 584#define TARGET_GENERAL_REGS_SSE_SPILL \ 585 ix86_tune_features[X86_TUNE_GENERAL_REGS_SSE_SPILL] 586#define TARGET_AVOID_MEM_OPND_FOR_CMOVE \ 587 ix86_tune_features[X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE] 588#define TARGET_SPLIT_MEM_OPND_FOR_FP_CONVERTS \ 589 ix86_tune_features[X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS] 590#define TARGET_ADJUST_UNROLL \ 591 ix86_tune_features[X86_TUNE_ADJUST_UNROLL] 592#define TARGET_AVOID_FALSE_DEP_FOR_BMI \ 593 ix86_tune_features[X86_TUNE_AVOID_FALSE_DEP_FOR_BMI] 594#define TARGET_ONE_IF_CONV_INSN \ 595 ix86_tune_features[X86_TUNE_ONE_IF_CONV_INSN] 596#define TARGET_AVOID_MFENCE ix86_tune_features[X86_TUNE_AVOID_MFENCE] 597#define TARGET_EMIT_VZEROUPPER \ 598 ix86_tune_features[X86_TUNE_EMIT_VZEROUPPER] 599#define TARGET_EXPAND_ABS \ 600 ix86_tune_features[X86_TUNE_EXPAND_ABS] 601 602/* Feature tests against the various architecture variations. */ 603enum ix86_arch_indices { 604 X86_ARCH_CMOV, 605 X86_ARCH_CMPXCHG, 606 X86_ARCH_CMPXCHG8B, 607 X86_ARCH_XADD, 608 X86_ARCH_BSWAP, 609 610 X86_ARCH_LAST 611}; 612 613extern unsigned char ix86_arch_features[X86_ARCH_LAST]; 614 615#define TARGET_CMOV ix86_arch_features[X86_ARCH_CMOV] 616#define TARGET_CMPXCHG ix86_arch_features[X86_ARCH_CMPXCHG] 617#define TARGET_CMPXCHG8B ix86_arch_features[X86_ARCH_CMPXCHG8B] 618#define TARGET_XADD ix86_arch_features[X86_ARCH_XADD] 619#define TARGET_BSWAP ix86_arch_features[X86_ARCH_BSWAP] 620 621/* For sane SSE instruction set generation we need fcomi instruction. 622 It is safe to enable all CMOVE instructions. Also, RDRAND intrinsic 623 expands to a sequence that includes conditional move. */ 624#define TARGET_CMOVE (TARGET_CMOV || TARGET_SSE || TARGET_RDRND) 625 626#define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387) 627 628extern unsigned char x86_prefetch_sse; 629#define TARGET_PREFETCH_SSE x86_prefetch_sse 630 631#define ASSEMBLER_DIALECT (ix86_asm_dialect) 632 633#define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0) 634#define TARGET_MIX_SSE_I387 \ 635 ((ix86_fpmath & (FPMATH_SSE | FPMATH_387)) == (FPMATH_SSE | FPMATH_387)) 636 637#define TARGET_HARD_SF_REGS (TARGET_80387 || TARGET_MMX || TARGET_SSE) 638#define TARGET_HARD_DF_REGS (TARGET_80387 || TARGET_SSE) 639#define TARGET_HARD_XF_REGS (TARGET_80387) 640 641#define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU) 642#define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2) 643#define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS) 644#define TARGET_SUN_TLS 0 645 646#ifndef TARGET_64BIT_DEFAULT 647#define TARGET_64BIT_DEFAULT 0 648#endif 649#ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 650#define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0 651#endif 652 653#define TARGET_SSP_GLOBAL_GUARD (ix86_stack_protector_guard == SSP_GLOBAL) 654#define TARGET_SSP_TLS_GUARD (ix86_stack_protector_guard == SSP_TLS) 655 656/* Fence to use after loop using storent. */ 657 658extern tree x86_mfence; 659#define FENCE_FOLLOWING_MOVNT x86_mfence 660 661/* Once GDB has been enhanced to deal with functions without frame 662 pointers, we can change this to allow for elimination of 663 the frame pointer in leaf functions. */ 664#define TARGET_DEFAULT 0 665 666/* Extra bits to force. */ 667#define TARGET_SUBTARGET_DEFAULT 0 668#define TARGET_SUBTARGET_ISA_DEFAULT 0 669 670/* Extra bits to force on w/ 32-bit mode. */ 671#define TARGET_SUBTARGET32_DEFAULT 0 672#define TARGET_SUBTARGET32_ISA_DEFAULT 0 673 674/* Extra bits to force on w/ 64-bit mode. */ 675#define TARGET_SUBTARGET64_DEFAULT 0 676/* Enable MMX, SSE and SSE2 by default. */ 677#define TARGET_SUBTARGET64_ISA_DEFAULT \ 678 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2) 679 680/* Replace MACH-O, ifdefs by in-line tests, where possible. 681 (a) Macros defined in config/i386/darwin.h */ 682#define TARGET_MACHO 0 683#define TARGET_MACHO_SYMBOL_STUBS 0 684#define MACHOPIC_ATT_STUB 0 685/* (b) Macros defined in config/darwin.h */ 686#define MACHO_DYNAMIC_NO_PIC_P 0 687#define MACHOPIC_INDIRECT 0 688#define MACHOPIC_PURE 0 689 690/* For the RDOS */ 691#define TARGET_RDOS 0 692 693/* For the Windows 64-bit ABI. */ 694#define TARGET_64BIT_MS_ABI (TARGET_64BIT && ix86_cfun_abi () == MS_ABI) 695 696/* For the Windows 32-bit ABI. */ 697#define TARGET_32BIT_MS_ABI (!TARGET_64BIT && ix86_cfun_abi () == MS_ABI) 698 699/* This is re-defined by cygming.h. */ 700#define TARGET_SEH 0 701 702/* The default abi used by target. */ 703#define DEFAULT_ABI SYSV_ABI 704 705/* The default TLS segment register used by target. */ 706#define DEFAULT_TLS_SEG_REG \ 707 (TARGET_64BIT ? ADDR_SPACE_SEG_FS : ADDR_SPACE_SEG_GS) 708 709/* Subtargets may reset this to 1 in order to enable 96-bit long double 710 with the rounding mode forced to 53 bits. */ 711#define TARGET_96_ROUND_53_LONG_DOUBLE 0 712 713#ifndef SUBTARGET_DRIVER_SELF_SPECS 714# define SUBTARGET_DRIVER_SELF_SPECS "" 715#endif 716 717#define DRIVER_SELF_SPECS SUBTARGET_DRIVER_SELF_SPECS 718 719/* -march=native handling only makes sense with compiler running on 720 an x86 or x86_64 chip. If changing this condition, also change 721 the condition in driver-i386.c. */ 722#if defined(__i386__) || defined(__x86_64__) 723/* In driver-i386.c. */ 724extern const char *host_detect_local_cpu (int argc, const char **argv); 725#define EXTRA_SPEC_FUNCTIONS \ 726 { "local_cpu_detect", host_detect_local_cpu }, 727#define HAVE_LOCAL_CPU_DETECT 728#endif 729 730#if TARGET_64BIT_DEFAULT 731#define OPT_ARCH64 "!m32" 732#define OPT_ARCH32 "m32" 733#else 734#define OPT_ARCH64 "m64|mx32" 735#define OPT_ARCH32 "m64|mx32:;" 736#endif 737 738/* Support for configure-time defaults of some command line options. 739 The order here is important so that -march doesn't squash the 740 tune or cpu values. */ 741#define OPTION_DEFAULT_SPECS \ 742 {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ 743 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ 744 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ 745 {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ 746 {"cpu_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ 747 {"cpu_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ 748 {"arch", "%{!march=*:-march=%(VALUE)}"}, \ 749 {"arch_32", "%{" OPT_ARCH32 ":%{!march=*:-march=%(VALUE)}}"}, \ 750 {"arch_64", "%{" OPT_ARCH64 ":%{!march=*:-march=%(VALUE)}}"}, 751 752/* Specs for the compiler proper */ 753 754#ifndef CC1_CPU_SPEC 755#define CC1_CPU_SPEC_1 "" 756 757#ifndef HAVE_LOCAL_CPU_DETECT 758#define CC1_CPU_SPEC CC1_CPU_SPEC_1 759#else 760#define CC1_CPU_SPEC CC1_CPU_SPEC_1 \ 761"%{march=native:%>march=native %:local_cpu_detect(arch) \ 762 %{!mtune=*:%>mtune=native %:local_cpu_detect(tune)}} \ 763%{mtune=native:%>mtune=native %:local_cpu_detect(tune)}" 764#endif 765#endif 766 767/* Target CPU builtins. */ 768#define TARGET_CPU_CPP_BUILTINS() ix86_target_macros () 769 770/* Target Pragmas. */ 771#define REGISTER_TARGET_PRAGMAS() ix86_register_pragmas () 772 773/* Target CPU versions for D. */ 774#define TARGET_D_CPU_VERSIONS ix86_d_target_versions 775 776#ifndef CC1_SPEC 777#define CC1_SPEC "%(cc1_cpu) " 778#endif 779 780/* This macro defines names of additional specifications to put in the 781 specs that can be used in various specifications like CC1_SPEC. Its 782 definition is an initializer with a subgrouping for each command option. 783 784 Each subgrouping contains a string constant, that defines the 785 specification name, and a string constant that used by the GCC driver 786 program. 787 788 Do not define this macro if it does not need to do anything. */ 789 790#ifndef SUBTARGET_EXTRA_SPECS 791#define SUBTARGET_EXTRA_SPECS 792#endif 793 794#define EXTRA_SPECS \ 795 { "cc1_cpu", CC1_CPU_SPEC }, \ 796 SUBTARGET_EXTRA_SPECS 797 798 799/* Whether to allow x87 floating-point arithmetic on MODE (one of 800 SFmode, DFmode and XFmode) in the current excess precision 801 configuration. */ 802#define X87_ENABLE_ARITH(MODE) \ 803 (ix86_unsafe_math_optimizations \ 804 || ix86_excess_precision == EXCESS_PRECISION_FAST \ 805 || (MODE) == XFmode) 806 807/* Likewise, whether to allow direct conversions from integer mode 808 IMODE (HImode, SImode or DImode) to MODE. */ 809#define X87_ENABLE_FLOAT(MODE, IMODE) \ 810 (ix86_unsafe_math_optimizations \ 811 || ix86_excess_precision == EXCESS_PRECISION_FAST \ 812 || (MODE) == XFmode \ 813 || ((MODE) == DFmode && (IMODE) == SImode) \ 814 || (IMODE) == HImode) 815 816/* target machine storage layout */ 817 818#define SHORT_TYPE_SIZE 16 819#define INT_TYPE_SIZE 32 820#define LONG_TYPE_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD) 821#define POINTER_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD) 822#define LONG_LONG_TYPE_SIZE 64 823#define FLOAT_TYPE_SIZE 32 824#define DOUBLE_TYPE_SIZE 64 825#define LONG_DOUBLE_TYPE_SIZE \ 826 (TARGET_LONG_DOUBLE_64 ? 64 : (TARGET_LONG_DOUBLE_128 ? 128 : 80)) 827 828#define WIDEST_HARDWARE_FP_SIZE 80 829 830#if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT 831#define MAX_BITS_PER_WORD 64 832#else 833#define MAX_BITS_PER_WORD 32 834#endif 835 836/* Define this if most significant byte of a word is the lowest numbered. */ 837/* That is true on the 80386. */ 838 839#define BITS_BIG_ENDIAN 0 840 841/* Define this if most significant byte of a word is the lowest numbered. */ 842/* That is not true on the 80386. */ 843#define BYTES_BIG_ENDIAN 0 844 845/* Define this if most significant word of a multiword number is the lowest 846 numbered. */ 847/* Not true for 80386 */ 848#define WORDS_BIG_ENDIAN 0 849 850/* Width of a word, in units (bytes). */ 851#define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) 852 853#ifndef IN_LIBGCC2 854#define MIN_UNITS_PER_WORD 4 855#endif 856 857/* Allocation boundary (in *bits*) for storing arguments in argument list. */ 858#define PARM_BOUNDARY BITS_PER_WORD 859 860/* Boundary (in *bits*) on which stack pointer should be aligned. */ 861#define STACK_BOUNDARY (TARGET_64BIT_MS_ABI ? 128 : BITS_PER_WORD) 862 863/* Stack boundary of the main function guaranteed by OS. */ 864#define MAIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32) 865 866/* Minimum stack boundary. */ 867#define MIN_STACK_BOUNDARY BITS_PER_WORD 868 869/* Boundary (in *bits*) on which the stack pointer prefers to be 870 aligned; the compiler cannot rely on having this alignment. */ 871#define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary 872 873/* It should be MIN_STACK_BOUNDARY. But we set it to 128 bits for 874 both 32bit and 64bit, to support codes that need 128 bit stack 875 alignment for SSE instructions, but can't realign the stack. */ 876#define PREFERRED_STACK_BOUNDARY_DEFAULT \ 877 (TARGET_IAMCU ? MIN_STACK_BOUNDARY : 128) 878 879/* 1 if -mstackrealign should be turned on by default. It will 880 generate an alternate prologue and epilogue that realigns the 881 runtime stack if nessary. This supports mixing codes that keep a 882 4-byte aligned stack, as specified by i386 psABI, with codes that 883 need a 16-byte aligned stack, as required by SSE instructions. */ 884#define STACK_REALIGN_DEFAULT 0 885 886/* Boundary (in *bits*) on which the incoming stack is aligned. */ 887#define INCOMING_STACK_BOUNDARY ix86_incoming_stack_boundary 888 889/* According to Windows x64 software convention, the maximum stack allocatable 890 in the prologue is 4G - 8 bytes. Furthermore, there is a limited set of 891 instructions allowed to adjust the stack pointer in the epilog, forcing the 892 use of frame pointer for frames larger than 2 GB. This theorical limit 893 is reduced by 256, an over-estimated upper bound for the stack use by the 894 prologue. 895 We define only one threshold for both the prolog and the epilog. When the 896 frame size is larger than this threshold, we allocate the area to save SSE 897 regs, then save them, and then allocate the remaining. There is no SEH 898 unwind info for this later allocation. */ 899#define SEH_MAX_FRAME_SIZE ((2U << 30) - 256) 900 901/* Target OS keeps a vector-aligned (128-bit, 16-byte) stack. This is 902 mandatory for the 64-bit ABI, and may or may not be true for other 903 operating systems. */ 904#define TARGET_KEEPS_VECTOR_ALIGNED_STACK TARGET_64BIT 905 906/* Minimum allocation boundary for the code of a function. */ 907#define FUNCTION_BOUNDARY 8 908 909/* C++ stores the virtual bit in the lowest bit of function pointers. */ 910#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn 911 912/* Minimum size in bits of the largest boundary to which any 913 and all fundamental data types supported by the hardware 914 might need to be aligned. No data type wants to be aligned 915 rounder than this. 916 917 Pentium+ prefers DFmode values to be aligned to 64 bit boundary 918 and Pentium Pro XFmode values at 128 bit boundaries. 919 920 When increasing the maximum, also update 921 TARGET_ABSOLUTE_BIGGEST_ALIGNMENT. */ 922 923#define BIGGEST_ALIGNMENT \ 924 (TARGET_IAMCU ? 32 : (TARGET_AVX512F ? 512 : (TARGET_AVX ? 256 : 128))) 925 926/* Maximum stack alignment. */ 927#define MAX_STACK_ALIGNMENT MAX_OFILE_ALIGNMENT 928 929/* Alignment value for attribute ((aligned)). It is a constant since 930 it is the part of the ABI. We shouldn't change it with -mavx. */ 931#define ATTRIBUTE_ALIGNED_VALUE (TARGET_IAMCU ? 32 : 128) 932 933/* Decide whether a variable of mode MODE should be 128 bit aligned. */ 934#define ALIGN_MODE_128(MODE) \ 935 ((MODE) == XFmode || SSE_REG_MODE_P (MODE)) 936 937/* The published ABIs say that doubles should be aligned on word 938 boundaries, so lower the alignment for structure fields unless 939 -malign-double is set. */ 940 941/* ??? Blah -- this macro is used directly by libobjc. Since it 942 supports no vector modes, cut out the complexity and fall back 943 on BIGGEST_FIELD_ALIGNMENT. */ 944#ifdef IN_TARGET_LIBS 945#ifdef __x86_64__ 946#define BIGGEST_FIELD_ALIGNMENT 128 947#else 948#define BIGGEST_FIELD_ALIGNMENT 32 949#endif 950#else 951#define ADJUST_FIELD_ALIGN(FIELD, TYPE, COMPUTED) \ 952 x86_field_alignment ((TYPE), (COMPUTED)) 953#endif 954 955/* If defined, a C expression to compute the alignment for a static 956 variable. TYPE is the data type, and ALIGN is the alignment that 957 the object would ordinarily have. The value of this macro is used 958 instead of that alignment to align the object. 959 960 If this macro is not defined, then ALIGN is used. 961 962 One use of this macro is to increase alignment of medium-size 963 data to make it all fit in fewer cache lines. Another is to 964 cause character arrays to be word-aligned so that `strcpy' calls 965 that copy constants to character arrays can be done inline. */ 966 967#define DATA_ALIGNMENT(TYPE, ALIGN) \ 968 ix86_data_alignment ((TYPE), (ALIGN), true) 969 970/* Similar to DATA_ALIGNMENT, but for the cases where the ABI mandates 971 some alignment increase, instead of optimization only purposes. E.g. 972 AMD x86-64 psABI says that variables with array type larger than 15 bytes 973 must be aligned to 16 byte boundaries. 974 975 If this macro is not defined, then ALIGN is used. */ 976 977#define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \ 978 ix86_data_alignment ((TYPE), (ALIGN), false) 979 980/* If defined, a C expression to compute the alignment for a local 981 variable. TYPE is the data type, and ALIGN is the alignment that 982 the object would ordinarily have. The value of this macro is used 983 instead of that alignment to align the object. 984 985 If this macro is not defined, then ALIGN is used. 986 987 One use of this macro is to increase alignment of medium-size 988 data to make it all fit in fewer cache lines. */ 989 990#define LOCAL_ALIGNMENT(TYPE, ALIGN) \ 991 ix86_local_alignment ((TYPE), VOIDmode, (ALIGN)) 992 993/* If defined, a C expression to compute the alignment for stack slot. 994 TYPE is the data type, MODE is the widest mode available, and ALIGN 995 is the alignment that the slot would ordinarily have. The value of 996 this macro is used instead of that alignment to align the slot. 997 998 If this macro is not defined, then ALIGN is used when TYPE is NULL, 999 Otherwise, LOCAL_ALIGNMENT will be used. 1000 1001 One use of this macro is to set alignment of stack slot to the 1002 maximum alignment of all possible modes which the slot may have. */ 1003 1004#define STACK_SLOT_ALIGNMENT(TYPE, MODE, ALIGN) \ 1005 ix86_local_alignment ((TYPE), (MODE), (ALIGN)) 1006 1007/* If defined, a C expression to compute the alignment for a local 1008 variable DECL. 1009 1010 If this macro is not defined, then 1011 LOCAL_ALIGNMENT (TREE_TYPE (DECL), DECL_ALIGN (DECL)) will be used. 1012 1013 One use of this macro is to increase alignment of medium-size 1014 data to make it all fit in fewer cache lines. */ 1015 1016#define LOCAL_DECL_ALIGNMENT(DECL) \ 1017 ix86_local_alignment ((DECL), VOIDmode, DECL_ALIGN (DECL)) 1018 1019/* If defined, a C expression to compute the minimum required alignment 1020 for dynamic stack realignment purposes for EXP (a TYPE or DECL), 1021 MODE, assuming normal alignment ALIGN. 1022 1023 If this macro is not defined, then (ALIGN) will be used. */ 1024 1025#define MINIMUM_ALIGNMENT(EXP, MODE, ALIGN) \ 1026 ix86_minimum_alignment ((EXP), (MODE), (ALIGN)) 1027 1028 1029/* Set this nonzero if move instructions will actually fail to work 1030 when given unaligned data. */ 1031#define STRICT_ALIGNMENT 0 1032 1033/* If bit field type is int, don't let it cross an int, 1034 and give entire struct the alignment of an int. */ 1035/* Required on the 386 since it doesn't have bit-field insns. */ 1036#define PCC_BITFIELD_TYPE_MATTERS 1 1037 1038/* Standard register usage. */ 1039 1040/* This processor has special stack-like registers. See reg-stack.c 1041 for details. */ 1042 1043#define STACK_REGS 1044 1045#define IS_STACK_MODE(MODE) \ 1046 (X87_FLOAT_MODE_P (MODE) \ 1047 && (!(SSE_FLOAT_MODE_P (MODE) && TARGET_SSE_MATH) \ 1048 || TARGET_MIX_SSE_I387)) 1049 1050/* Number of actual hardware registers. 1051 The hardware registers are assigned numbers for the compiler 1052 from 0 to just below FIRST_PSEUDO_REGISTER. 1053 All registers that the compiler knows about must be given numbers, 1054 even those that are not normally considered general registers. 1055 1056 In the 80386 we give the 8 general purpose registers the numbers 0-7. 1057 We number the floating point registers 8-15. 1058 Note that registers 0-7 can be accessed as a short or int, 1059 while only 0-3 may be used with byte `mov' instructions. 1060 1061 Reg 16 does not correspond to any hardware register, but instead 1062 appears in the RTL as an argument pointer prior to reload, and is 1063 eliminated during reloading in favor of either the stack or frame 1064 pointer. */ 1065 1066#define FIRST_PSEUDO_REGISTER FIRST_PSEUDO_REG 1067 1068/* Number of hardware registers that go into the DWARF-2 unwind info. 1069 If not defined, equals FIRST_PSEUDO_REGISTER. */ 1070 1071#define DWARF_FRAME_REGISTERS 17 1072 1073/* 1 for registers that have pervasive standard uses 1074 and are not available for the register allocator. 1075 On the 80386, the stack pointer is such, as is the arg pointer. 1076 1077 REX registers are disabled for 32bit targets in 1078 TARGET_CONDITIONAL_REGISTER_USAGE. */ 1079 1080#define FIXED_REGISTERS \ 1081/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ 1082{ 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ 1083/*arg,flags,fpsr,frame*/ \ 1084 1, 1, 1, 1, \ 1085/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 1086 0, 0, 0, 0, 0, 0, 0, 0, \ 1087/* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \ 1088 0, 0, 0, 0, 0, 0, 0, 0, \ 1089/* r8, r9, r10, r11, r12, r13, r14, r15*/ \ 1090 0, 0, 0, 0, 0, 0, 0, 0, \ 1091/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ 1092 0, 0, 0, 0, 0, 0, 0, 0, \ 1093/*xmm16,xmm17,xmm18,xmm19,xmm20,xmm21,xmm22,xmm23*/ \ 1094 0, 0, 0, 0, 0, 0, 0, 0, \ 1095/*xmm24,xmm25,xmm26,xmm27,xmm28,xmm29,xmm30,xmm31*/ \ 1096 0, 0, 0, 0, 0, 0, 0, 0, \ 1097/* k0, k1, k2, k3, k4, k5, k6, k7*/ \ 1098 0, 0, 0, 0, 0, 0, 0, 0 } 1099 1100/* 1 for registers not available across function calls. 1101 These must include the FIXED_REGISTERS and also any 1102 registers that can be used without being saved. 1103 The latter must include the registers where values are returned 1104 and the register where structure-value addresses are passed. 1105 Aside from that, you can include as many other registers as you like. 1106 1107 Value is set to 1 if the register is call used unconditionally. 1108 Bit one is set if the register is call used on TARGET_32BIT ABI. 1109 Bit two is set if the register is call used on TARGET_64BIT ABI. 1110 Bit three is set if the register is call used on TARGET_64BIT_MS_ABI. 1111 1112 Proper values are computed in TARGET_CONDITIONAL_REGISTER_USAGE. */ 1113 1114#define CALL_USED_REGISTERS_MASK(IS_64BIT_MS_ABI) \ 1115 ((IS_64BIT_MS_ABI) ? (1 << 3) : TARGET_64BIT ? (1 << 2) : (1 << 1)) 1116 1117#define CALL_USED_REGISTERS \ 1118/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ 1119{ 1, 1, 1, 0, 4, 4, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1120/*arg,flags,fpsr,frame*/ \ 1121 1, 1, 1, 1, \ 1122/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 1123 1, 1, 1, 1, 1, 1, 6, 6, \ 1124/* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \ 1125 1, 1, 1, 1, 1, 1, 1, 1, \ 1126/* r8, r9, r10, r11, r12, r13, r14, r15*/ \ 1127 1, 1, 1, 1, 2, 2, 2, 2, \ 1128/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ 1129 6, 6, 6, 6, 6, 6, 6, 6, \ 1130/*xmm16,xmm17,xmm18,xmm19,xmm20,xmm21,xmm22,xmm23*/ \ 1131 1, 1, 1, 1, 1, 1, 1, 1, \ 1132/*xmm24,xmm25,xmm26,xmm27,xmm28,xmm29,xmm30,xmm31*/ \ 1133 1, 1, 1, 1, 1, 1, 1, 1, \ 1134 /* k0, k1, k2, k3, k4, k5, k6, k7*/ \ 1135 1, 1, 1, 1, 1, 1, 1, 1 } 1136 1137/* Order in which to allocate registers. Each register must be 1138 listed once, even those in FIXED_REGISTERS. List frame pointer 1139 late and fixed registers last. Note that, in general, we prefer 1140 registers listed in CALL_USED_REGISTERS, keeping the others 1141 available for storage of persistent values. 1142 1143 The ADJUST_REG_ALLOC_ORDER actually overwrite the order, 1144 so this is just empty initializer for array. */ 1145 1146#define REG_ALLOC_ORDER \ 1147{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \ 1148 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \ 1149 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ 1150 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \ 1151 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75 } 1152 1153/* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order 1154 to be rearranged based on a particular function. When using sse math, 1155 we want to allocate SSE before x87 registers and vice versa. */ 1156 1157#define ADJUST_REG_ALLOC_ORDER x86_order_regs_for_local_alloc () 1158 1159 1160#define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL) 1161 1162#define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \ 1163 (TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT \ 1164 && GENERAL_REGNO_P (REGNO) \ 1165 && ((MODE) == XFmode || (MODE) == XCmode)) 1166 1167#define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8) 1168 1169#define REGMODE_NATURAL_SIZE(MODE) ix86_regmode_natural_size (MODE) 1170 1171#define VALID_AVX256_REG_MODE(MODE) \ 1172 ((MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \ 1173 || (MODE) == V4DImode || (MODE) == V2TImode || (MODE) == V8SFmode \ 1174 || (MODE) == V4DFmode) 1175 1176#define VALID_AVX256_REG_OR_OI_MODE(MODE) \ 1177 (VALID_AVX256_REG_MODE (MODE) || (MODE) == OImode) 1178 1179#define VALID_AVX512F_SCALAR_MODE(MODE) \ 1180 ((MODE) == DImode || (MODE) == DFmode || (MODE) == SImode \ 1181 || (MODE) == SFmode) 1182 1183#define VALID_AVX512F_REG_MODE(MODE) \ 1184 ((MODE) == V8DImode || (MODE) == V8DFmode || (MODE) == V64QImode \ 1185 || (MODE) == V16SImode || (MODE) == V16SFmode || (MODE) == V32HImode \ 1186 || (MODE) == V4TImode) 1187 1188#define VALID_AVX512F_REG_OR_XI_MODE(MODE) \ 1189 (VALID_AVX512F_REG_MODE (MODE) || (MODE) == XImode) 1190 1191#define VALID_AVX512VL_128_REG_MODE(MODE) \ 1192 ((MODE) == V2DImode || (MODE) == V2DFmode || (MODE) == V16QImode \ 1193 || (MODE) == V4SImode || (MODE) == V4SFmode || (MODE) == V8HImode \ 1194 || (MODE) == TFmode || (MODE) == V1TImode) 1195 1196#define VALID_SSE2_REG_MODE(MODE) \ 1197 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \ 1198 || (MODE) == V2DImode || (MODE) == DFmode) 1199 1200#define VALID_SSE_REG_MODE(MODE) \ 1201 ((MODE) == V1TImode || (MODE) == TImode \ 1202 || (MODE) == V4SFmode || (MODE) == V4SImode \ 1203 || (MODE) == SFmode || (MODE) == TFmode) 1204 1205#define VALID_MMX_REG_MODE_3DNOW(MODE) \ 1206 ((MODE) == V2SFmode || (MODE) == SFmode) 1207 1208#define VALID_MMX_REG_MODE(MODE) \ 1209 ((MODE) == V1DImode || (MODE) == DImode \ 1210 || (MODE) == V2SImode || (MODE) == SImode \ 1211 || (MODE) == V4HImode || (MODE) == V8QImode) 1212 1213#define VALID_MASK_REG_MODE(MODE) ((MODE) == HImode || (MODE) == QImode) 1214 1215#define VALID_MASK_AVX512BW_MODE(MODE) ((MODE) == SImode || (MODE) == DImode) 1216 1217#define VALID_DFP_MODE_P(MODE) \ 1218 ((MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode) 1219 1220#define VALID_FP_MODE_P(MODE) \ 1221 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \ 1222 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \ 1223 1224#define VALID_INT_MODE_P(MODE) \ 1225 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \ 1226 || (MODE) == DImode \ 1227 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \ 1228 || (MODE) == CDImode \ 1229 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \ 1230 || (MODE) == TFmode || (MODE) == TCmode))) 1231 1232/* Return true for modes passed in SSE registers. */ 1233#define SSE_REG_MODE_P(MODE) \ 1234 ((MODE) == V1TImode || (MODE) == TImode || (MODE) == V16QImode \ 1235 || (MODE) == TFmode || (MODE) == V8HImode || (MODE) == V2DFmode \ 1236 || (MODE) == V2DImode || (MODE) == V4SFmode || (MODE) == V4SImode \ 1237 || (MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \ 1238 || (MODE) == V4DImode || (MODE) == V8SFmode || (MODE) == V4DFmode \ 1239 || (MODE) == V2TImode || (MODE) == V8DImode || (MODE) == V64QImode \ 1240 || (MODE) == V16SImode || (MODE) == V32HImode || (MODE) == V8DFmode \ 1241 || (MODE) == V16SFmode) 1242 1243#define X87_FLOAT_MODE_P(MODE) \ 1244 (TARGET_80387 && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode)) 1245 1246#define SSE_FLOAT_MODE_P(MODE) \ 1247 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode)) 1248 1249#define FMA4_VEC_FLOAT_MODE_P(MODE) \ 1250 (TARGET_FMA4 && ((MODE) == V4SFmode || (MODE) == V2DFmode \ 1251 || (MODE) == V8SFmode || (MODE) == V4DFmode)) 1252 1253/* It is possible to write patterns to move flags; but until someone 1254 does it, */ 1255#define AVOID_CCMODE_COPIES 1256 1257/* Specify the modes required to caller save a given hard regno. 1258 We do this on i386 to prevent flags from being saved at all. 1259 1260 Kill any attempts to combine saving of modes. */ 1261 1262#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 1263 (CC_REGNO_P (REGNO) ? VOIDmode \ 1264 : MMX_REGNO_P (REGNO) ? V8QImode \ 1265 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \ 1266 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), NULL) \ 1267 : (MODE) == HImode && !((GENERAL_REGNO_P (REGNO) \ 1268 && TARGET_PARTIAL_REG_STALL) \ 1269 || MASK_REGNO_P (REGNO)) ? SImode \ 1270 : (MODE) == QImode && !(ANY_QI_REGNO_P (REGNO) \ 1271 || MASK_REGNO_P (REGNO)) ? SImode \ 1272 : (MODE)) 1273 1274/* Specify the registers used for certain standard purposes. 1275 The values of these macros are register numbers. */ 1276 1277/* on the 386 the pc register is %eip, and is not usable as a general 1278 register. The ordinary mov instructions won't work */ 1279/* #define PC_REGNUM */ 1280 1281/* Base register for access to arguments of the function. */ 1282#define ARG_POINTER_REGNUM ARGP_REG 1283 1284/* Register to use for pushing function arguments. */ 1285#define STACK_POINTER_REGNUM SP_REG 1286 1287/* Base register for access to local variables of the function. */ 1288#define FRAME_POINTER_REGNUM FRAME_REG 1289#define HARD_FRAME_POINTER_REGNUM BP_REG 1290 1291#define FIRST_INT_REG AX_REG 1292#define LAST_INT_REG SP_REG 1293 1294#define FIRST_QI_REG AX_REG 1295#define LAST_QI_REG BX_REG 1296 1297/* First & last stack-like regs */ 1298#define FIRST_STACK_REG ST0_REG 1299#define LAST_STACK_REG ST7_REG 1300 1301#define FIRST_SSE_REG XMM0_REG 1302#define LAST_SSE_REG XMM7_REG 1303 1304#define FIRST_MMX_REG MM0_REG 1305#define LAST_MMX_REG MM7_REG 1306 1307#define FIRST_REX_INT_REG R8_REG 1308#define LAST_REX_INT_REG R15_REG 1309 1310#define FIRST_REX_SSE_REG XMM8_REG 1311#define LAST_REX_SSE_REG XMM15_REG 1312 1313#define FIRST_EXT_REX_SSE_REG XMM16_REG 1314#define LAST_EXT_REX_SSE_REG XMM31_REG 1315 1316#define FIRST_MASK_REG MASK0_REG 1317#define LAST_MASK_REG MASK7_REG 1318 1319/* Override this in other tm.h files to cope with various OS lossage 1320 requiring a frame pointer. */ 1321#ifndef SUBTARGET_FRAME_POINTER_REQUIRED 1322#define SUBTARGET_FRAME_POINTER_REQUIRED 0 1323#endif 1324 1325/* Make sure we can access arbitrary call frames. */ 1326#define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses () 1327 1328/* Register to hold the addressing base for position independent 1329 code access to data items. We don't use PIC pointer for 64bit 1330 mode. Define the regnum to dummy value to prevent gcc from 1331 pessimizing code dealing with EBX. 1332 1333 To avoid clobbering a call-saved register unnecessarily, we renumber 1334 the pic register when possible. The change is visible after the 1335 prologue has been emitted. */ 1336 1337#define REAL_PIC_OFFSET_TABLE_REGNUM (TARGET_64BIT ? R15_REG : BX_REG) 1338 1339#define PIC_OFFSET_TABLE_REGNUM \ 1340 (ix86_use_pseudo_pic_reg () \ 1341 ? (pic_offset_table_rtx \ 1342 ? INVALID_REGNUM \ 1343 : REAL_PIC_OFFSET_TABLE_REGNUM) \ 1344 : INVALID_REGNUM) 1345 1346#define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_" 1347 1348/* This is overridden by <cygwin.h>. */ 1349#define MS_AGGREGATE_RETURN 0 1350 1351#define KEEP_AGGREGATE_RETURN_POINTER 0 1352 1353/* Define the classes of registers for register constraints in the 1354 machine description. Also define ranges of constants. 1355 1356 One of the classes must always be named ALL_REGS and include all hard regs. 1357 If there is more than one class, another class must be named NO_REGS 1358 and contain no registers. 1359 1360 The name GENERAL_REGS must be the name of a class (or an alias for 1361 another name such as ALL_REGS). This is the class of registers 1362 that is allowed by "g" or "r" in a register constraint. 1363 Also, registers outside this class are allocated only when 1364 instructions express preferences for them. 1365 1366 The classes must be numbered in nondecreasing order; that is, 1367 a larger-numbered class must never be contained completely 1368 in a smaller-numbered class. This is why CLOBBERED_REGS class 1369 is listed early, even though in 64-bit mode it contains more 1370 registers than just %eax, %ecx, %edx. 1371 1372 For any two classes, it is very desirable that there be another 1373 class that represents their union. 1374 1375 The flags and fpsr registers are in no class. */ 1376 1377enum reg_class 1378{ 1379 NO_REGS, 1380 AREG, DREG, CREG, BREG, SIREG, DIREG, 1381 AD_REGS, /* %eax/%edx for DImode */ 1382 CLOBBERED_REGS, /* call-clobbered integer registers */ 1383 Q_REGS, /* %eax %ebx %ecx %edx */ 1384 NON_Q_REGS, /* %esi %edi %ebp %esp */ 1385 TLS_GOTBASE_REGS, /* %ebx %ecx %edx %esi %edi %ebp */ 1386 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */ 1387 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */ 1388 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp 1389 %r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15 */ 1390 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */ 1391 FLOAT_REGS, 1392 SSE_FIRST_REG, 1393 NO_REX_SSE_REGS, 1394 SSE_REGS, 1395 ALL_SSE_REGS, 1396 MMX_REGS, 1397 FLOAT_SSE_REGS, 1398 FLOAT_INT_REGS, 1399 INT_SSE_REGS, 1400 FLOAT_INT_SSE_REGS, 1401 MASK_REGS, 1402 ALL_MASK_REGS, 1403 ALL_REGS, 1404 LIM_REG_CLASSES 1405}; 1406 1407#define N_REG_CLASSES ((int) LIM_REG_CLASSES) 1408 1409#define INTEGER_CLASS_P(CLASS) \ 1410 reg_class_subset_p ((CLASS), GENERAL_REGS) 1411#define FLOAT_CLASS_P(CLASS) \ 1412 reg_class_subset_p ((CLASS), FLOAT_REGS) 1413#define SSE_CLASS_P(CLASS) \ 1414 reg_class_subset_p ((CLASS), ALL_SSE_REGS) 1415#define MMX_CLASS_P(CLASS) \ 1416 ((CLASS) == MMX_REGS) 1417#define MASK_CLASS_P(CLASS) \ 1418 reg_class_subset_p ((CLASS), ALL_MASK_REGS) 1419#define MAYBE_INTEGER_CLASS_P(CLASS) \ 1420 reg_classes_intersect_p ((CLASS), GENERAL_REGS) 1421#define MAYBE_FLOAT_CLASS_P(CLASS) \ 1422 reg_classes_intersect_p ((CLASS), FLOAT_REGS) 1423#define MAYBE_SSE_CLASS_P(CLASS) \ 1424 reg_classes_intersect_p ((CLASS), ALL_SSE_REGS) 1425#define MAYBE_MMX_CLASS_P(CLASS) \ 1426 reg_classes_intersect_p ((CLASS), MMX_REGS) 1427#define MAYBE_MASK_CLASS_P(CLASS) \ 1428 reg_classes_intersect_p ((CLASS), ALL_MASK_REGS) 1429 1430#define Q_CLASS_P(CLASS) \ 1431 reg_class_subset_p ((CLASS), Q_REGS) 1432 1433#define MAYBE_NON_Q_CLASS_P(CLASS) \ 1434 reg_classes_intersect_p ((CLASS), NON_Q_REGS) 1435 1436/* Give names of register classes as strings for dump file. */ 1437 1438#define REG_CLASS_NAMES \ 1439{ "NO_REGS", \ 1440 "AREG", "DREG", "CREG", "BREG", \ 1441 "SIREG", "DIREG", \ 1442 "AD_REGS", \ 1443 "CLOBBERED_REGS", \ 1444 "Q_REGS", "NON_Q_REGS", \ 1445 "TLS_GOTBASE_REGS", \ 1446 "INDEX_REGS", \ 1447 "LEGACY_REGS", \ 1448 "GENERAL_REGS", \ 1449 "FP_TOP_REG", "FP_SECOND_REG", \ 1450 "FLOAT_REGS", \ 1451 "SSE_FIRST_REG", \ 1452 "NO_REX_SSE_REGS", \ 1453 "SSE_REGS", \ 1454 "ALL_SSE_REGS", \ 1455 "MMX_REGS", \ 1456 "FLOAT_SSE_REGS", \ 1457 "FLOAT_INT_REGS", \ 1458 "INT_SSE_REGS", \ 1459 "FLOAT_INT_SSE_REGS", \ 1460 "MASK_REGS", \ 1461 "ALL_MASK_REGS", \ 1462 "ALL_REGS" } 1463 1464/* Define which registers fit in which classes. This is an initializer 1465 for a vector of HARD_REG_SET of length N_REG_CLASSES. 1466 1467 Note that CLOBBERED_REGS are calculated by 1468 TARGET_CONDITIONAL_REGISTER_USAGE. */ 1469 1470#define REG_CLASS_CONTENTS \ 1471{ { 0x0, 0x0, 0x0 }, /* NO_REGS */ \ 1472 { 0x01, 0x0, 0x0 }, /* AREG */ \ 1473 { 0x02, 0x0, 0x0 }, /* DREG */ \ 1474 { 0x04, 0x0, 0x0 }, /* CREG */ \ 1475 { 0x08, 0x0, 0x0 }, /* BREG */ \ 1476 { 0x10, 0x0, 0x0 }, /* SIREG */ \ 1477 { 0x20, 0x0, 0x0 }, /* DIREG */ \ 1478 { 0x03, 0x0, 0x0 }, /* AD_REGS */ \ 1479 { 0x07, 0x0, 0x0 }, /* CLOBBERED_REGS */ \ 1480 { 0x0f, 0x0, 0x0 }, /* Q_REGS */ \ 1481 { 0x900f0, 0x0, 0x0 }, /* NON_Q_REGS */ \ 1482 { 0x7e, 0xff0, 0x0 }, /* TLS_GOTBASE_REGS */ \ 1483 { 0x7f, 0xff0, 0x0 }, /* INDEX_REGS */ \ 1484 { 0x900ff, 0x0, 0x0 }, /* LEGACY_REGS */ \ 1485 { 0x900ff, 0xff0, 0x0 }, /* GENERAL_REGS */ \ 1486 { 0x100, 0x0, 0x0 }, /* FP_TOP_REG */ \ 1487 { 0x200, 0x0, 0x0 }, /* FP_SECOND_REG */ \ 1488 { 0xff00, 0x0, 0x0 }, /* FLOAT_REGS */ \ 1489 { 0x100000, 0x0, 0x0 }, /* SSE_FIRST_REG */ \ 1490 { 0xff00000, 0x0, 0x0 }, /* NO_REX_SSE_REGS */ \ 1491 { 0xff00000, 0xff000, 0x0 }, /* SSE_REGS */ \ 1492 { 0xff00000, 0xfffff000, 0xf }, /* ALL_SSE_REGS */ \ 1493{ 0xf0000000, 0xf, 0x0 }, /* MMX_REGS */ \ 1494 { 0xff0ff00, 0xfffff000, 0xf }, /* FLOAT_SSE_REGS */ \ 1495 { 0x9ffff, 0xff0, 0x0 }, /* FLOAT_INT_REGS */ \ 1496 { 0xff900ff, 0xfffffff0, 0xf }, /* INT_SSE_REGS */ \ 1497 { 0xff9ffff, 0xfffffff0, 0xf }, /* FLOAT_INT_SSE_REGS */ \ 1498 { 0x0, 0x0, 0xfe0 }, /* MASK_REGS */ \ 1499 { 0x0, 0x0, 0xff0 }, /* ALL_MASK_REGS */ \ 1500{ 0xffffffff, 0xffffffff, 0xfff } /* ALL_REGS */ \ 1501} 1502 1503/* The same information, inverted: 1504 Return the class number of the smallest class containing 1505 reg number REGNO. This could be a conditional expression 1506 or could index an array. */ 1507 1508#define REGNO_REG_CLASS(REGNO) (regclass_map[(REGNO)]) 1509 1510/* When this hook returns true for MODE, the compiler allows 1511 registers explicitly used in the rtl to be used as spill registers 1512 but prevents the compiler from extending the lifetime of these 1513 registers. */ 1514#define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true 1515 1516#define QI_REG_P(X) (REG_P (X) && QI_REGNO_P (REGNO (X))) 1517#define QI_REGNO_P(N) IN_RANGE ((N), FIRST_QI_REG, LAST_QI_REG) 1518 1519#define LEGACY_INT_REG_P(X) (REG_P (X) && LEGACY_INT_REGNO_P (REGNO (X))) 1520#define LEGACY_INT_REGNO_P(N) (IN_RANGE ((N), FIRST_INT_REG, LAST_INT_REG)) 1521 1522#define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X))) 1523#define REX_INT_REGNO_P(N) \ 1524 IN_RANGE ((N), FIRST_REX_INT_REG, LAST_REX_INT_REG) 1525 1526#define GENERAL_REG_P(X) (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) 1527#define GENERAL_REGNO_P(N) \ 1528 (LEGACY_INT_REGNO_P (N) || REX_INT_REGNO_P (N)) 1529 1530#define ANY_QI_REG_P(X) (REG_P (X) && ANY_QI_REGNO_P (REGNO (X))) 1531#define ANY_QI_REGNO_P(N) \ 1532 (TARGET_64BIT ? GENERAL_REGNO_P (N) : QI_REGNO_P (N)) 1533 1534#define STACK_REG_P(X) (REG_P (X) && STACK_REGNO_P (REGNO (X))) 1535#define STACK_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG) 1536 1537#define SSE_REG_P(X) (REG_P (X) && SSE_REGNO_P (REGNO (X))) 1538#define SSE_REGNO_P(N) \ 1539 (IN_RANGE ((N), FIRST_SSE_REG, LAST_SSE_REG) \ 1540 || REX_SSE_REGNO_P (N) \ 1541 || EXT_REX_SSE_REGNO_P (N)) 1542 1543#define REX_SSE_REGNO_P(N) \ 1544 IN_RANGE ((N), FIRST_REX_SSE_REG, LAST_REX_SSE_REG) 1545 1546#define EXT_REX_SSE_REG_P(X) (REG_P (X) && EXT_REX_SSE_REGNO_P (REGNO (X))) 1547 1548#define EXT_REX_SSE_REGNO_P(N) \ 1549 IN_RANGE ((N), FIRST_EXT_REX_SSE_REG, LAST_EXT_REX_SSE_REG) 1550 1551#define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X))) 1552#define ANY_FP_REGNO_P(N) (STACK_REGNO_P (N) || SSE_REGNO_P (N)) 1553 1554#define MASK_REG_P(X) (REG_P (X) && MASK_REGNO_P (REGNO (X))) 1555#define MASK_REGNO_P(N) IN_RANGE ((N), FIRST_MASK_REG, LAST_MASK_REG) 1556#define MASK_PAIR_REGNO_P(N) ((((N) - FIRST_MASK_REG) & 1) == 0) 1557 1558#define MMX_REG_P(X) (REG_P (X) && MMX_REGNO_P (REGNO (X))) 1559#define MMX_REGNO_P(N) IN_RANGE ((N), FIRST_MMX_REG, LAST_MMX_REG) 1560 1561#define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) 1562#define CC_REGNO_P(X) ((X) == FLAGS_REG) 1563 1564#define MOD4_SSE_REG_P(X) (REG_P (X) && MOD4_SSE_REGNO_P (REGNO (X))) 1565#define MOD4_SSE_REGNO_P(N) ((N) == XMM0_REG \ 1566 || (N) == XMM4_REG \ 1567 || (N) == XMM8_REG \ 1568 || (N) == XMM12_REG \ 1569 || (N) == XMM16_REG \ 1570 || (N) == XMM20_REG \ 1571 || (N) == XMM24_REG \ 1572 || (N) == XMM28_REG) 1573 1574/* First floating point reg */ 1575#define FIRST_FLOAT_REG FIRST_STACK_REG 1576#define STACK_TOP_P(X) (REG_P (X) && REGNO (X) == FIRST_FLOAT_REG) 1577 1578#define GET_SSE_REGNO(N) \ 1579 ((N) < 8 ? FIRST_SSE_REG + (N) \ 1580 : (N) < 16 ? FIRST_REX_SSE_REG + (N) - 8 \ 1581 : FIRST_EXT_REX_SSE_REG + (N) - 16) 1582 1583/* The class value for index registers, and the one for base regs. */ 1584 1585#define INDEX_REG_CLASS INDEX_REGS 1586#define BASE_REG_CLASS GENERAL_REGS 1587 1588/* Stack layout; function entry, exit and calling. */ 1589 1590/* Define this if pushing a word on the stack 1591 makes the stack pointer a smaller address. */ 1592#define STACK_GROWS_DOWNWARD 1 1593 1594/* Define this to nonzero if the nominal address of the stack frame 1595 is at the high-address end of the local variables; 1596 that is, each additional local variable allocated 1597 goes at a more negative offset in the frame. */ 1598#define FRAME_GROWS_DOWNWARD 1 1599 1600#define PUSH_ROUNDING(BYTES) ix86_push_rounding (BYTES) 1601 1602/* If defined, the maximum amount of space required for outgoing arguments 1603 will be computed and placed into the variable `crtl->outgoing_args_size'. 1604 No space will be pushed onto the stack for each call; instead, the 1605 function prologue should increase the stack frame size by this amount. 1606 1607 In 32bit mode enabling argument accumulation results in about 5% code size 1608 growth because move instructions are less compact than push. In 64bit 1609 mode the difference is less drastic but visible. 1610 1611 FIXME: Unlike earlier implementations, the size of unwind info seems to 1612 actually grow with accumulation. Is that because accumulated args 1613 unwind info became unnecesarily bloated? 1614 1615 With the 64-bit MS ABI, we can generate correct code with or without 1616 accumulated args, but because of OUTGOING_REG_PARM_STACK_SPACE the code 1617 generated without accumulated args is terrible. 1618 1619 If stack probes are required, the space used for large function 1620 arguments on the stack must also be probed, so enable 1621 -maccumulate-outgoing-args so this happens in the prologue. 1622 1623 We must use argument accumulation in interrupt function if stack 1624 may be realigned to avoid DRAP. */ 1625 1626#define ACCUMULATE_OUTGOING_ARGS \ 1627 ((TARGET_ACCUMULATE_OUTGOING_ARGS \ 1628 && optimize_function_for_speed_p (cfun)) \ 1629 || (cfun->machine->func_type != TYPE_NORMAL \ 1630 && crtl->stack_realign_needed) \ 1631 || TARGET_STACK_PROBE \ 1632 || TARGET_64BIT_MS_ABI \ 1633 || (TARGET_MACHO && crtl->profile)) 1634 1635/* If defined, a C expression whose value is nonzero when we want to use PUSH 1636 instructions to pass outgoing arguments. */ 1637 1638#define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS) 1639 1640/* We want the stack and args grow in opposite directions, even if 1641 PUSH_ARGS is 0. */ 1642#define PUSH_ARGS_REVERSED 1 1643 1644/* Offset of first parameter from the argument pointer register value. */ 1645#define FIRST_PARM_OFFSET(FNDECL) 0 1646 1647/* Define this macro if functions should assume that stack space has been 1648 allocated for arguments even when their values are passed in registers. 1649 1650 The value of this macro is the size, in bytes, of the area reserved for 1651 arguments passed in registers for the function represented by FNDECL. 1652 1653 This space can be allocated by the caller, or be a part of the 1654 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says 1655 which. */ 1656#define REG_PARM_STACK_SPACE(FNDECL) ix86_reg_parm_stack_space (FNDECL) 1657 1658#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) \ 1659 (TARGET_64BIT && ix86_function_type_abi (FNTYPE) == MS_ABI) 1660 1661/* Define how to find the value returned by a library function 1662 assuming the value has mode MODE. */ 1663 1664#define LIBCALL_VALUE(MODE) ix86_libcall_value (MODE) 1665 1666/* Define the size of the result block used for communication between 1667 untyped_call and untyped_return. The block contains a DImode value 1668 followed by the block used by fnsave and frstor. */ 1669 1670#define APPLY_RESULT_SIZE (8+108) 1671 1672/* 1 if N is a possible register number for function argument passing. */ 1673#define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N) 1674 1675/* Define a data type for recording info about an argument list 1676 during the scan of that argument list. This data type should 1677 hold all necessary information about the function itself 1678 and about the args processed so far, enough to enable macros 1679 such as FUNCTION_ARG to determine where the next arg should go. */ 1680 1681typedef struct ix86_args { 1682 int words; /* # words passed so far */ 1683 int nregs; /* # registers available for passing */ 1684 int regno; /* next available register number */ 1685 int fastcall; /* fastcall or thiscall calling convention 1686 is used */ 1687 int sse_words; /* # sse words passed so far */ 1688 int sse_nregs; /* # sse registers available for passing */ 1689 int warn_avx512f; /* True when we want to warn 1690 about AVX512F ABI. */ 1691 int warn_avx; /* True when we want to warn about AVX ABI. */ 1692 int warn_sse; /* True when we want to warn about SSE ABI. */ 1693 int warn_mmx; /* True when we want to warn about MMX ABI. */ 1694 int warn_empty; /* True when we want to warn about empty classes 1695 passing ABI change. */ 1696 int sse_regno; /* next available sse register number */ 1697 int mmx_words; /* # mmx words passed so far */ 1698 int mmx_nregs; /* # mmx registers available for passing */ 1699 int mmx_regno; /* next available mmx register number */ 1700 int maybe_vaarg; /* true for calls to possibly vardic fncts. */ 1701 int caller; /* true if it is caller. */ 1702 int float_in_sse; /* Set to 1 or 2 for 32bit targets if 1703 SFmode/DFmode arguments should be passed 1704 in SSE registers. Otherwise 0. */ 1705 int stdarg; /* Set to 1 if function is stdarg. */ 1706 enum calling_abi call_abi; /* Set to SYSV_ABI for sysv abi. Otherwise 1707 MS_ABI for ms abi. */ 1708 tree decl; /* Callee decl. */ 1709} CUMULATIVE_ARGS; 1710 1711/* Initialize a variable CUM of type CUMULATIVE_ARGS 1712 for a call to a function whose data type is FNTYPE. 1713 For a library call, FNTYPE is 0. */ 1714 1715#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1716 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL), \ 1717 (N_NAMED_ARGS) != -1) 1718 1719/* Output assembler code to FILE to increment profiler label # LABELNO 1720 for profiling a function entry. */ 1721 1722#define FUNCTION_PROFILER(FILE, LABELNO) \ 1723 x86_function_profiler ((FILE), (LABELNO)) 1724 1725#define MCOUNT_NAME "_mcount" 1726 1727#define MCOUNT_NAME_BEFORE_PROLOGUE "__fentry__" 1728 1729#define PROFILE_COUNT_REGISTER "edx" 1730 1731/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1732 the stack pointer does not matter. The value is tested only in 1733 functions that have frame pointers. 1734 No definition is equivalent to always zero. */ 1735/* Note on the 386 it might be more efficient not to define this since 1736 we have to restore it ourselves from the frame pointer, in order to 1737 use pop */ 1738 1739#define EXIT_IGNORE_STACK 1 1740 1741/* Define this macro as a C expression that is nonzero for registers 1742 used by the epilogue or the `return' pattern. */ 1743 1744#define EPILOGUE_USES(REGNO) ix86_epilogue_uses (REGNO) 1745 1746/* Output assembler code for a block containing the constant parts 1747 of a trampoline, leaving space for the variable parts. */ 1748 1749/* On the 386, the trampoline contains two instructions: 1750 mov #STATIC,ecx 1751 jmp FUNCTION 1752 The trampoline is generated entirely at runtime. The operand of JMP 1753 is the address of FUNCTION relative to the instruction following the 1754 JMP (which is 5 bytes long). */ 1755 1756/* Length in units of the trampoline for entering a nested function. */ 1757 1758#define TRAMPOLINE_SIZE (TARGET_64BIT ? 28 : 14) 1759 1760/* Definitions for register eliminations. 1761 1762 This is an array of structures. Each structure initializes one pair 1763 of eliminable registers. The "from" register number is given first, 1764 followed by "to". Eliminations of the same "from" register are listed 1765 in order of preference. 1766 1767 There are two registers that can always be eliminated on the i386. 1768 The frame pointer and the arg pointer can be replaced by either the 1769 hard frame pointer or to the stack pointer, depending upon the 1770 circumstances. The hard frame pointer is not used before reload and 1771 so it is not eligible for elimination. */ 1772 1773#define ELIMINABLE_REGS \ 1774{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1775 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 1776 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1777 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \ 1778 1779/* Define the offset between two registers, one to be eliminated, and the other 1780 its replacement, at the start of a routine. */ 1781 1782#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1783 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO))) 1784 1785/* Addressing modes, and classification of registers for them. */ 1786 1787/* Macros to check register numbers against specific register classes. */ 1788 1789/* These assume that REGNO is a hard or pseudo reg number. 1790 They give nonzero only if REGNO is a hard reg of the suitable class 1791 or a pseudo reg currently allocated to a suitable hard reg. 1792 Since they use reg_renumber, they are safe only once reg_renumber 1793 has been allocated, which happens in reginfo.c during register 1794 allocation. */ 1795 1796#define REGNO_OK_FOR_INDEX_P(REGNO) \ 1797 ((REGNO) < STACK_POINTER_REGNUM \ 1798 || REX_INT_REGNO_P (REGNO) \ 1799 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM \ 1800 || REX_INT_REGNO_P ((unsigned) reg_renumber[(REGNO)])) 1801 1802#define REGNO_OK_FOR_BASE_P(REGNO) \ 1803 (GENERAL_REGNO_P (REGNO) \ 1804 || (REGNO) == ARG_POINTER_REGNUM \ 1805 || (REGNO) == FRAME_POINTER_REGNUM \ 1806 || GENERAL_REGNO_P ((unsigned) reg_renumber[(REGNO)])) 1807 1808/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1809 and check its validity for a certain class. 1810 We have two alternate definitions for each of them. 1811 The usual definition accepts all pseudo regs; the other rejects 1812 them unless they have been allocated suitable hard regs. 1813 The symbol REG_OK_STRICT causes the latter definition to be used. 1814 1815 Most source files want to accept pseudo regs in the hope that 1816 they will get allocated to the class that the insn wants them to be in. 1817 Source files for reload pass need to be strict. 1818 After reload, it makes no difference, since pseudo regs have 1819 been eliminated by then. */ 1820 1821 1822/* Non strict versions, pseudos are ok. */ 1823#define REG_OK_FOR_INDEX_NONSTRICT_P(X) \ 1824 (REGNO (X) < STACK_POINTER_REGNUM \ 1825 || REX_INT_REGNO_P (REGNO (X)) \ 1826 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1827 1828#define REG_OK_FOR_BASE_NONSTRICT_P(X) \ 1829 (GENERAL_REGNO_P (REGNO (X)) \ 1830 || REGNO (X) == ARG_POINTER_REGNUM \ 1831 || REGNO (X) == FRAME_POINTER_REGNUM \ 1832 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1833 1834/* Strict versions, hard registers only */ 1835#define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 1836#define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 1837 1838#ifndef REG_OK_STRICT 1839#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X) 1840#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X) 1841 1842#else 1843#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X) 1844#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X) 1845#endif 1846 1847/* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression 1848 that is a valid memory address for an instruction. 1849 The MODE argument is the machine mode for the MEM expression 1850 that wants to use this address. 1851 1852 The other macros defined here are used only in TARGET_LEGITIMATE_ADDRESS_P, 1853 except for CONSTANT_ADDRESS_P which is usually machine-independent. 1854 1855 See legitimize_pic_address in i386.c for details as to what 1856 constitutes a legitimate address when -fpic is used. */ 1857 1858#define MAX_REGS_PER_ADDRESS 2 1859 1860#define CONSTANT_ADDRESS_P(X) constant_address_p (X) 1861 1862/* If defined, a C expression to determine the base term of address X. 1863 This macro is used in only one place: `find_base_term' in alias.c. 1864 1865 It is always safe for this macro to not be defined. It exists so 1866 that alias analysis can understand machine-dependent addresses. 1867 1868 The typical use of this macro is to handle addresses containing 1869 a label_ref or symbol_ref within an UNSPEC. */ 1870 1871#define FIND_BASE_TERM(X) ix86_find_base_term (X) 1872 1873/* Nonzero if the constant value X is a legitimate general operand 1874 when generating PIC code. It is given that flag_pic is on and 1875 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 1876 1877#define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) 1878 1879#define SYMBOLIC_CONST(X) \ 1880 (GET_CODE (X) == SYMBOL_REF \ 1881 || GET_CODE (X) == LABEL_REF \ 1882 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) 1883 1884/* Max number of args passed in registers. If this is more than 3, we will 1885 have problems with ebx (register #4), since it is a caller save register and 1886 is also used as the pic register in ELF. So for now, don't allow more than 1887 3 registers to be passed in registers. */ 1888 1889/* Abi specific values for REGPARM_MAX and SSE_REGPARM_MAX */ 1890#define X86_64_REGPARM_MAX 6 1891#define X86_64_MS_REGPARM_MAX 4 1892 1893#define X86_32_REGPARM_MAX 3 1894 1895#define REGPARM_MAX \ 1896 (TARGET_64BIT \ 1897 ? (TARGET_64BIT_MS_ABI \ 1898 ? X86_64_MS_REGPARM_MAX \ 1899 : X86_64_REGPARM_MAX) \ 1900 : X86_32_REGPARM_MAX) 1901 1902#define X86_64_SSE_REGPARM_MAX 8 1903#define X86_64_MS_SSE_REGPARM_MAX 4 1904 1905#define X86_32_SSE_REGPARM_MAX (TARGET_SSE ? (TARGET_MACHO ? 4 : 3) : 0) 1906 1907#define SSE_REGPARM_MAX \ 1908 (TARGET_64BIT \ 1909 ? (TARGET_64BIT_MS_ABI \ 1910 ? X86_64_MS_SSE_REGPARM_MAX \ 1911 : X86_64_SSE_REGPARM_MAX) \ 1912 : X86_32_SSE_REGPARM_MAX) 1913 1914#define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0)) 1915 1916/* Specify the machine mode that this machine uses 1917 for the index in the tablejump instruction. */ 1918#define CASE_VECTOR_MODE \ 1919 (!TARGET_LP64 || (flag_pic && ix86_cmodel != CM_LARGE_PIC) ? SImode : DImode) 1920 1921/* Define this as 1 if `char' should by default be signed; else as 0. */ 1922#define DEFAULT_SIGNED_CHAR 1 1923 1924/* Max number of bytes we can move from memory to memory 1925 in one reasonably fast instruction. */ 1926#define MOVE_MAX 16 1927 1928/* MOVE_MAX_PIECES is the number of bytes at a time which we can 1929 move efficiently, as opposed to MOVE_MAX which is the maximum 1930 number of bytes we can move with a single instruction. 1931 1932 ??? We should use TImode in 32-bit mode and use OImode or XImode 1933 if they are available. But since by_pieces_ninsns determines the 1934 widest mode with MAX_FIXED_MODE_SIZE, we can only use TImode in 1935 64-bit mode. */ 1936#define MOVE_MAX_PIECES \ 1937 ((TARGET_64BIT \ 1938 && TARGET_SSE2 \ 1939 && TARGET_SSE_UNALIGNED_LOAD_OPTIMAL \ 1940 && TARGET_SSE_UNALIGNED_STORE_OPTIMAL) \ 1941 ? GET_MODE_SIZE (TImode) : UNITS_PER_WORD) 1942 1943/* If a memory-to-memory move would take MOVE_RATIO or more simple 1944 move-instruction pairs, we will do a cpymem or libcall instead. 1945 Increasing the value will always make code faster, but eventually 1946 incurs high cost in increased code size. 1947 1948 If you don't define this, a reasonable default is used. */ 1949 1950#define MOVE_RATIO(speed) ((speed) ? ix86_cost->move_ratio : 3) 1951 1952/* If a clear memory operation would take CLEAR_RATIO or more simple 1953 move-instruction sequences, we will do a clrmem or libcall instead. */ 1954 1955#define CLEAR_RATIO(speed) ((speed) ? ix86_cost->clear_ratio : 2) 1956 1957/* Define if shifts truncate the shift count which implies one can 1958 omit a sign-extension or zero-extension of a shift count. 1959 1960 On i386, shifts do truncate the count. But bit test instructions 1961 take the modulo of the bit offset operand. */ 1962 1963/* #define SHIFT_COUNT_TRUNCATED */ 1964 1965/* A macro to update M and UNSIGNEDP when an object whose type is 1966 TYPE and which has the specified mode and signedness is to be 1967 stored in a register. This macro is only called when TYPE is a 1968 scalar type. 1969 1970 On i386 it is sometimes useful to promote HImode and QImode 1971 quantities to SImode. The choice depends on target type. */ 1972 1973#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 1974do { \ 1975 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \ 1976 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \ 1977 (MODE) = SImode; \ 1978} while (0) 1979 1980/* Specify the machine mode that pointers have. 1981 After generation of rtl, the compiler makes no further distinction 1982 between pointers and any other objects of this machine mode. */ 1983#define Pmode (ix86_pmode == PMODE_DI ? DImode : SImode) 1984 1985/* Supply a definition of STACK_SAVEAREA_MODE for emit_stack_save. 1986 NONLOCAL needs space to save both shadow stack and stack pointers. 1987 1988 FIXME: We only need to save and restore stack pointer in ptr_mode. 1989 But expand_builtin_setjmp_setup and expand_builtin_longjmp use Pmode 1990 to save and restore stack pointer. See 1991 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84150 1992 */ 1993#define STACK_SAVEAREA_MODE(LEVEL) \ 1994 ((LEVEL) == SAVE_NONLOCAL ? (TARGET_64BIT ? TImode : DImode) : Pmode) 1995 1996/* Specify the machine_mode of the size increment 1997 operand of an 'allocate_stack' named pattern. */ 1998#define STACK_SIZE_MODE Pmode 1999 2000/* A C expression whose value is zero if pointers that need to be extended 2001 from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and 2002 greater then zero if they are zero-extended and less then zero if the 2003 ptr_extend instruction should be used. */ 2004 2005#define POINTERS_EXTEND_UNSIGNED 1 2006 2007/* A function address in a call instruction 2008 is a byte address (for indexing purposes) 2009 so give the MEM rtx a byte's mode. */ 2010#define FUNCTION_MODE QImode 2011 2012 2013/* A C expression for the cost of a branch instruction. A value of 1 2014 is the default; other values are interpreted relative to that. */ 2015 2016#define BRANCH_COST(speed_p, predictable_p) \ 2017 (!(speed_p) ? 2 : (predictable_p) ? 0 : ix86_branch_cost) 2018 2019/* An integer expression for the size in bits of the largest integer machine 2020 mode that should actually be used. We allow pairs of registers. */ 2021#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode) 2022 2023/* Define this macro as a C expression which is nonzero if accessing 2024 less than a word of memory (i.e. a `char' or a `short') is no 2025 faster than accessing a word of memory, i.e., if such access 2026 require more than one instruction or if there is no difference in 2027 cost between byte and (aligned) word loads. 2028 2029 When this macro is not defined, the compiler will access a field by 2030 finding the smallest containing object; when it is defined, a 2031 fullword load will be used if alignment permits. Unless bytes 2032 accesses are faster than word accesses, using word accesses is 2033 preferable since it may eliminate subsequent memory access if 2034 subsequent accesses occur to other fields in the same word of the 2035 structure, but to different bytes. */ 2036 2037#define SLOW_BYTE_ACCESS 0 2038 2039/* Nonzero if access to memory by shorts is slow and undesirable. */ 2040#define SLOW_SHORT_ACCESS 0 2041 2042/* Define this macro if it is as good or better to call a constant 2043 function address than to call an address kept in a register. 2044 2045 Desirable on the 386 because a CALL with a constant address is 2046 faster than one with a register address. */ 2047 2048#define NO_FUNCTION_CSE 1 2049 2050/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 2051 return the mode to be used for the comparison. 2052 2053 For floating-point equality comparisons, CCFPEQmode should be used. 2054 VOIDmode should be used in all other cases. 2055 2056 For integer comparisons against zero, reduce to CCNOmode or CCZmode if 2057 possible, to allow for more combinations. */ 2058 2059#define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y)) 2060 2061/* Return nonzero if MODE implies a floating point inequality can be 2062 reversed. */ 2063 2064#define REVERSIBLE_CC_MODE(MODE) 1 2065 2066/* A C expression whose value is reversed condition code of the CODE for 2067 comparison done in CC_MODE mode. */ 2068#define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE)) 2069 2070 2071/* Control the assembler format that we output, to the extent 2072 this does not vary between assemblers. */ 2073 2074/* How to refer to registers in assembler output. 2075 This sequence is indexed by compiler's hard-register-number (see above). */ 2076 2077/* In order to refer to the first 8 regs as 32-bit regs, prefix an "e". 2078 For non floating point regs, the following are the HImode names. 2079 2080 For float regs, the stack top is sometimes referred to as "%st(0)" 2081 instead of just "%st". TARGET_PRINT_OPERAND handles this with the 2082 "y" code. */ 2083 2084#define HI_REGISTER_NAMES \ 2085{"ax","dx","cx","bx","si","di","bp","sp", \ 2086 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \ 2087 "argp", "flags", "fpsr", "frame", \ 2088 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \ 2089 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", \ 2090 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ 2091 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", \ 2092 "xmm16", "xmm17", "xmm18", "xmm19", \ 2093 "xmm20", "xmm21", "xmm22", "xmm23", \ 2094 "xmm24", "xmm25", "xmm26", "xmm27", \ 2095 "xmm28", "xmm29", "xmm30", "xmm31", \ 2096 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7" } 2097 2098#define REGISTER_NAMES HI_REGISTER_NAMES 2099 2100#define QI_REGISTER_NAMES \ 2101{"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl"} 2102 2103#define QI_HIGH_REGISTER_NAMES \ 2104{"ah", "dh", "ch", "bh"} 2105 2106/* Table of additional register names to use in user input. */ 2107 2108#define ADDITIONAL_REGISTER_NAMES \ 2109{ \ 2110 { "eax", AX_REG }, { "edx", DX_REG }, { "ecx", CX_REG }, { "ebx", BX_REG }, \ 2111 { "esi", SI_REG }, { "edi", DI_REG }, { "ebp", BP_REG }, { "esp", SP_REG }, \ 2112 { "rax", AX_REG }, { "rdx", DX_REG }, { "rcx", CX_REG }, { "rbx", BX_REG }, \ 2113 { "rsi", SI_REG }, { "rdi", DI_REG }, { "rbp", BP_REG }, { "rsp", SP_REG }, \ 2114 { "al", AX_REG }, { "dl", DX_REG }, { "cl", CX_REG }, { "bl", BX_REG }, \ 2115 { "sil", SI_REG }, { "dil", DI_REG }, { "bpl", BP_REG }, { "spl", SP_REG }, \ 2116 { "ah", AX_REG }, { "dh", DX_REG }, { "ch", CX_REG }, { "bh", BX_REG }, \ 2117 { "ymm0", XMM0_REG }, { "ymm1", XMM1_REG }, { "ymm2", XMM2_REG }, { "ymm3", XMM3_REG }, \ 2118 { "ymm4", XMM4_REG }, { "ymm5", XMM5_REG }, { "ymm6", XMM6_REG }, { "ymm7", XMM7_REG }, \ 2119 { "ymm8", XMM8_REG }, { "ymm9", XMM9_REG }, { "ymm10", XMM10_REG }, { "ymm11", XMM11_REG }, \ 2120 { "ymm12", XMM12_REG }, { "ymm13", XMM13_REG }, { "ymm14", XMM14_REG }, { "ymm15", XMM15_REG }, \ 2121 { "ymm16", XMM16_REG }, { "ymm17", XMM17_REG }, { "ymm18", XMM18_REG }, { "ymm19", XMM19_REG }, \ 2122 { "ymm20", XMM20_REG }, { "ymm21", XMM21_REG }, { "ymm22", XMM22_REG }, { "ymm23", XMM23_REG }, \ 2123 { "ymm24", XMM24_REG }, { "ymm25", XMM25_REG }, { "ymm26", XMM26_REG }, { "ymm27", XMM27_REG }, \ 2124 { "ymm28", XMM28_REG }, { "ymm29", XMM29_REG }, { "ymm30", XMM30_REG }, { "ymm31", XMM31_REG }, \ 2125 { "zmm0", XMM0_REG }, { "zmm1", XMM1_REG }, { "zmm2", XMM2_REG }, { "zmm3", XMM3_REG }, \ 2126 { "zmm4", XMM4_REG }, { "zmm5", XMM5_REG }, { "zmm6", XMM6_REG }, { "zmm7", XMM7_REG }, \ 2127 { "zmm8", XMM8_REG }, { "zmm9", XMM9_REG }, { "zmm10", XMM10_REG }, { "zmm11", XMM11_REG }, \ 2128 { "zmm12", XMM12_REG }, { "zmm13", XMM13_REG }, { "zmm14", XMM14_REG }, { "zmm15", XMM15_REG }, \ 2129 { "zmm16", XMM16_REG }, { "zmm17", XMM17_REG }, { "zmm18", XMM18_REG }, { "zmm19", XMM19_REG }, \ 2130 { "zmm20", XMM20_REG }, { "zmm21", XMM21_REG }, { "zmm22", XMM22_REG }, { "zmm23", XMM23_REG }, \ 2131 { "zmm24", XMM24_REG }, { "zmm25", XMM25_REG }, { "zmm26", XMM26_REG }, { "zmm27", XMM27_REG }, \ 2132 { "zmm28", XMM28_REG }, { "zmm29", XMM29_REG }, { "zmm30", XMM30_REG }, { "zmm31", XMM31_REG } \ 2133} 2134 2135/* How to renumber registers for dbx and gdb. */ 2136 2137#define DBX_REGISTER_NUMBER(N) \ 2138 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)]) 2139 2140extern int const dbx_register_map[FIRST_PSEUDO_REGISTER]; 2141extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER]; 2142extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER]; 2143 2144/* Before the prologue, RA is at 0(%esp). */ 2145#define INCOMING_RETURN_ADDR_RTX \ 2146 gen_rtx_MEM (Pmode, stack_pointer_rtx) 2147 2148/* After the prologue, RA is at -4(AP) in the current frame. */ 2149#define RETURN_ADDR_RTX(COUNT, FRAME) \ 2150 ((COUNT) == 0 \ 2151 ? gen_rtx_MEM (Pmode, plus_constant (Pmode, arg_pointer_rtx, \ 2152 -UNITS_PER_WORD)) \ 2153 : gen_rtx_MEM (Pmode, plus_constant (Pmode, (FRAME), UNITS_PER_WORD))) 2154 2155/* PC is dbx register 8; let's use that column for RA. */ 2156#define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8) 2157 2158/* Before the prologue, there are return address and error code for 2159 exception handler on the top of the frame. */ 2160#define INCOMING_FRAME_SP_OFFSET \ 2161 (cfun->machine->func_type == TYPE_EXCEPTION \ 2162 ? 2 * UNITS_PER_WORD : UNITS_PER_WORD) 2163 2164/* The value of INCOMING_FRAME_SP_OFFSET the assembler assumes in 2165 .cfi_startproc. */ 2166#define DEFAULT_INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD 2167 2168/* Describe how we implement __builtin_eh_return. */ 2169#define EH_RETURN_DATA_REGNO(N) ((N) <= DX_REG ? (N) : INVALID_REGNUM) 2170#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, CX_REG) 2171 2172 2173/* Select a format to encode pointers in exception handling data. CODE 2174 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is 2175 true if the symbol may be affected by dynamic relocations. 2176 2177 ??? All x86 object file formats are capable of representing this. 2178 After all, the relocation needed is the same as for the call insn. 2179 Whether or not a particular assembler allows us to enter such, I 2180 guess we'll have to see. */ 2181#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 2182 asm_preferred_eh_data_format ((CODE), (GLOBAL)) 2183 2184/* These are a couple of extensions to the formats accepted 2185 by asm_fprintf: 2186 %z prints out opcode suffix for word-mode instruction 2187 %r prints out word-mode name for reg_names[arg] */ 2188#define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \ 2189 case 'z': \ 2190 fputc (TARGET_64BIT ? 'q' : 'l', (FILE)); \ 2191 break; \ 2192 \ 2193 case 'r': \ 2194 { \ 2195 unsigned int regno = va_arg ((ARGS), int); \ 2196 if (LEGACY_INT_REGNO_P (regno)) \ 2197 fputc (TARGET_64BIT ? 'r' : 'e', (FILE)); \ 2198 fputs (reg_names[regno], (FILE)); \ 2199 break; \ 2200 } 2201 2202/* This is how to output an insn to push a register on the stack. */ 2203 2204#define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \ 2205 asm_fprintf ((FILE), "\tpush%z\t%%%r\n", (REGNO)) 2206 2207/* This is how to output an insn to pop a register from the stack. */ 2208 2209#define ASM_OUTPUT_REG_POP(FILE, REGNO) \ 2210 asm_fprintf ((FILE), "\tpop%z\t%%%r\n", (REGNO)) 2211 2212/* This is how to output an element of a case-vector that is absolute. */ 2213 2214#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 2215 ix86_output_addr_vec_elt ((FILE), (VALUE)) 2216 2217/* This is how to output an element of a case-vector that is relative. */ 2218 2219#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 2220 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL)) 2221 2222/* When we see %v, we will print the 'v' prefix if TARGET_AVX is true. */ 2223 2224#define ASM_OUTPUT_AVX_PREFIX(STREAM, PTR) \ 2225{ \ 2226 if ((PTR)[0] == '%' && (PTR)[1] == 'v') \ 2227 (PTR) += TARGET_AVX ? 1 : 2; \ 2228} 2229 2230/* A C statement or statements which output an assembler instruction 2231 opcode to the stdio stream STREAM. The macro-operand PTR is a 2232 variable of type `char *' which points to the opcode name in 2233 its "internal" form--the form that is written in the machine 2234 description. */ 2235 2236#define ASM_OUTPUT_OPCODE(STREAM, PTR) \ 2237 ASM_OUTPUT_AVX_PREFIX ((STREAM), (PTR)) 2238 2239/* A C statement to output to the stdio stream FILE an assembler 2240 command to pad the location counter to a multiple of 1<<LOG 2241 bytes if it is within MAX_SKIP bytes. */ 2242 2243#ifdef HAVE_GAS_MAX_SKIP_P2ALIGN 2244#undef ASM_OUTPUT_MAX_SKIP_PAD 2245#define ASM_OUTPUT_MAX_SKIP_PAD(FILE, LOG, MAX_SKIP) \ 2246 if ((LOG) != 0) \ 2247 { \ 2248 if ((MAX_SKIP) == 0 || (MAX_SKIP) >= (1 << (LOG)) - 1) \ 2249 fprintf ((FILE), "\t.p2align %d\n", (LOG)); \ 2250 else \ 2251 fprintf ((FILE), "\t.p2align %d,,%d\n", (LOG), (MAX_SKIP)); \ 2252 } 2253#endif 2254 2255/* Write the extra assembler code needed to declare a function 2256 properly. */ 2257 2258#undef ASM_OUTPUT_FUNCTION_LABEL 2259#define ASM_OUTPUT_FUNCTION_LABEL(FILE, NAME, DECL) \ 2260 ix86_asm_output_function_label ((FILE), (NAME), (DECL)) 2261 2262/* A C statement (sans semicolon) to output a reference to SYMBOL_REF SYM. 2263 If not defined, assemble_name will be used to output the name of the 2264 symbol. This macro may be used to modify the way a symbol is referenced 2265 depending on information encoded by TARGET_ENCODE_SECTION_INFO. */ 2266 2267#ifndef ASM_OUTPUT_SYMBOL_REF 2268#define ASM_OUTPUT_SYMBOL_REF(FILE, SYM) \ 2269 do { \ 2270 const char *name \ 2271 = assemble_name_resolve (XSTR (x, 0)); \ 2272 /* In -masm=att wrap identifiers that start with $ \ 2273 into parens. */ \ 2274 if (ASSEMBLER_DIALECT == ASM_ATT \ 2275 && name[0] == '$' \ 2276 && user_label_prefix[0] == '\0') \ 2277 { \ 2278 fputc ('(', (FILE)); \ 2279 assemble_name_raw ((FILE), name); \ 2280 fputc (')', (FILE)); \ 2281 } \ 2282 else \ 2283 assemble_name_raw ((FILE), name); \ 2284 } while (0) 2285#endif 2286 2287/* Under some conditions we need jump tables in the text section, 2288 because the assembler cannot handle label differences between 2289 sections. */ 2290 2291#define JUMP_TABLES_IN_TEXT_SECTION \ 2292 (flag_pic && !(TARGET_64BIT || HAVE_AS_GOTOFF_IN_DATA)) 2293 2294/* Switch to init or fini section via SECTION_OP, emit a call to FUNC, 2295 and switch back. For x86 we do this only to save a few bytes that 2296 would otherwise be unused in the text section. */ 2297#define CRT_MKSTR2(VAL) #VAL 2298#define CRT_MKSTR(x) CRT_MKSTR2(x) 2299 2300#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 2301 asm (SECTION_OP "\n\t" \ 2302 "call " CRT_MKSTR(__USER_LABEL_PREFIX__) #FUNC "\n" \ 2303 TEXT_SECTION_ASM_OP); 2304 2305/* Default threshold for putting data in large sections 2306 with x86-64 medium memory model */ 2307#define DEFAULT_LARGE_SECTION_THRESHOLD 65536 2308 2309/* Which processor to tune code generation for. These must be in sync 2310 with processor_target_table in i386.c. */ 2311 2312enum processor_type 2313{ 2314 PROCESSOR_GENERIC = 0, 2315 PROCESSOR_I386, /* 80386 */ 2316 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */ 2317 PROCESSOR_PENTIUM, 2318 PROCESSOR_LAKEMONT, 2319 PROCESSOR_PENTIUMPRO, 2320 PROCESSOR_PENTIUM4, 2321 PROCESSOR_NOCONA, 2322 PROCESSOR_CORE2, 2323 PROCESSOR_NEHALEM, 2324 PROCESSOR_SANDYBRIDGE, 2325 PROCESSOR_HASWELL, 2326 PROCESSOR_BONNELL, 2327 PROCESSOR_SILVERMONT, 2328 PROCESSOR_GOLDMONT, 2329 PROCESSOR_GOLDMONT_PLUS, 2330 PROCESSOR_TREMONT, 2331 PROCESSOR_KNL, 2332 PROCESSOR_KNM, 2333 PROCESSOR_SKYLAKE, 2334 PROCESSOR_SKYLAKE_AVX512, 2335 PROCESSOR_CANNONLAKE, 2336 PROCESSOR_ICELAKE_CLIENT, 2337 PROCESSOR_ICELAKE_SERVER, 2338 PROCESSOR_CASCADELAKE, 2339 PROCESSOR_TIGERLAKE, 2340 PROCESSOR_COOPERLAKE, 2341 PROCESSOR_INTEL, 2342 PROCESSOR_GEODE, 2343 PROCESSOR_K6, 2344 PROCESSOR_ATHLON, 2345 PROCESSOR_K8, 2346 PROCESSOR_AMDFAM10, 2347 PROCESSOR_BDVER1, 2348 PROCESSOR_BDVER2, 2349 PROCESSOR_BDVER3, 2350 PROCESSOR_BDVER4, 2351 PROCESSOR_BTVER1, 2352 PROCESSOR_BTVER2, 2353 PROCESSOR_ZNVER1, 2354 PROCESSOR_ZNVER2, 2355 PROCESSOR_ZNVER3, 2356 PROCESSOR_max 2357}; 2358 2359#if !defined(IN_LIBGCC2) && !defined(IN_TARGET_LIBS) && !defined(IN_RTS) 2360extern const char *const processor_names[]; 2361 2362#include "wide-int-bitmask.h" 2363 2364const wide_int_bitmask PTA_3DNOW (HOST_WIDE_INT_1U << 0); 2365const wide_int_bitmask PTA_3DNOW_A (HOST_WIDE_INT_1U << 1); 2366const wide_int_bitmask PTA_64BIT (HOST_WIDE_INT_1U << 2); 2367const wide_int_bitmask PTA_ABM (HOST_WIDE_INT_1U << 3); 2368const wide_int_bitmask PTA_AES (HOST_WIDE_INT_1U << 4); 2369const wide_int_bitmask PTA_AVX (HOST_WIDE_INT_1U << 5); 2370const wide_int_bitmask PTA_BMI (HOST_WIDE_INT_1U << 6); 2371const wide_int_bitmask PTA_CX16 (HOST_WIDE_INT_1U << 7); 2372const wide_int_bitmask PTA_F16C (HOST_WIDE_INT_1U << 8); 2373const wide_int_bitmask PTA_FMA (HOST_WIDE_INT_1U << 9); 2374const wide_int_bitmask PTA_FMA4 (HOST_WIDE_INT_1U << 10); 2375const wide_int_bitmask PTA_FSGSBASE (HOST_WIDE_INT_1U << 11); 2376const wide_int_bitmask PTA_LWP (HOST_WIDE_INT_1U << 12); 2377const wide_int_bitmask PTA_LZCNT (HOST_WIDE_INT_1U << 13); 2378const wide_int_bitmask PTA_MMX (HOST_WIDE_INT_1U << 14); 2379const wide_int_bitmask PTA_MOVBE (HOST_WIDE_INT_1U << 15); 2380const wide_int_bitmask PTA_NO_SAHF (HOST_WIDE_INT_1U << 16); 2381const wide_int_bitmask PTA_PCLMUL (HOST_WIDE_INT_1U << 17); 2382const wide_int_bitmask PTA_POPCNT (HOST_WIDE_INT_1U << 18); 2383const wide_int_bitmask PTA_PREFETCH_SSE (HOST_WIDE_INT_1U << 19); 2384const wide_int_bitmask PTA_RDRND (HOST_WIDE_INT_1U << 20); 2385const wide_int_bitmask PTA_SSE (HOST_WIDE_INT_1U << 21); 2386const wide_int_bitmask PTA_SSE2 (HOST_WIDE_INT_1U << 22); 2387const wide_int_bitmask PTA_SSE3 (HOST_WIDE_INT_1U << 23); 2388const wide_int_bitmask PTA_SSE4_1 (HOST_WIDE_INT_1U << 24); 2389const wide_int_bitmask PTA_SSE4_2 (HOST_WIDE_INT_1U << 25); 2390const wide_int_bitmask PTA_SSE4A (HOST_WIDE_INT_1U << 26); 2391const wide_int_bitmask PTA_SSSE3 (HOST_WIDE_INT_1U << 27); 2392const wide_int_bitmask PTA_TBM (HOST_WIDE_INT_1U << 28); 2393const wide_int_bitmask PTA_XOP (HOST_WIDE_INT_1U << 29); 2394const wide_int_bitmask PTA_AVX2 (HOST_WIDE_INT_1U << 30); 2395const wide_int_bitmask PTA_BMI2 (HOST_WIDE_INT_1U << 31); 2396const wide_int_bitmask PTA_RTM (HOST_WIDE_INT_1U << 32); 2397const wide_int_bitmask PTA_HLE (HOST_WIDE_INT_1U << 33); 2398const wide_int_bitmask PTA_PRFCHW (HOST_WIDE_INT_1U << 34); 2399const wide_int_bitmask PTA_RDSEED (HOST_WIDE_INT_1U << 35); 2400const wide_int_bitmask PTA_ADX (HOST_WIDE_INT_1U << 36); 2401const wide_int_bitmask PTA_FXSR (HOST_WIDE_INT_1U << 37); 2402const wide_int_bitmask PTA_XSAVE (HOST_WIDE_INT_1U << 38); 2403const wide_int_bitmask PTA_XSAVEOPT (HOST_WIDE_INT_1U << 39); 2404const wide_int_bitmask PTA_AVX512F (HOST_WIDE_INT_1U << 40); 2405const wide_int_bitmask PTA_AVX512ER (HOST_WIDE_INT_1U << 41); 2406const wide_int_bitmask PTA_AVX512PF (HOST_WIDE_INT_1U << 42); 2407const wide_int_bitmask PTA_AVX512CD (HOST_WIDE_INT_1U << 43); 2408/* Hole after PTA_MPX was removed. */ 2409const wide_int_bitmask PTA_SHA (HOST_WIDE_INT_1U << 45); 2410const wide_int_bitmask PTA_PREFETCHWT1 (HOST_WIDE_INT_1U << 46); 2411const wide_int_bitmask PTA_CLFLUSHOPT (HOST_WIDE_INT_1U << 47); 2412const wide_int_bitmask PTA_XSAVEC (HOST_WIDE_INT_1U << 48); 2413const wide_int_bitmask PTA_XSAVES (HOST_WIDE_INT_1U << 49); 2414const wide_int_bitmask PTA_AVX512DQ (HOST_WIDE_INT_1U << 50); 2415const wide_int_bitmask PTA_AVX512BW (HOST_WIDE_INT_1U << 51); 2416const wide_int_bitmask PTA_AVX512VL (HOST_WIDE_INT_1U << 52); 2417const wide_int_bitmask PTA_AVX512IFMA (HOST_WIDE_INT_1U << 53); 2418const wide_int_bitmask PTA_AVX512VBMI (HOST_WIDE_INT_1U << 54); 2419const wide_int_bitmask PTA_CLWB (HOST_WIDE_INT_1U << 55); 2420const wide_int_bitmask PTA_MWAITX (HOST_WIDE_INT_1U << 56); 2421const wide_int_bitmask PTA_CLZERO (HOST_WIDE_INT_1U << 57); 2422const wide_int_bitmask PTA_NO_80387 (HOST_WIDE_INT_1U << 58); 2423const wide_int_bitmask PTA_PKU (HOST_WIDE_INT_1U << 59); 2424const wide_int_bitmask PTA_AVX5124VNNIW (HOST_WIDE_INT_1U << 60); 2425const wide_int_bitmask PTA_AVX5124FMAPS (HOST_WIDE_INT_1U << 61); 2426const wide_int_bitmask PTA_AVX512VPOPCNTDQ (HOST_WIDE_INT_1U << 62); 2427const wide_int_bitmask PTA_SGX (HOST_WIDE_INT_1U << 63); 2428const wide_int_bitmask PTA_AVX512VNNI (0, HOST_WIDE_INT_1U); 2429const wide_int_bitmask PTA_GFNI (0, HOST_WIDE_INT_1U << 1); 2430const wide_int_bitmask PTA_VAES (0, HOST_WIDE_INT_1U << 2); 2431const wide_int_bitmask PTA_AVX512VBMI2 (0, HOST_WIDE_INT_1U << 3); 2432const wide_int_bitmask PTA_VPCLMULQDQ (0, HOST_WIDE_INT_1U << 4); 2433const wide_int_bitmask PTA_AVX512BITALG (0, HOST_WIDE_INT_1U << 5); 2434const wide_int_bitmask PTA_RDPID (0, HOST_WIDE_INT_1U << 6); 2435const wide_int_bitmask PTA_PCONFIG (0, HOST_WIDE_INT_1U << 7); 2436const wide_int_bitmask PTA_WBNOINVD (0, HOST_WIDE_INT_1U << 8); 2437const wide_int_bitmask PTA_AVX512VP2INTERSECT (0, HOST_WIDE_INT_1U << 9); 2438const wide_int_bitmask PTA_PTWRITE (0, HOST_WIDE_INT_1U << 10); 2439const wide_int_bitmask PTA_AVX512BF16 (0, HOST_WIDE_INT_1U << 11); 2440const wide_int_bitmask PTA_WAITPKG (0, HOST_WIDE_INT_1U << 12); 2441const wide_int_bitmask PTA_MOVDIRI (0, HOST_WIDE_INT_1U << 13); 2442const wide_int_bitmask PTA_MOVDIR64B (0, HOST_WIDE_INT_1U << 14); 2443const wide_int_bitmask PTA_CLDEMOTE (0, HOST_WIDE_INT_1U << 16); 2444 2445const wide_int_bitmask PTA_CORE2 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 2446 | PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR; 2447const wide_int_bitmask PTA_NEHALEM = PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2 2448 | PTA_POPCNT; 2449const wide_int_bitmask PTA_WESTMERE = PTA_NEHALEM | PTA_PCLMUL; 2450const wide_int_bitmask PTA_SANDYBRIDGE = PTA_WESTMERE | PTA_AVX | PTA_XSAVE 2451 | PTA_XSAVEOPT; 2452const wide_int_bitmask PTA_IVYBRIDGE = PTA_SANDYBRIDGE | PTA_FSGSBASE 2453 | PTA_RDRND | PTA_F16C; 2454const wide_int_bitmask PTA_HASWELL = PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI 2455 | PTA_BMI2 | PTA_LZCNT | PTA_FMA | PTA_MOVBE | PTA_HLE; 2456const wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX | PTA_RDSEED 2457 | PTA_PRFCHW; 2458const wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_AES | PTA_CLFLUSHOPT 2459 | PTA_XSAVEC | PTA_XSAVES | PTA_SGX; 2460const wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F 2461 | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU 2462 | PTA_CLWB; 2463const wide_int_bitmask PTA_CASCADELAKE = PTA_SKYLAKE_AVX512 | PTA_AVX512VNNI; 2464const wide_int_bitmask PTA_COOPERLAKE = PTA_CASCADELAKE | PTA_AVX512BF16; 2465const wide_int_bitmask PTA_CANNONLAKE = PTA_SKYLAKE | PTA_AVX512F 2466 | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU 2467 | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA; 2468const wide_int_bitmask PTA_ICELAKE_CLIENT = PTA_CANNONLAKE | PTA_AVX512VNNI 2469 | PTA_GFNI | PTA_VAES | PTA_AVX512VBMI2 | PTA_VPCLMULQDQ | PTA_AVX512BITALG 2470 | PTA_RDPID | PTA_AVX512VPOPCNTDQ; 2471const wide_int_bitmask PTA_ICELAKE_SERVER = PTA_ICELAKE_CLIENT | PTA_PCONFIG 2472 | PTA_WBNOINVD | PTA_CLWB; 2473const wide_int_bitmask PTA_TIGERLAKE = PTA_ICELAKE_CLIENT | PTA_MOVDIRI 2474 | PTA_MOVDIR64B | PTA_CLWB | PTA_AVX512VP2INTERSECT; 2475const wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER 2476 | PTA_AVX512F | PTA_AVX512CD | PTA_PREFETCHWT1; 2477const wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE; 2478const wide_int_bitmask PTA_SILVERMONT = PTA_WESTMERE | PTA_MOVBE | PTA_RDRND 2479 | PTA_PRFCHW; 2480const wide_int_bitmask PTA_GOLDMONT = PTA_SILVERMONT | PTA_AES | PTA_SHA | PTA_XSAVE 2481 | PTA_RDSEED | PTA_XSAVEC | PTA_XSAVES | PTA_CLFLUSHOPT | PTA_XSAVEOPT 2482 | PTA_FSGSBASE; 2483const wide_int_bitmask PTA_GOLDMONT_PLUS = PTA_GOLDMONT | PTA_RDPID 2484 | PTA_SGX | PTA_PTWRITE; 2485const wide_int_bitmask PTA_TREMONT = PTA_GOLDMONT_PLUS | PTA_CLWB 2486 | PTA_GFNI | PTA_MOVDIRI | PTA_MOVDIR64B | PTA_CLDEMOTE | PTA_WAITPKG; 2487const wide_int_bitmask PTA_KNM = PTA_KNL | PTA_AVX5124VNNIW 2488 | PTA_AVX5124FMAPS | PTA_AVX512VPOPCNTDQ; 2489 2490#ifndef GENERATOR_FILE 2491 2492#include "insn-attr-common.h" 2493 2494#include "common/config/i386/i386-cpuinfo.h" 2495 2496class pta 2497{ 2498public: 2499 const char *const name; /* processor name or nickname. */ 2500 const enum processor_type processor; 2501 const enum attr_cpu schedule; 2502 const wide_int_bitmask flags; 2503 const int model; 2504 const enum feature_priority priority; 2505}; 2506 2507extern const pta processor_alias_table[]; 2508extern int const pta_size; 2509extern unsigned int const num_arch_names; 2510#endif 2511 2512#endif 2513 2514extern enum processor_type ix86_tune; 2515extern enum processor_type ix86_arch; 2516 2517/* Size of the RED_ZONE area. */ 2518#define RED_ZONE_SIZE 128 2519/* Reserved area of the red zone for temporaries. */ 2520#define RED_ZONE_RESERVE 8 2521 2522extern unsigned int ix86_preferred_stack_boundary; 2523extern unsigned int ix86_incoming_stack_boundary; 2524 2525/* Smallest class containing REGNO. */ 2526extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER]; 2527 2528enum ix86_fpcmp_strategy { 2529 IX86_FPCMP_SAHF, 2530 IX86_FPCMP_COMI, 2531 IX86_FPCMP_ARITH 2532}; 2533 2534/* To properly truncate FP values into integers, we need to set i387 control 2535 word. We can't emit proper mode switching code before reload, as spills 2536 generated by reload may truncate values incorrectly, but we still can avoid 2537 redundant computation of new control word by the mode switching pass. 2538 The fldcw instructions are still emitted redundantly, but this is probably 2539 not going to be noticeable problem, as most CPUs do have fast path for 2540 the sequence. 2541 2542 The machinery is to emit simple truncation instructions and split them 2543 before reload to instructions having USEs of two memory locations that 2544 are filled by this code to old and new control word. 2545 2546 Post-reload pass may be later used to eliminate the redundant fildcw if 2547 needed. */ 2548 2549enum ix86_stack_slot 2550{ 2551 SLOT_TEMP = 0, 2552 SLOT_CW_STORED, 2553 SLOT_CW_ROUNDEVEN, 2554 SLOT_CW_TRUNC, 2555 SLOT_CW_FLOOR, 2556 SLOT_CW_CEIL, 2557 SLOT_STV_TEMP, 2558 MAX_386_STACK_LOCALS 2559}; 2560 2561enum ix86_entity 2562{ 2563 X86_DIRFLAG = 0, 2564 AVX_U128, 2565 I387_ROUNDEVEN, 2566 I387_TRUNC, 2567 I387_FLOOR, 2568 I387_CEIL, 2569 MAX_386_ENTITIES 2570}; 2571 2572enum x86_dirflag_state 2573{ 2574 X86_DIRFLAG_RESET, 2575 X86_DIRFLAG_ANY 2576}; 2577 2578enum avx_u128_state 2579{ 2580 AVX_U128_CLEAN, 2581 AVX_U128_DIRTY, 2582 AVX_U128_ANY 2583}; 2584 2585/* Define this macro if the port needs extra instructions inserted 2586 for mode switching in an optimizing compilation. */ 2587 2588#define OPTIMIZE_MODE_SWITCHING(ENTITY) \ 2589 ix86_optimize_mode_switching[(ENTITY)] 2590 2591/* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as 2592 initializer for an array of integers. Each initializer element N 2593 refers to an entity that needs mode switching, and specifies the 2594 number of different modes that might need to be set for this 2595 entity. The position of the initializer in the initializer - 2596 starting counting at zero - determines the integer that is used to 2597 refer to the mode-switched entity in question. */ 2598 2599#define NUM_MODES_FOR_MODE_SWITCHING \ 2600 { X86_DIRFLAG_ANY, AVX_U128_ANY, \ 2601 I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY } 2602 2603 2604/* Avoid renaming of stack registers, as doing so in combination with 2605 scheduling just increases amount of live registers at time and in 2606 the turn amount of fxch instructions needed. 2607 2608 ??? Maybe Pentium chips benefits from renaming, someone can try.... 2609 2610 Don't rename evex to non-evex sse registers. */ 2611 2612#define HARD_REGNO_RENAME_OK(SRC, TARGET) \ 2613 (!STACK_REGNO_P (SRC) \ 2614 && EXT_REX_SSE_REGNO_P (SRC) == EXT_REX_SSE_REGNO_P (TARGET)) 2615 2616 2617#define FASTCALL_PREFIX '@' 2618 2619#ifndef USED_FOR_TARGET 2620/* Structure describing stack frame layout. 2621 Stack grows downward: 2622 2623 [arguments] 2624 <- ARG_POINTER 2625 saved pc 2626 2627 saved static chain if ix86_static_chain_on_stack 2628 2629 saved frame pointer if frame_pointer_needed 2630 <- HARD_FRAME_POINTER 2631 [saved regs] 2632 <- reg_save_offset 2633 [padding0] 2634 <- stack_realign_offset 2635 [saved SSE regs] 2636 OR 2637 [stub-saved registers for ms x64 --> sysv clobbers 2638 <- Start of out-of-line, stub-saved/restored regs 2639 (see libgcc/config/i386/(sav|res)ms64*.S) 2640 [XMM6-15] 2641 [RSI] 2642 [RDI] 2643 [?RBX] only if RBX is clobbered 2644 [?RBP] only if RBP and RBX are clobbered 2645 [?R12] only if R12 and all previous regs are clobbered 2646 [?R13] only if R13 and all previous regs are clobbered 2647 [?R14] only if R14 and all previous regs are clobbered 2648 [?R15] only if R15 and all previous regs are clobbered 2649 <- end of stub-saved/restored regs 2650 [padding1] 2651 ] 2652 <- sse_reg_save_offset 2653 [padding2] 2654 | <- FRAME_POINTER 2655 [va_arg registers] | 2656 | 2657 [frame] | 2658 | 2659 [padding2] | = to_allocate 2660 <- STACK_POINTER 2661 */ 2662struct GTY(()) ix86_frame 2663{ 2664 int nsseregs; 2665 int nregs; 2666 int va_arg_size; 2667 int red_zone_size; 2668 int outgoing_arguments_size; 2669 2670 /* The offsets relative to ARG_POINTER. */ 2671 HOST_WIDE_INT frame_pointer_offset; 2672 HOST_WIDE_INT hard_frame_pointer_offset; 2673 HOST_WIDE_INT stack_pointer_offset; 2674 HOST_WIDE_INT hfp_save_offset; 2675 HOST_WIDE_INT reg_save_offset; 2676 HOST_WIDE_INT stack_realign_allocate; 2677 HOST_WIDE_INT stack_realign_offset; 2678 HOST_WIDE_INT sse_reg_save_offset; 2679 2680 /* When save_regs_using_mov is set, emit prologue using 2681 move instead of push instructions. */ 2682 bool save_regs_using_mov; 2683 2684 /* Assume without checking that: 2685 EXPENSIVE_P = expensive_function_p (EXPENSIVE_COUNT). */ 2686 bool expensive_p; 2687 int expensive_count; 2688}; 2689 2690/* Machine specific frame tracking during prologue/epilogue generation. All 2691 values are positive, but since the x86 stack grows downward, are subtratced 2692 from the CFA to produce a valid address. */ 2693 2694struct GTY(()) machine_frame_state 2695{ 2696 /* This pair tracks the currently active CFA as reg+offset. When reg 2697 is drap_reg, we don't bother trying to record here the real CFA when 2698 it might really be a DW_CFA_def_cfa_expression. */ 2699 rtx cfa_reg; 2700 HOST_WIDE_INT cfa_offset; 2701 2702 /* The current offset (canonically from the CFA) of ESP and EBP. 2703 When stack frame re-alignment is active, these may not be relative 2704 to the CFA. However, in all cases they are relative to the offsets 2705 of the saved registers stored in ix86_frame. */ 2706 HOST_WIDE_INT sp_offset; 2707 HOST_WIDE_INT fp_offset; 2708 2709 /* The size of the red-zone that may be assumed for the purposes of 2710 eliding register restore notes in the epilogue. This may be zero 2711 if no red-zone is in effect, or may be reduced from the real 2712 red-zone value by a maximum runtime stack re-alignment value. */ 2713 int red_zone_offset; 2714 2715 /* Indicate whether each of ESP, EBP or DRAP currently holds a valid 2716 value within the frame. If false then the offset above should be 2717 ignored. Note that DRAP, if valid, *always* points to the CFA and 2718 thus has an offset of zero. */ 2719 BOOL_BITFIELD sp_valid : 1; 2720 BOOL_BITFIELD fp_valid : 1; 2721 BOOL_BITFIELD drap_valid : 1; 2722 2723 /* Indicate whether the local stack frame has been re-aligned. When 2724 set, the SP/FP offsets above are relative to the aligned frame 2725 and not the CFA. */ 2726 BOOL_BITFIELD realigned : 1; 2727 2728 /* Indicates whether the stack pointer has been re-aligned. When set, 2729 SP/FP continue to be relative to the CFA, but the stack pointer 2730 should only be used for offsets > sp_realigned_offset, while 2731 the frame pointer should be used for offsets <= sp_realigned_fp_last. 2732 The flags realigned and sp_realigned are mutually exclusive. */ 2733 BOOL_BITFIELD sp_realigned : 1; 2734 2735 /* If sp_realigned is set, this is the last valid offset from the CFA 2736 that can be used for access with the frame pointer. */ 2737 HOST_WIDE_INT sp_realigned_fp_last; 2738 2739 /* If sp_realigned is set, this is the offset from the CFA that the stack 2740 pointer was realigned, and may or may not be equal to sp_realigned_fp_last. 2741 Access via the stack pointer is only valid for offsets that are greater than 2742 this value. */ 2743 HOST_WIDE_INT sp_realigned_offset; 2744}; 2745 2746/* Private to winnt.c. */ 2747struct seh_frame_state; 2748 2749enum function_type 2750{ 2751 TYPE_UNKNOWN = 0, 2752 TYPE_NORMAL, 2753 /* The current function is an interrupt service routine with a 2754 pointer argument as specified by the "interrupt" attribute. */ 2755 TYPE_INTERRUPT, 2756 /* The current function is an interrupt service routine with a 2757 pointer argument and an integer argument as specified by the 2758 "interrupt" attribute. */ 2759 TYPE_EXCEPTION 2760}; 2761 2762struct GTY(()) machine_function { 2763 struct stack_local_entry *stack_locals; 2764 int varargs_gpr_size; 2765 int varargs_fpr_size; 2766 int optimize_mode_switching[MAX_386_ENTITIES]; 2767 2768 /* Cached initial frame layout for the current function. */ 2769 struct ix86_frame frame; 2770 2771 /* For -fsplit-stack support: A stack local which holds a pointer to 2772 the stack arguments for a function with a variable number of 2773 arguments. This is set at the start of the function and is used 2774 to initialize the overflow_arg_area field of the va_list 2775 structure. */ 2776 rtx split_stack_varargs_pointer; 2777 2778 /* This value is used for amd64 targets and specifies the current abi 2779 to be used. MS_ABI means ms abi. Otherwise SYSV_ABI means sysv abi. */ 2780 ENUM_BITFIELD(calling_abi) call_abi : 8; 2781 2782 /* Nonzero if the function accesses a previous frame. */ 2783 BOOL_BITFIELD accesses_prev_frame : 1; 2784 2785 /* Set by ix86_compute_frame_layout and used by prologue/epilogue 2786 expander to determine the style used. */ 2787 BOOL_BITFIELD use_fast_prologue_epilogue : 1; 2788 2789 /* Nonzero if the current function calls pc thunk and 2790 must not use the red zone. */ 2791 BOOL_BITFIELD pc_thunk_call_expanded : 1; 2792 2793 /* If true, the current function needs the default PIC register, not 2794 an alternate register (on x86) and must not use the red zone (on 2795 x86_64), even if it's a leaf function. We don't want the 2796 function to be regarded as non-leaf because TLS calls need not 2797 affect register allocation. This flag is set when a TLS call 2798 instruction is expanded within a function, and never reset, even 2799 if all such instructions are optimized away. Use the 2800 ix86_current_function_calls_tls_descriptor macro for a better 2801 approximation. */ 2802 BOOL_BITFIELD tls_descriptor_call_expanded_p : 1; 2803 2804 /* If true, the current function has a STATIC_CHAIN is placed on the 2805 stack below the return address. */ 2806 BOOL_BITFIELD static_chain_on_stack : 1; 2807 2808 /* If true, it is safe to not save/restore DRAP register. */ 2809 BOOL_BITFIELD no_drap_save_restore : 1; 2810 2811 /* Function type. */ 2812 ENUM_BITFIELD(function_type) func_type : 2; 2813 2814 /* How to generate indirec branch. */ 2815 ENUM_BITFIELD(indirect_branch) indirect_branch_type : 3; 2816 2817 /* If true, the current function has local indirect jumps, like 2818 "indirect_jump" or "tablejump". */ 2819 BOOL_BITFIELD has_local_indirect_jump : 1; 2820 2821 /* How to generate function return. */ 2822 ENUM_BITFIELD(indirect_branch) function_return_type : 3; 2823 2824 /* If true, the current function is a function specified with 2825 the "interrupt" or "no_caller_saved_registers" attribute. */ 2826 BOOL_BITFIELD no_caller_saved_registers : 1; 2827 2828 /* If true, there is register available for argument passing. This 2829 is used only in ix86_function_ok_for_sibcall by 32-bit to determine 2830 if there is scratch register available for indirect sibcall. In 2831 64-bit, rax, r10 and r11 are scratch registers which aren't used to 2832 pass arguments and can be used for indirect sibcall. */ 2833 BOOL_BITFIELD arg_reg_available : 1; 2834 2835 /* If true, we're out-of-lining reg save/restore for regs clobbered 2836 by 64-bit ms_abi functions calling a sysv_abi function. */ 2837 BOOL_BITFIELD call_ms2sysv : 1; 2838 2839 /* If true, the incoming 16-byte aligned stack has an offset (of 8) and 2840 needs padding prior to out-of-line stub save/restore area. */ 2841 BOOL_BITFIELD call_ms2sysv_pad_in : 1; 2842 2843 /* This is the number of extra registers saved by stub (valid range is 2844 0-6). Each additional register is only saved/restored by the stubs 2845 if all successive ones are. (Will always be zero when using a hard 2846 frame pointer.) */ 2847 unsigned int call_ms2sysv_extra_regs:3; 2848 2849 /* Nonzero if the function places outgoing arguments on stack. */ 2850 BOOL_BITFIELD outgoing_args_on_stack : 1; 2851 2852 /* If true, ENDBR is queued at function entrance. */ 2853 BOOL_BITFIELD endbr_queued_at_entrance : 1; 2854 2855 /* True if the function needs a stack frame. */ 2856 BOOL_BITFIELD stack_frame_required : 1; 2857 2858 /* True if __builtin_ia32_vzeroupper () has been expanded in current 2859 function. */ 2860 BOOL_BITFIELD has_explicit_vzeroupper : 1; 2861 2862 /* The largest alignment, in bytes, of stack slot actually used. */ 2863 unsigned int max_used_stack_alignment; 2864 2865 /* During prologue/epilogue generation, the current frame state. 2866 Otherwise, the frame state at the end of the prologue. */ 2867 struct machine_frame_state fs; 2868 2869 /* During SEH output, this is non-null. */ 2870 struct seh_frame_state * GTY((skip(""))) seh; 2871}; 2872 2873extern GTY(()) tree sysv_va_list_type_node; 2874extern GTY(()) tree ms_va_list_type_node; 2875#endif 2876 2877#define ix86_stack_locals (cfun->machine->stack_locals) 2878#define ix86_varargs_gpr_size (cfun->machine->varargs_gpr_size) 2879#define ix86_varargs_fpr_size (cfun->machine->varargs_fpr_size) 2880#define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching) 2881#define ix86_pc_thunk_call_expanded (cfun->machine->pc_thunk_call_expanded) 2882#define ix86_tls_descriptor_calls_expanded_in_cfun \ 2883 (cfun->machine->tls_descriptor_call_expanded_p) 2884/* Since tls_descriptor_call_expanded is not cleared, even if all TLS 2885 calls are optimized away, we try to detect cases in which it was 2886 optimized away. Since such instructions (use (reg REG_SP)), we can 2887 verify whether there's any such instruction live by testing that 2888 REG_SP is live. */ 2889#define ix86_current_function_calls_tls_descriptor \ 2890 (ix86_tls_descriptor_calls_expanded_in_cfun && df_regs_ever_live_p (SP_REG)) 2891#define ix86_static_chain_on_stack (cfun->machine->static_chain_on_stack) 2892#define ix86_red_zone_size (cfun->machine->frame.red_zone_size) 2893 2894/* Control behavior of x86_file_start. */ 2895#define X86_FILE_START_VERSION_DIRECTIVE false 2896#define X86_FILE_START_FLTUSED false 2897 2898/* Flag to mark data that is in the large address area. */ 2899#define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0) 2900#define SYMBOL_REF_FAR_ADDR_P(X) \ 2901 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0) 2902 2903/* Flags to mark dllimport/dllexport. Used by PE ports, but handy to 2904 have defined always, to avoid ifdefing. */ 2905#define SYMBOL_FLAG_DLLIMPORT (SYMBOL_FLAG_MACH_DEP << 1) 2906#define SYMBOL_REF_DLLIMPORT_P(X) \ 2907 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLIMPORT) != 0) 2908 2909#define SYMBOL_FLAG_DLLEXPORT (SYMBOL_FLAG_MACH_DEP << 2) 2910#define SYMBOL_REF_DLLEXPORT_P(X) \ 2911 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLEXPORT) != 0) 2912 2913#define SYMBOL_FLAG_STUBVAR (SYMBOL_FLAG_MACH_DEP << 4) 2914#define SYMBOL_REF_STUBVAR_P(X) \ 2915 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_STUBVAR) != 0) 2916 2917extern void debug_ready_dispatch (void); 2918extern void debug_dispatch_window (int); 2919 2920/* The value at zero is only defined for the BMI instructions 2921 LZCNT and TZCNT, not the BSR/BSF insns in the original isa. */ 2922#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 2923 ((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_BMI ? 1 : 0) 2924#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 2925 ((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_LZCNT ? 1 : 0) 2926 2927 2928/* Flags returned by ix86_get_callcvt (). */ 2929#define IX86_CALLCVT_CDECL 0x1 2930#define IX86_CALLCVT_STDCALL 0x2 2931#define IX86_CALLCVT_FASTCALL 0x4 2932#define IX86_CALLCVT_THISCALL 0x8 2933#define IX86_CALLCVT_REGPARM 0x10 2934#define IX86_CALLCVT_SSEREGPARM 0x20 2935 2936#define IX86_BASE_CALLCVT(FLAGS) \ 2937 ((FLAGS) & (IX86_CALLCVT_CDECL | IX86_CALLCVT_STDCALL \ 2938 | IX86_CALLCVT_FASTCALL | IX86_CALLCVT_THISCALL)) 2939 2940#define RECIP_MASK_NONE 0x00 2941#define RECIP_MASK_DIV 0x01 2942#define RECIP_MASK_SQRT 0x02 2943#define RECIP_MASK_VEC_DIV 0x04 2944#define RECIP_MASK_VEC_SQRT 0x08 2945#define RECIP_MASK_ALL (RECIP_MASK_DIV | RECIP_MASK_SQRT \ 2946 | RECIP_MASK_VEC_DIV | RECIP_MASK_VEC_SQRT) 2947#define RECIP_MASK_DEFAULT (RECIP_MASK_VEC_DIV | RECIP_MASK_VEC_SQRT) 2948 2949#define TARGET_RECIP_DIV ((recip_mask & RECIP_MASK_DIV) != 0) 2950#define TARGET_RECIP_SQRT ((recip_mask & RECIP_MASK_SQRT) != 0) 2951#define TARGET_RECIP_VEC_DIV ((recip_mask & RECIP_MASK_VEC_DIV) != 0) 2952#define TARGET_RECIP_VEC_SQRT ((recip_mask & RECIP_MASK_VEC_SQRT) != 0) 2953 2954/* Use 128-bit AVX instructions in the auto-vectorizer. */ 2955#define TARGET_PREFER_AVX128 (prefer_vector_width_type == PVW_AVX128) 2956/* Use 256-bit AVX instructions in the auto-vectorizer. */ 2957#define TARGET_PREFER_AVX256 (TARGET_PREFER_AVX128 \ 2958 || prefer_vector_width_type == PVW_AVX256) 2959 2960#define TARGET_INDIRECT_BRANCH_REGISTER \ 2961 (ix86_indirect_branch_register \ 2962 || cfun->machine->indirect_branch_type != indirect_branch_keep) 2963 2964#define IX86_HLE_ACQUIRE (1 << 16) 2965#define IX86_HLE_RELEASE (1 << 17) 2966 2967/* For switching between functions with different target attributes. */ 2968#define SWITCHABLE_TARGET 1 2969 2970#define TARGET_SUPPORTS_WIDE_INT 1 2971 2972#if !defined(GENERATOR_FILE) && !defined(IN_LIBGCC2) 2973extern enum attr_cpu ix86_schedule; 2974 2975#define NUM_X86_64_MS_CLOBBERED_REGS 12 2976#endif 2977 2978/* Standard location for 32-bit ASAN shadow map. */ 2979#define X86_32_ASAN_BIT_OFFSET 29 2980 2981/* 2982Local variables: 2983version-control: t 2984End: 2985*/ 2986