cr16.h revision 1.7
174462Salfred/* Definitions of target machine for GNU compiler, for CR16. 274462Salfred Copyright (C) 2012-2018 Free Software Foundation, Inc. 3261046Smav Contributed by KPIT Cummins Infosystems Limited. 4261046Smav 5261046Smav This file is part of GCC. 68870Srgrimes 7261046Smav GCC is free software; you can redistribute it and/or modify it 8261046Smav under the terms of the GNU General Public License as published 9261046Smav by the Free Software Foundation; either version 3, or (at your 10261046Smav option) any later version. 11261046Smav 12261046Smav GCC is distributed in the hope that it will be useful, but WITHOUT 13261046Smav ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14261046Smav or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15261046Smav License for more details. 16261046Smav 17261046Smav You should have received a copy of the GNU General Public License 18261046Smav along with GCC; see the file COPYING3. If not see 19261046Smav <http://www.gnu.org/licenses/>. */ 20261046Smav 21261046Smav#ifndef GCC_CR16_H 22261046Smav#define GCC_CR16_H 23261046Smav 24261046Smav#define OBJECT_FORMAT_ELF 25261046Smav 26261046Smav/* Controlling the driver. */ 27261046Smav 28261046Smav/* The GNU C++ standard library requires that these macros be defined. */ 291901Swollman#undef CPLUSPLUS_CPP_SPEC 3074462Salfred#define CPLUSPLUS_CPP_SPEC "-D_GNU_SOURCE %(cpp)" 3174462Salfred 3274462Salfred#undef STARTFILE_SPEC 331901Swollman#define STARTFILE_SPEC "crt1.o%s crti.o%s crtbegin.o%s crtlibid.o%s" 3474462Salfred 3592990Sobrien#undef ENDFILE_SPEC 3692990Sobrien#define ENDFILE_SPEC "crtend.o%s crtn.o%s" 371901Swollman 388870Srgrimes#undef MATH_LIBRARY 391901Swollman#define MATH_LIBRARY "" 401901Swollman 411901Swollman#undef LIB_SPEC 421901Swollman#define LIB_SPEC "-( -lc %{msim*:-lsim}%{!msim*:-lnosys} -) \ 4374462Salfred%{msim*:%{!T*:-Tsim.ld}} \ 4474462Salfred%{!T*:%{!msim*: %{-Telf32cr16.x}}}" 4574462Salfred 4674462Salfred/* Run-time target specification. */ 4774462Salfred#ifndef TARGET_CPU_CPP_BUILTINS 4874462Salfred#define TARGET_CPU_CPP_BUILTINS() \ 4974462Salfreddo \ 5075094Siedowse { \ 5174462Salfred builtin_define ("__CR__"); \ 5274462Salfred builtin_define ("__CR16__"); \ 5374462Salfred builtin_define ("__CR16C__"); \ 5474462Salfred if (TARGET_CR16CP) \ 551901Swollman builtin_define ("__CR16CP__"); \ 5611666Sphk else \ 5711666Sphk builtin_define ("__CR16CSTD__"); \ 5874462Salfred if (CR16_TARGET_DATA_NEAR) \ 5974462Salfred builtin_define ("__DATA_NEAR__"); \ 601901Swollman if (CR16_TARGET_DATA_MEDIUM) \ 6174462Salfred builtin_define ("__DATA_MEDIUM__"); \ 62156090Sdeischen if (CR16_TARGET_DATA_FAR) \ 6374462Salfred builtin_define ("__DATA_FAR__"); \ 6492905Sobrien if (TARGET_INT32) \ 6574462Salfred builtin_define ("__INT32__"); \ 661901Swollman } \ 6792905Sobrienwhile (0) 6874462Salfred#endif 6974462Salfred 7074462Salfred/* Force the generation of dwarf .debug_frame sections even if not 7174462Salfred compiling -g. This guarantees that we can unwind the stack. */ 7274462Salfred#define DWARF2_FRAME_INFO 1 7374462Salfred 7474462Salfred#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG 751901Swollman 761901Swollman/* Generate .file/.loc directives, so that the assembler generates the 771901Swollman line table. */ 781901Swollman#define DWARF2_ASM_LINE_DEBUG_INFO 1 7974462Salfred 8074462Salfred#define CR16_TARGET_DATA_NEAR cr16_is_data_model (DM_NEAR) 8174462Salfred#define CR16_TARGET_DATA_MEDIUM cr16_is_data_model (DM_DEFAULT) 8274462Salfred#define CR16_TARGET_DATA_FAR cr16_is_data_model (DM_FAR) 8374462Salfred 8474462Salfred/* Storage layout. */ 8574462Salfred#define BITS_BIG_ENDIAN 0 8674462Salfred 8774462Salfred#define BYTES_BIG_ENDIAN 0 8874462Salfred 8974462Salfred#define WORDS_BIG_ENDIAN 0 9074462Salfred 9174462Salfred#define UNITS_PER_WORD 2 9274462Salfred 9374462Salfred/* Units per 32-bit (DWORD). */ 9474462Salfred#define CR16_UNITS_PER_DWORD 4 9574462Salfred 9674462Salfred#define POINTER_SIZE 32 9721090Speter 9874462Salfred#define PARM_BOUNDARY 16 9974462Salfred 10074462Salfred#define STACK_BOUNDARY (MAX (BIGGEST_ALIGNMENT, PARM_BOUNDARY)) 10174462Salfred 10292905Sobrien#define FUNCTION_BOUNDARY BIGGEST_ALIGNMENT 10374462Salfred 10474462Salfred/* Biggest alignment on CR16C+ is 32-bit as internal bus is AMBA based 1051901Swollman where as CR16C is proprietary internal bus architecture. */ 10674462Salfred#define BIGGEST_ALIGNMENT ((TARGET_CR16CP) ? 32 : 16) 10774462Salfred 10874462Salfred#define MAX_FIXED_MODE_SIZE 64 1098870Srgrimes 11074462Salfred/* In CR16 arrays of chars are word-aligned, so strcpy () will be faster. */ 1111901Swollman#define DATA_ALIGNMENT(TYPE, ALIGN) \ 11274462Salfred (((TREE_CODE (TYPE) == ARRAY_TYPE) \ 11374462Salfred && (TYPE_MODE (TREE_TYPE (TYPE)) == QImode) \ 1141901Swollman && ((ALIGN) < BITS_PER_WORD)) \ 1151901Swollman ? (BITS_PER_WORD) : (ALIGN)) 11674462Salfred 11774462Salfred#define STRICT_ALIGNMENT 0 11874462Salfred 11974462Salfred#define PCC_BITFIELD_TYPE_MATTERS 1 12074462Salfred 12174462Salfred/* Layout of source language data types. */ 12274462Salfred#define INT_TYPE_SIZE (TARGET_INT32 ? 32 : 16) 12374462Salfred 12474462Salfred#define SHORT_TYPE_SIZE 16 12574462Salfred 12674462Salfred#define LONG_TYPE_SIZE 32 12774462Salfred 12874462Salfred#define LONG_LONG_TYPE_SIZE 64 12974462Salfred 13074462Salfred#define FLOAT_TYPE_SIZE 32 13174462Salfred 13274462Salfred#define DOUBLE_TYPE_SIZE 64 13374462Salfred 13474462Salfred#define LONG_DOUBLE_TYPE_SIZE 64 13590271Salfred 13690271Salfred#define DEFAULT_SIGNED_CHAR 1 13790271Salfred 13874462Salfred#define SIZE_TYPE "long unsigned int" 13974462Salfred 14074462Salfred#define PTRDIFF_TYPE "long int" 14174462Salfred 14274462Salfred#define WCHAR_TYPE "short unsigned int" 14374462Salfred 14474462Salfred#define WCHAR_TYPE_SIZE 16 14590271Salfred 14674462Salfred/* By default, the C++ compiler will use the lowest bit of the pointer 14774462Salfred to function to indicate a pointer-to-member-function points to a 14874462Salfred virtual member function. However, in CR architecture FUNCTION_BOUNDARY 14974462Salfred indicates function addresses are always even, but function pointers can be 15074462Salfred odd (after right-shifting them when loading them into a register), and the 15174462Salfred default doesn't work. In that case, the lowest bit of the delta 15274462Salfred field will be used (the remainder of the field is shifted to the left). */ 15374462Salfred#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta 15474462Salfred 15574462Salfred/* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return 15674462Salfred values must be in memory. */ 15774462Salfred#define DEFAULT_PCC_STRUCT_RETURN 0 15874462Salfred 15974462Salfred/* Register usage. */ 16074462Salfred 16174462Salfred/* First 32-bit register is R12. */ 16274462Salfred#define CR16_FIRST_DWORD_REGISTER 12 16374462Salfred 16474462Salfred#define FIRST_PSEUDO_REGISTER 16 16574462Salfred 16674462Salfred/* 1 for registers that have pervasive standard uses 167162195Smbr and are not available for the register allocator. 168162195Smbr On the CR16, only the stack pointer (r15) is such. */ 169162195Smbr#define FIXED_REGISTERS \ 170162195Smbr { \ 17174462Salfred /* r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10. */ \ 17274462Salfred 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 17374462Salfred /* r11 r12 r13 ra sp. */ \ 17474462Salfred 0, 0, 0, 0, 1 \ 1751901Swollman } 17674462Salfred 17774462Salfred/* 1 for registers not available across function calls. 17874462Salfred These must include the FIXED_REGISTERS and also any 17974462Salfred registers that can be used without being saved. 18074462Salfred The latter must include the registers where values are returned 18174462Salfred and the register where structure-value addresses are passed. 18274462Salfred 18374462Salfred On the CR16, calls clobbers r0-r6 (scratch registers), 18474462Salfred ra (the return address) and sp (the stack pointer). */ 18574462Salfred#define CALL_USED_REGISTERS \ 18674462Salfred { \ 18774462Salfred /* r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10. */ \ 18874462Salfred 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, \ 18974462Salfred /* r11 r12 r13 ra sp. */ \ 19074462Salfred 0, 0, 0, 1, 1 \ 19174462Salfred } 19274462Salfred 19374462Salfred/* Returns 1 if the register is longer than word size, 0 otherwise. */ 19474462Salfred#define LONG_REG_P(REGNO) \ 19574462Salfred (targetm.hard_regno_nregs (REGNO, \ 19674462Salfred GET_MODE_WIDER_MODE (word_mode).require ()) == 1) 19774462Salfred 19874462Salfred#define NOTICE_UPDATE_CC(EXP, INSN) \ 19974462Salfred notice_update_cc ((EXP)) 20074462Salfred 20174462Salfred/* Interrupt functions can only use registers that have already been 20274462Salfred saved by the prologue, even if they would normally be call-clobbered 20374462Salfred Check if sizes are same and then check if it is possible to rename. */ 20474462Salfred#define HARD_REGNO_RENAME_OK(SRC, DEST) \ 20574462Salfred (!cr16_interrupt_function_p () || (df_regs_ever_live_p (DEST))) 20674462Salfred 20774462Salfred/* Exception handling stuff. */ 20874462Salfred 20974462Salfred/*To ensure correct dwarf unwinding. */ 21074462Salfred#define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((optimize ("no-gcse","no-dse"))) 21174462Salfred 21274462Salfred#define gen_rtx_RA gen_rtx_REG (Pmode, RETURN_ADDRESS_REGNUM) 21374462Salfred 21474462Salfred/* Use (r8,r7) and (r10,r9) to pass exception handling information. */ 21574462Salfred#define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? (N*2 + 7) : INVALID_REGNUM) 21674462Salfred 21774462Salfred#define DWARF2_UNWIND_INFO 1 21874462Salfred 21974462Salfred/* (r5,r4) holds a stack adjustment for returning to a handler. */ 22074462Salfred#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 4) 22174462Salfred 22274462Salfred#define EH_RETURN_HANDLER_RTX \ 22374462Salfred gen_rtx_MEM (Pmode, plus_constant (Pmode, arg_pointer_rtx, -4)) 22474462Salfred 22574462Salfred#define INCOMING_RETURN_ADDR_RTX gen_rtx_RA 22674462Salfred 2271901Swollman#define DWARF_FRAME_RETURN_COLUMN \ 22874462Salfred DWARF_FRAME_REGNUM (RETURN_ADDRESS_REGNUM) 22974462Salfred 23074462Salfred#define INCOMING_FRAME_SP_OFFSET 0 23174462Salfred#define FRAME_POINTER_CFA_OFFSET(FNDECL) 0 23274462Salfred 23374462Salfred/* A C expression whose value is RTL representing the value of the return 2341901Swollman address for the frame COUNT steps up from the current frame. */ 2351901Swollman#define RETURN_ADDR_RTX(COUNT, FRAME) \ 2361901Swollman (COUNT == 0) ? gen_rtx_PLUS (Pmode, gen_rtx_RA, gen_rtx_RA) \ 2371901Swollman : const0_rtx 2381901Swollman 23974462Salfredenum reg_class 24074462Salfred{ 24174462Salfred NO_REGS, 24274462Salfred SHORT_REGS, 24374462Salfred LONG_REGS, 2441901Swollman NOSP_REGS, 2451901Swollman DOUBLE_BASE_REGS, 2461901Swollman GENERAL_REGS, 2471901Swollman ALL_REGS, 2481901Swollman LIM_REG_CLASSES 24974462Salfred}; 25074462Salfred 25174462Salfred#define N_REG_CLASSES (int) LIM_REG_CLASSES 2521901Swollman 25374462Salfred#define REG_CLASS_NAMES \ 2541901Swollman { \ 2551901Swollman "NO_REGS", \ 2568870Srgrimes "SHORT_REGS", \ 2571901Swollman "LONG_REGS", \ 2581901Swollman "NOSP_REGS", \ 2591901Swollman "DOUBLE_BASE_REGS", \ 26074462Salfred "GENERAL_REGS", \ 26174462Salfred "ALL_REGS" \ 26274462Salfred } 2631901Swollman 2641901Swollman#define REG_CLASS_CONTENTS \ 2651901Swollman { \ 2661901Swollman {0x00000000}, /* NO_REGS */ \ 26774462Salfred {0x00000FFF}, /* SHORT_REGS : 0 - 11 */ \ 2681901Swollman {0x0000F000}, /* LONG_REGS : 12 - 15 */ \ 26974462Salfred {0x00007FFF}, /* NOSP_REGS : 0 - 14 */ \ 27074462Salfred {0x0000F555}, /* DOUBLE_BASE_REGS : 2,4,6,8,10 */ \ 27174462Salfred {0x0000FFFF}, /* GENERAL_REGS : 0 - 15 */ \ 27274462Salfred {0x0000FFFF} /* ALL_REGS : 0 - 15 */ \ 27374462Salfred } 2741901Swollman 27574462Salfred#define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true 27674462Salfred 27774462Salfred#define REGNO_REG_CLASS(REGNO) cr16_regno_reg_class (REGNO) 27874462Salfred 27974462Salfred#define BASE_REG_CLASS GENERAL_REGS 28074462Salfred 28174462Salfred#define MODE_BASE_REG_CLASS(MODE) \ 28274462Salfred (GET_MODE_SIZE (MODE) <= 4 ? (BASE_REG_CLASS) : (DOUBLE_BASE_REGS)) 2831901Swollman 2841901Swollman#define INDEX_REG_CLASS LONG_REGS 28574462Salfred 2861901Swollman#define CR16_REGNO_OK_FOR_BASE_P(REGNO) \ 2871901Swollman (((REGNO) < FIRST_PSEUDO_REGISTER) \ 2881901Swollman || (reg_renumber && ((unsigned) reg_renumber[REGNO] \ 28974462Salfred < FIRST_PSEUDO_REGISTER))) 29074462Salfred 2911901Swollman/* Use even-numbered reg for 64-bit accesses. */ 29274462Salfred#define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 2931901Swollman (CR16_REGNO_OK_FOR_BASE_P(REGNO) && \ 29474462Salfred ((GET_MODE_SIZE (MODE) > 4 && \ 2951901Swollman (REGNO) < CR16_FIRST_DWORD_REGISTER) \ 29674462Salfred ? (((REGNO) & 1) == 0) \ 29774462Salfred : 1)) 29874462Salfred 29974462Salfred/* TODO: For now lets not support index addressing mode. */ 30074462Salfred#define REGNO_OK_FOR_INDEX_P(REGNO) \ 3011901Swollman (((REGNO >= CR16_FIRST_DWORD_REGISTER) \ 3021901Swollman && ((REGNO) < FIRST_PSEUDO_REGISTER)) \ 3031901Swollman || (reg_renumber \ 30474462Salfred && (((unsigned) reg_renumber[REGNO] >= CR16_FIRST_DWORD_REGISTER) \ 3051901Swollman && ((unsigned) reg_renumber[REGNO] < FIRST_PSEUDO_REGISTER))) \ 3061901Swollman ) 30774462Salfred 30874462Salfred#define PREFERRED_RELOAD_CLASS(X, CLASS) CLASS 30974462Salfred 31074462Salfred/* The maximum number of consecutive registers of class CLASS needed to 31174462Salfred hold a value of mode MODE. 3121901Swollman On the CompactRISC architecture, the size of MODE in words. 313 The size of MODE in double words for the class LONG_REGS. 314 315 The following check assumes if the class is not LONG_REGS, then 316 all (NO_REGS, SHORT_REGS, NOSP_REGS and GENERAL_REGS) other classes are 317 short. We may have to check if this can cause any degradation in 318 performance. */ 319#define CLASS_MAX_NREGS(CLASS, MODE) \ 320 (CLASS == LONG_REGS \ 321 ? (GET_MODE_SIZE (MODE) + CR16_UNITS_PER_DWORD - 1) / CR16_UNITS_PER_DWORD\ 322 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 323 324/* Macros to check the range of integers . These macros were used across 325 the port, majorly in constraints.md, predicates.md files. */ 326#define SIGNED_INT_FITS_N_BITS(imm, N) \ 327 ((((imm) < ((HOST_WIDE_INT) 1 << ((N) - 1))) \ 328 && ((imm) >= -((HOST_WIDE_INT) 1 << ((N) - 1)))) ? 1 : 0) 329 330#define UNSIGNED_INT_FITS_N_BITS(imm, N) \ 331 (((imm) < ((HOST_WIDE_INT) 1 << (N)) && (imm) >= (HOST_WIDE_INT) 0) ? 1 : 0) 332 333#define IN_RANGE_P(VALUE, LOW, HIGH) \ 334 ((((HOST_WIDE_INT)(VALUE)) >= (HOST_WIDE_INT)(LOW)) \ 335 && (((HOST_WIDE_INT)(VALUE)) <= ((HOST_WIDE_INT)(HIGH)))) 336 337#define IN_RAN(VALUE, LOW, HIGH) \ 338 (((((HOST_WIDE_INT)(VALUE)) >= (HOST_WIDE_INT)(LOW)) \ 339 && (((HOST_WIDE_INT)(VALUE)) <= ((HOST_WIDE_INT)(HIGH)))) ? 1 : 0) 340 341/* This check is for sbit/cbit instruction. */ 342#define OK_FOR_Z(OP) \ 343 ((GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == CONST_INT) \ 344 || (GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG) \ 345 || (GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == PLUS \ 346 && GET_CODE (XEXP ((XEXP (OP, 0)), 0)) == REG \ 347 && GET_CODE (XEXP ((XEXP (OP, 0)), 1)) == CONST_INT)) 348 349/* Stack layout and calling conventions. */ 350#define STACK_GROWS_DOWNWARD 1 351 352#define STACK_POINTER_REGNUM 15 353 354#define FRAME_POINTER_REGNUM 13 355 356#define ARG_POINTER_REGNUM 12 357 358#define STATIC_CHAIN_REGNUM 1 359 360#define RETURN_ADDRESS_REGNUM 14 361 362#define FIRST_PARM_OFFSET(FNDECL) 0 363 364#define ELIMINABLE_REGS \ 365 { \ 366 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 367 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ 368 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM} \ 369 } 370 371#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 372 do \ 373 { \ 374 (OFFSET) = cr16_initial_elimination_offset ((FROM), (TO)); \ 375 } \ 376 while (0) 377 378/* Passing function arguments. */ 379 380#define ACCUMULATE_OUTGOING_ARGS 0 381 382#define PUSH_ARGS 1 383 384#define PUSH_ROUNDING(BYTES) cr16_push_rounding (BYTES) 385 386#ifndef CUMULATIVE_ARGS 387struct cumulative_args 388{ 389 int ints; 390 int last_parm_in_reg; 391}; 392 393#define CUMULATIVE_ARGS struct cumulative_args 394#endif 395 396/* On the CR16 architecture, Varargs routines should receive their parameters 397 on the stack. */ 398 399#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 400 cr16_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME)) 401 402#define FUNCTION_ARG_REGNO_P(REGNO) cr16_function_arg_regno_p (REGNO) 403 404/* Generating code for profiling - NOT IMPLEMENTED. */ 405#undef FUNCTION_PROFILER 406#define FUNCTION_PROFILER(STREAM, LABELNO) \ 407{ \ 408 sorry ("profiler support for CR16"); \ 409} 410 411/* Trampolines for nested functions - NOT SUPPORTED. */ 412#define TRAMPOLINE_SIZE 16 413 414/* ADDRESSING MODES. */ 415 416#define CONSTANT_ADDRESS_P(X) \ 417 (GET_CODE (X) == LABEL_REF \ 418 || GET_CODE (X) == SYMBOL_REF \ 419 || GET_CODE (X) == CONST \ 420 || GET_CODE (X) == CONST_INT) 421 422#define MAX_REGS_PER_ADDRESS 2 423 424#define HAVE_POST_INCREMENT 0 425#define HAVE_POST_DECREMENT 0 426#define HAVE_POST_MODIFY_DISP 0 427#define HAVE_POST_MODIFY_REG 0 428 429#ifdef REG_OK_STRICT 430#define CR16_REG_OK_FOR_BASE_P(X) CR16_REGNO_OK_FOR_BASE_P (REGNO (X)) 431#define REG_MODE_OK_FOR_BASE_P(X, MODE) \ 432 REGNO_MODE_OK_FOR_BASE_P (REGNO(X), MODE) 433#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 434#else /* not REG_OK_STRICT. */ 435#define CR16_REG_OK_FOR_BASE_P(X) 1 436#define REG_MODE_OK_FOR_BASE_P(X, MODE) 1 437#define REG_OK_FOR_INDEX_P(X) 1 438#endif /* not REG_OK_STRICT. */ 439 440/* Assume best case (branch predicted). */ 441#define BRANCH_COST(speed_p, predictable_p) 2 442 443#define SLOW_BYTE_ACCESS 1 444 445/* It is as good or better to call a constant function address than to 446 call an address kept in a register. */ 447#define NO_FUNCTION_CSE 1 448 449/* Dividing the output into sections. */ 450 451#define TEXT_SECTION_ASM_OP "\t.section\t.text" 452 453#define DATA_SECTION_ASM_OP "\t.section\t.data" 454 455#define BSS_SECTION_ASM_OP "\t.section\t.bss" 456 457/* Position independent code (PIC). */ 458/* NEAR_PIC for -fpic option. */ 459 460#define NEAR_PIC 1 461 462/* FAR_PIC for -fPIC option. */ 463 464#define FAR_PIC 2 465 466#define PIC_OFFSET_TABLE_REGNUM 12 467 468#define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) 469 470/* Assembler format. */ 471 472/* Character to start a comment. */ 473#define ASM_COMMENT_START "#" 474 475#define GLOBAL_ASM_OP "\t.globl\t" 476 477#undef USER_LABEL_PREFIX 478#define USER_LABEL_PREFIX "_" 479 480#undef ASM_OUTPUT_LABELREF 481#define ASM_OUTPUT_LABELREF(STREAM, NAME) \ 482 asm_fprintf (STREAM, "%U%s", (*targetm.strip_name_encoding) (NAME)) 483 484#define ASM_OUTPUT_SYMBOL_REF(STREAM, SYMBOL) \ 485 do \ 486 { \ 487 const char *rn = XSTR (SYMBOL, 0); \ 488 assemble_name (STREAM, rn); \ 489 if (SYMBOL_REF_FUNCTION_P (SYMBOL)) \ 490 { \ 491 fprintf ((STREAM), "@c"); \ 492 } \ 493 } \ 494 while (0) 495 496#undef ASM_APP_ON 497#define ASM_APP_ON "#APP\n" 498 499#undef ASM_APP_OFF 500#define ASM_APP_OFF "#NO_APP\n" 501 502/* Switch into a generic section. */ 503#define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section 504 505#undef INIT_SECTION_ASM_OP 506#define INIT_SECTION_ASM_OP "\t.section\t.init" 507 508#undef FINI_SECTION_ASM_OP 509#define FINI_SECTION_ASM_OP "\t.section\t.fini" 510 511/* Instruction output. */ 512 513#define REGISTER_NAMES \ 514 { \ 515 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ 516 "r8", "r9", "r10", "r11", "r12", "r13", "ra", "sp" \ 517 } 518 519/* Output of dispatch tables. */ 520 521/* Revisit. No PC relative case as label expressions are not 522 properly supported in binutils else we could have done this: 523 #define CASE_VECTOR_PC_RELATIVE (optimize_size ? 1 : 0). */ 524#define CASE_VECTOR_PC_RELATIVE 0 525 526#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 527 ((GET_MODE (BODY) == QImode) \ 528 ? fprintf ((FILE), "\t.byte (.L%d-.L%d) >> 1\n", \ 529 VALUE, REL) \ 530 : fprintf ((FILE), "\t.word (.L%d-.L%d) >> 1\n", \ 531 VALUE, REL)) 532 533#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \ 534 asm_fprintf ((STREAM), "\t.long\t.L%d@c\n", (VALUE)) 535 536/* Alignment in assembler file. */ 537 538#define ASM_OUTPUT_ALIGN(STREAM, POWER) \ 539 asm_fprintf ((STREAM), "\t.align\t%d\n", 1 << (POWER)) 540 541/* Miscellaneous parameters. */ 542 543#define CASE_VECTOR_MODE Pmode 544 545#define MOVE_MAX 4 546 547#define STORE_FLAG_VALUE 1 548 549#define Pmode SImode 550 551#define FUNCTION_MODE QImode 552 553/* Define this boolean macro(s) to indicate whether or not your architecture 554 has (un)conditional branches that can span all of memory. It is used in 555 conjunction with an optimization that partitions hot and cold basic blocks 556 into separate sections of the executable. 557 CR16 contains branch instructions that span whole address space. */ 558#define HAS_LONG_COND_BRANCH 1 559#define HAS_LONG_UNCOND_BRANCH 1 560 561#endif /* End of GCC_CR16_H. */ 562