arm.opt revision 1.1 
1; Options for the ARM port of the compiler.
2
3; Copyright (C) 2005, 2007, 2008 Free Software Foundation, Inc.
4;
5; This file is part of GCC.
6;
7; GCC is free software; you can redistribute it and/or modify it under
8; the terms of the GNU General Public License as published by the Free
9; Software Foundation; either version 3, or (at your option) any later
10; version.
11;
12; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13; WARRANTY; without even the implied warranty of MERCHANTABILITY or
14; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
15; for more details.
16;
17; You should have received a copy of the GNU General Public License
18; along with GCC; see the file COPYING3.  If not see
19; <http://www.gnu.org/licenses/>.
20
21mabi=
22Target RejectNegative Joined Var(target_abi_name)
23Specify an ABI
24
25mabort-on-noreturn
26Target Report Mask(ABORT_NORETURN)
27Generate a call to abort if a noreturn function returns
28
29mapcs
30Target RejectNegative Mask(APCS_FRAME) MaskExists Undocumented
31
32mapcs-float
33Target Report Mask(APCS_FLOAT)
34Pass FP arguments in FP registers
35
36mapcs-frame
37Target Report Mask(APCS_FRAME)
38Generate APCS conformant stack frames
39
40mapcs-reentrant
41Target Report Mask(APCS_REENT)
42Generate re-entrant, PIC code
43
44mapcs-stack-check
45Target Report Mask(APCS_STACK) Undocumented
46
47march=
48Target RejectNegative Joined
49Specify the name of the target architecture
50
51marm
52Target RejectNegative InverseMask(THUMB) Undocumented
53
54mbig-endian
55Target Report RejectNegative Mask(BIG_END)
56Assume target CPU is configured as big endian
57
58mcallee-super-interworking
59Target Report Mask(CALLEE_INTERWORKING)
60Thumb: Assume non-static functions may be called from ARM code
61
62mcaller-super-interworking
63Target Report Mask(CALLER_INTERWORKING)
64Thumb: Assume function pointers may go to non-Thumb aware code
65
66mcirrus-fix-invalid-insns
67Target Report Mask(CIRRUS_FIX_INVALID_INSNS)
68Cirrus: Place NOPs to avoid invalid instruction combinations
69
70mcpu=
71Target RejectNegative Joined
72Specify the name of the target CPU
73
74mfloat-abi=
75Target RejectNegative Joined Var(target_float_abi_name)
76Specify if floating point hardware should be used
77
78mfp=
79Target RejectNegative Joined Undocumented Var(target_fpe_name)
80
81mfp16-format=
82Target RejectNegative Joined Var(target_fp16_format_name)
83Specify the __fp16 floating-point format
84
85;; Now ignored.
86mfpe
87Target RejectNegative Mask(FPE) Undocumented
88
89mfpe=
90Target RejectNegative Joined Undocumented Var(target_fpe_name)
91
92mfpu=
93Target RejectNegative Joined Var(target_fpu_name)
94Specify the name of the target floating point hardware/format
95
96mhard-float
97Target RejectNegative
98Alias for -mfloat-abi=hard
99
100mlittle-endian
101Target Report RejectNegative InverseMask(BIG_END)
102Assume target CPU is configured as little endian
103
104mlong-calls
105Target Report Mask(LONG_CALLS)
106Generate call insns as indirect calls, if necessary
107
108mpic-register=
109Target RejectNegative Joined Var(arm_pic_register_string)
110Specify the register to be used for PIC addressing
111
112mpoke-function-name
113Target Report Mask(POKE_FUNCTION_NAME)
114Store function names in object code
115
116msched-prolog
117Target Report Mask(SCHED_PROLOG)
118Permit scheduling of a function's prologue sequence
119
120msingle-pic-base
121Target Report Mask(SINGLE_PIC_BASE)
122Do not load the PIC register in function prologues
123
124msoft-float
125Target RejectNegative
126Alias for -mfloat-abi=soft
127
128mstructure-size-boundary=
129Target RejectNegative Joined Var(structure_size_string)
130Specify the minimum bit alignment of structures
131
132mthumb
133Target Report Mask(THUMB)
134Compile for the Thumb not the ARM
135
136mthumb-interwork
137Target Report Mask(INTERWORK)
138Support calls between Thumb and ARM instruction sets
139
140mtp=
141Target RejectNegative Joined Var(target_thread_switch)
142Specify how to access the thread pointer
143
144mtpcs-frame
145Target Report Mask(TPCS_FRAME)
146Thumb: Generate (non-leaf) stack frames even if not needed
147
148mtpcs-leaf-frame
149Target Report Mask(TPCS_LEAF_FRAME)
150Thumb: Generate (leaf) stack frames even if not needed
151
152mtune=
153Target RejectNegative Joined
154Tune code for the given processor
155
156mwords-little-endian
157Target Report RejectNegative Mask(LITTLE_WORDS)
158Assume big endian bytes, little endian words
159
160mvectorize-with-neon-quad
161Target Report Mask(NEON_VECTORIZE_QUAD)
162Use Neon quad-word (rather than double-word) registers for vectorization
163
164mword-relocations
165Target Report Var(target_word_relocations) Init(TARGET_DEFAULT_WORD_RELOCATIONS)
166Only generate absolute relocations on word sized values.
167
168mfix-cortex-m3-ldrd
169Target Report Var(fix_cm3_ldrd) Init(2)
170Avoid overlapping destination and address registers on LDRD instructions
171that may trigger Cortex-M3 errata.
172