arm-cpus.in revision 1.1.1.4
1# CPU, FPU and architecture specifications for ARM. 2# 3# Copyright (C) 2011-2020 Free Software Foundation, Inc. 4# 5# This file is part of GCC. 6# 7# GCC is free software; you can redistribute it and/or modify it under 8# the terms of the GNU General Public License as published by the Free 9# Software Foundation; either version 3, or (at your option) any later 10# version. 11# 12# GCC is distributed in the hope that it will be useful, but WITHOUT ANY 13# WARRANTY; without even the implied warranty of MERCHANTABILITY or 14# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15# for more details. 16# 17# You should have received a copy of the GNU General Public License 18# along with GCC; see the file COPYING3. If not see 19# <http://www.gnu.org/licenses/>. 20 21# This file describes all the various CPUs, FPUs and architectures supported 22# by the compiler. It is pre-processed by parsecpu.awk for a number of 23# purposes. 24# 25# The general form is a sequence of begin..end blocks with the following 26# syntax: 27# begin <object-type> <name> 28# attribute-statement* 29# end <object-type> <name> 30# 31# where object type is one of "cpu" "arch" "fpu". Each object type has 32# a specific set of permitted attributes, some of which are optional; further 33# details can be found below. 34# 35# Some objects cross-reference other objects by name. Objects are permitted 36# in any order and it is not necessary to place a cross-referenced object 37# earlier in the file. 38# 39# The object names for cpu, arch and fpu objects are used for the public option 40# names in the final compiler. The order within each group is preserved and 41# forms the order for the list within the compiler. 42 43# Most objects in this file support forward references. The major 44# exception is feature groups, which may only refer to previously 45# defined features or feature groups. This is done to avoid the risk 46# of feature groups recursively referencing each other and causing 47# the parser to hang. 48 49# Features - general convention: all lower case. 50 51# Architecture rel 4 52define feature armv4 53 54# Thumb aware. 55define feature thumb 56 57# Architecture rel 5t. 58define feature armv5t 59 60# Architecture rel 5te. 61define feature armv5te 62 63# XScale. 64define feature xscale 65 66# Architecture rel 6. 67define feature armv6 68 69# Architecture rel 6k. 70define feature armv6k 71 72# Thumb-2. 73define feature thumb2 74 75# Instructions not present in 'M' profile. 76define feature notm 77 78# Architecture uses be8 mode in big-endian. 79define feature be8 80 81# Thumb division instructions. 82define feature tdiv 83 84# Architecture rel 7e-m. 85define feature armv7em 86 87# Architecture rel 7. 88define feature armv7 89 90# MP extension to ArmV7-A 91define feature mp 92 93# SEC extension to ArmV7-A 94define feature sec 95 96# ARM division instructions. 97define feature adiv 98 99# Architecture rel 8. 100define feature armv8 101 102# ARMv8 CRC32 instructions. 103define feature crc32 104 105# XScale v2 (Wireless MMX). 106define feature iwmmxt 107 108# XScale Wireless MMX2. 109define feature iwmmxt2 110 111# Architecture rel 8.1. 112define feature armv8_1 113 114# Architecture rel 8.2. 115define feature armv8_2 116 117# Architecture rel 8.3. 118define feature armv8_3 119 120# Architecture rel 8.4. 121define feature armv8_4 122 123# Architecture rel 8.5. 124define feature armv8_5 125 126# Architecture rel 8.6. 127define feature armv8_6 128 129# M-Profile security extensions. 130define feature cmse 131 132# Architecture rel 8.1-M. 133define feature armv8_1m_main 134 135# Floating point and Neon extensions. 136# VFPv1 is not supported in GCC. 137 138# Vector floating point v2. 139define feature vfpv2 140 141# Vector floating point v3. 142define feature vfpv3 143 144# Vector floating point v4. 145define feature vfpv4 146 147# Floating point v5. 148define feature fpv5 149 150# ARMv7-A LPAE. 151define feature lpae 152 153# Advanced SIMD instructions. 154define feature neon 155 156# Conversions to/from fp16 (VFPv3 extension). 157define feature fp16conv 158 159# Double precision operations supported. 160define feature fp_dbl 161 162# 32 Double precision registers. 163define feature fp_d32 164 165# Crypto extension to ARMv8. 166define feature crypto 167 168# FP16 data processing (half-precision float). 169define feature fp16 170 171# Dot Product instructions extension to ARMv8.2-a. 172define feature dotprod 173 174# Half-precision floating-point instructions in ARMv8.4-A. 175define feature fp16fml 176 177# ISA Quirks (errata?). Don't forget to add this to the fgroup 178# ALL_QUIRKS below. 179 180# No volatile memory in IT blocks. 181define feature quirk_no_volatile_ce 182 183# Previously mis-identified by GCC. 184define feature quirk_armv6kz 185 186# Cortex-M3 LDRD quirk. 187define feature quirk_cm3_ldrd 188 189# v8-m/v8.1-m VLLDM errata. 190define feature quirk_vlldm 191 192# Don't use .cpu assembly directive 193define feature quirk_no_asmcpu 194 195# (Very) slow multiply operations. Should probably be a tuning bit. 196define feature smallmul 197 198# Speculation Barrier Instruction for v8-A architectures, added by 199# default to v8.5-A 200define feature sb 201 202# Execution and Data Prediction Restriction Instruction for 203# v8-A architectures, added by default from v8.5-A 204define feature predres 205 206# M-profile Vector Extension feature bits 207define feature mve 208define feature mve_float 209 210# 8-bit Integer Matrix Multiply extension. Optional from v8.2-A. 211define feature i8mm 212 213# Brain half-precision floating-point extension. Optional from v8.2-A. 214define feature bf16 215 216# Arm Custom Datapath Extension (CDE). 217define feature cdecp0 218define feature cdecp1 219define feature cdecp2 220define feature cdecp3 221define feature cdecp4 222define feature cdecp5 223define feature cdecp6 224define feature cdecp7 225 226# Feature groups. Conventionally all (or mostly) upper case. 227# ALL_FPU lists all the feature bits associated with the floating-point 228# unit; these will all be removed if the floating-point unit is disabled 229# (eg -mfloat-abi=soft). ALL_FPU_INTERNAL must ONLY contain features that 230# form part of a named -mfpu option; it is used to map the capabilities 231# back to a named FPU for the benefit of the assembler. 232# 233# ALL_SIMD_INTERNAL and ALL_SIMD are similarly defined to help with the 234# construction of ALL_FPU and ALL_FPU_INTERNAL; they describe the SIMD 235# extensions that are either part of a named FPU or optional extensions 236# respectively. 237 238 239# List of all cryptographic extensions to stripout if crypto is 240# disabled. Currently, that's trivial, but we define it anyway for 241# consistency with the SIMD and FP disable lists. 242define fgroup ALL_CRYPTO crypto 243 244# List of all SIMD bits to strip out if SIMD is disabled. This does 245# strip off 32 D-registers, but does not remove support for 246# double-precision FP. 247define fgroup ALL_SIMD_INTERNAL fp_d32 neon ALL_CRYPTO 248define fgroup ALL_SIMD_EXTERNAL dotprod fp16fml i8mm 249define fgroup ALL_SIMD ALL_SIMD_INTERNAL ALL_SIMD_EXTERNAL 250 251# List of all FPU bits to strip out if -mfpu is used to override the 252# default. fp16 is deliberately missing from this list. 253define fgroup ALL_FPU_INTERNAL vfpv2 vfpv3 vfpv4 fpv5 fp16conv fp_dbl ALL_SIMD_INTERNAL 254# Similarly, but including fp16 and other extensions that aren't part of 255# -mfpu support. 256define fgroup ALL_FPU_EXTERNAL fp16 bf16 257 258# Everything related to the FPU extensions (FP or SIMD). 259define fgroup ALL_FP ALL_FPU_EXTERNAL ALL_FPU_INTERNAL ALL_SIMD 260 261define fgroup ARMv4 armv4 notm 262define fgroup ARMv4t ARMv4 thumb 263define fgroup ARMv5t ARMv4t armv5t 264define fgroup ARMv5te ARMv5t armv5te 265define fgroup ARMv5tej ARMv5te 266define fgroup ARMv6 ARMv5te armv6 be8 267define fgroup ARMv6j ARMv6 268define fgroup ARMv6k ARMv6 armv6k 269define fgroup ARMv6z ARMv6 270define fgroup ARMv6kz ARMv6k quirk_armv6kz 271define fgroup ARMv6zk ARMv6k 272define fgroup ARMv6t2 ARMv6 thumb2 273# This is suspect. ARMv6-m doesn't really pull in any useful features 274# from ARMv5* or ARMv6. 275define fgroup ARMv6m armv4 thumb armv5t armv5te armv6 be8 276# This is suspect, the 'common' ARMv7 subset excludes the thumb2 'DSP' and 277# integer SIMD instructions that are in ARMv6T2. */ 278define fgroup ARMv7 ARMv6m thumb2 armv7 279 280define fgroup ARMv7a ARMv7 notm armv6k 281define fgroup ARMv7ve ARMv7a adiv tdiv lpae mp sec 282define fgroup ARMv7r ARMv7a tdiv 283define fgroup ARMv7m ARMv7 tdiv 284define fgroup ARMv7em ARMv7m armv7em 285define fgroup ARMv8a ARMv7ve armv8 286define fgroup ARMv8_1a ARMv8a crc32 armv8_1 287define fgroup ARMv8_2a ARMv8_1a armv8_2 288define fgroup ARMv8_3a ARMv8_2a armv8_3 289define fgroup ARMv8_4a ARMv8_3a armv8_4 290define fgroup ARMv8_5a ARMv8_4a armv8_5 sb predres 291define fgroup ARMv8_6a ARMv8_5a armv8_6 292define fgroup ARMv8m_base ARMv6m armv8 cmse tdiv 293define fgroup ARMv8m_main ARMv7m armv8 cmse 294define fgroup ARMv8r ARMv8a 295define fgroup ARMv8_1m_main ARMv8m_main armv8_1m_main 296 297# Useful combinations. 298define fgroup VFPv2 vfpv2 299define fgroup VFPv3 VFPv2 vfpv3 300define fgroup VFPv4 VFPv3 vfpv4 fp16conv 301define fgroup FPv5 VFPv4 fpv5 302define fgroup MVE mve armv7em 303define fgroup MVE_FP MVE FPv5 fp16 mve_float 304 305define fgroup FP_DBL fp_dbl 306define fgroup FP_D32 FP_DBL fp_d32 307define fgroup FP_ARMv8 FPv5 FP_D32 308define fgroup NEON FP_D32 neon 309define fgroup CRYPTO NEON crypto 310define fgroup DOTPROD NEON dotprod 311 312# Implied feature bits. These are for non-named features shared between fgroups. 313# Shared feature f belonging to fgroups A and B will be erroneously removed if: 314# A and B are enabled by default AND A is disabled by a removal flag. 315# To ensure that f is retained, we must add such bits to the ISA after 316# processing the removal flags. This is implemented by 'implied bits': 317# define implied <name> [<feature-or-fgroup>]+ 318# This indicates that, if any of the listed features are enabled, or if any 319# member of a listed fgroup is enabled, then <name> will be implicitly enabled. 320 321# Enabled for all VFP, MVE and MVE with floating point extensions. 322define implied vfp_base MVE MVE_FP ALL_FP 323 324# List of all quirk bits to strip out when comparing CPU features with 325# architectures. 326# xscale isn't really a 'quirk', but it isn't an architecture either and we 327# need to ignore it for matching purposes. 328define fgroup ALL_QUIRKS quirk_no_volatile_ce quirk_armv6kz quirk_cm3_ldrd quirk_vlldm xscale quirk_no_asmcpu 329 330define fgroup IGNORE_FOR_MULTILIB cdecp0 cdecp1 cdecp2 cdecp3 cdecp4 cdecp5 cdecp6 cdecp7 331 332# Architecture entries 333# format: 334# begin arch <name> 335# tune for <cpu> 336# [tune flags <list>] 337# base <name> 338# [profile <A|R|M>] 339# isa <isa-flags-list> 340# end arch <name> 341# 342 343begin arch armv4 344 tune for arm7tdmi 345 tune flags CO_PROC 346 base 4 347 isa ARMv4 348end arch armv4 349 350begin arch armv4t 351 tune for arm7tdmi 352 tune flags CO_PROC 353 base 4T 354 isa ARMv4t 355end arch armv4t 356 357begin arch armv5t 358 tune for arm10tdmi 359 tune flags CO_PROC 360 base 5T 361 isa ARMv5t 362end arch armv5t 363 364begin arch armv5te 365 tune for arm1026ej-s 366 tune flags CO_PROC 367 base 5TE 368 isa ARMv5te 369 option fp add VFPv2 FP_DBL 370 optalias vfpv2 fp 371 option nofp remove ALL_FP 372end arch armv5te 373 374begin arch armv5tej 375 tune for arm1026ej-s 376 tune flags CO_PROC 377 base 5TEJ 378 isa ARMv5tej 379 option fp add VFPv2 FP_DBL 380 optalias vfpv2 fp 381 option nofp remove ALL_FP 382end arch armv5tej 383 384begin arch armv6 385 tune for arm1136j-s 386 tune flags CO_PROC 387 base 6 388 isa ARMv6 389 option fp add VFPv2 FP_DBL 390 optalias vfpv2 fp 391 option nofp remove ALL_FP 392end arch armv6 393 394begin arch armv6j 395 tune for arm1136j-s 396 tune flags CO_PROC 397 base 6J 398 isa ARMv6j 399 option fp add VFPv2 FP_DBL 400 optalias vfpv2 fp 401 option nofp remove ALL_FP 402end arch armv6j 403 404begin arch armv6k 405 tune for mpcore 406 tune flags CO_PROC 407 base 6K 408 isa ARMv6k 409 option fp add VFPv2 FP_DBL 410 optalias vfpv2 fp 411 option nofp remove ALL_FP 412end arch armv6k 413 414begin arch armv6z 415 tune for arm1176jz-s 416 tune flags CO_PROC 417 base 6Z 418 isa ARMv6z 419 option fp add VFPv2 FP_DBL 420 optalias vfpv2 fp 421 option nofp remove ALL_FP 422end arch armv6z 423 424begin arch armv6kz 425 tune for arm1176jz-s 426 tune flags CO_PROC 427 base 6KZ 428 isa ARMv6kz 429 option fp add VFPv2 FP_DBL 430 optalias vfpv2 fp 431 option nofp remove ALL_FP 432end arch armv6kz 433 434begin arch armv6zk 435 tune for arm1176jz-s 436 tune flags CO_PROC 437 base 6KZ 438 isa ARMv6kz 439 option fp add VFPv2 FP_DBL 440 optalias vfpv2 fp 441 option nofp remove ALL_FP 442end arch armv6zk 443 444begin arch armv6t2 445 tune for arm1156t2-s 446 tune flags CO_PROC 447 base 6T2 448 isa ARMv6t2 449 option fp add VFPv2 FP_DBL 450 optalias vfpv2 fp 451 option nofp remove ALL_FP 452end arch armv6t2 453 454begin arch armv6-m 455 tune for cortex-m1 456 base 6M 457 profile M 458 isa ARMv6m 459end arch armv6-m 460 461# This is now equivalent to armv6-m, but we keep it because some 462# versions of GAS still distinguish between the two. 463begin arch armv6s-m 464 tune for cortex-m1 465 base 6M 466 profile M 467 isa ARMv6m 468end arch armv6s-m 469 470begin arch armv7 471 tune for cortex-a53 472 tune flags CO_PROC 473 base 7 474 isa ARMv7 475# fp => VFPv3-d16 (only useful for the A+R profile subset). 476 option fp add VFPv3 FP_DBL 477 optalias vfpv3-d16 fp 478 option nofp remove ALL_FP 479end arch armv7 480 481begin arch armv7-a 482 tune for cortex-a53 483 tune flags CO_PROC 484 base 7A 485 profile A 486 isa ARMv7a 487 option mp add mp 488 option sec add sec 489# fp => VFPv3-d16, simd => neon-vfpv3 490 option fp add VFPv3 FP_DBL 491 optalias vfpv3-d16 fp 492 option vfpv3 add VFPv3 FP_D32 493 option vfpv3-d16-fp16 add VFPv3 FP_DBL fp16conv 494 option vfpv3-fp16 add VFPv3 FP_DBL FP_D32 fp16conv 495 option vfpv4-d16 add VFPv4 FP_DBL 496 option vfpv4 add VFPv4 FP_D32 497 option simd add VFPv3 NEON 498 optalias neon simd 499 optalias neon-vfpv3 simd 500 option neon-fp16 add VFPv3 NEON fp16conv 501 option neon-vfpv4 add VFPv4 NEON 502 option nosimd remove ALL_SIMD 503 option nofp remove ALL_FP 504end arch armv7-a 505 506begin arch armv7ve 507 tune for cortex-a53 508 tune flags CO_PROC 509 base 7A 510 profile A 511 isa ARMv7ve 512# fp => VFPv4-d16, simd => neon-vfpv4 513 option vfpv3-d16 add VFPv3 FP_DBL 514 option vfpv3 add VFPv3 FP_D32 515 option vfpv3-d16-fp16 add VFPv3 FP_DBL fp16conv 516 option vfpv3-fp16 add VFPv3 FP_DBL FP_D32 fp16conv 517 option fp add VFPv4 FP_DBL 518 optalias vfpv4-d16 fp 519 option vfpv4 add VFPv4 FP_D32 520 option neon add VFPv3 NEON 521 optalias neon-vfpv3 neon 522 option neon-fp16 add VFPv3 NEON fp16conv 523 option simd add VFPv4 NEON 524 optalias neon-vfpv4 simd 525 option nosimd remove ALL_SIMD 526 option nofp remove ALL_FP 527end arch armv7ve 528 529begin arch armv7-r 530 tune for cortex-r4 531 tune flags CO_PROC 532 base 7R 533 profile R 534 isa ARMv7r 535# ARMv7-r uses VFPv3-d16 536 option fp.sp add VFPv3 537 optalias vfpv3xd fp.sp 538 option fp add VFPv3 FP_DBL 539 optalias vfpv3-d16 fp 540 option vfpv3xd-fp16 add VFPv3 fp16conv 541 option vfpv3-d16-fp16 add VFPv3 FP_DBL fp16conv 542 option idiv add adiv 543 option nofp remove ALL_FP 544 option noidiv remove adiv 545end arch armv7-r 546 547begin arch armv7-m 548 tune for cortex-m3 549 tune flags CO_PROC 550 base 7M 551 profile M 552 isa ARMv7m 553# In theory FP is permitted in v7-m, but in practice no implementations exist. 554# leave it out for now. 555end arch armv7-m 556 557begin arch armv7e-m 558 tune for cortex-m4 559 tune flags CO_PROC 560 base 7EM 561 profile M 562 isa ARMv7em 563# fp => VFPv4-sp-d16; fpv5 => FPv5-sp-d16; fp.dp => FPv5-d16 564 option fp add VFPv4 565 optalias vfpv4-sp-d16 fp 566 option fpv5 add FPv5 567 option fp.dp add FPv5 FP_DBL 568 optalias fpv5-d16 fp.dp 569 option nofp remove ALL_FP 570end arch armv7e-m 571 572begin arch armv8-a 573 tune for cortex-a53 574 tune flags CO_PROC 575 base 8A 576 profile A 577 isa ARMv8a 578 option crc add crc32 579 option simd add FP_ARMv8 NEON 580 option crypto add FP_ARMv8 CRYPTO 581 option nocrypto remove ALL_CRYPTO 582 option nofp remove ALL_FP 583 option sb add sb 584 option predres add predres 585end arch armv8-a 586 587begin arch armv8.1-a 588 tune for cortex-a53 589 tune flags CO_PROC 590 base 8A 591 profile A 592 isa ARMv8_1a 593 option simd add FP_ARMv8 NEON 594 option crypto add FP_ARMv8 CRYPTO 595 option nocrypto remove ALL_CRYPTO 596 option nofp remove ALL_FP 597 option sb add sb 598 option predres add predres 599end arch armv8.1-a 600 601begin arch armv8.2-a 602 tune for cortex-a53 603 tune flags CO_PROC 604 base 8A 605 profile A 606 isa ARMv8_2a 607 option simd add FP_ARMv8 NEON 608 option fp16 add fp16 FP_ARMv8 NEON 609 option fp16fml add fp16fml fp16 FP_ARMv8 NEON 610 option crypto add FP_ARMv8 CRYPTO 611 option nocrypto remove ALL_CRYPTO 612 option nofp remove ALL_FP 613 option dotprod add FP_ARMv8 DOTPROD 614 option sb add sb 615 option predres add predres 616 option i8mm add i8mm FP_ARMv8 NEON 617 option bf16 add bf16 FP_ARMv8 NEON 618end arch armv8.2-a 619 620begin arch armv8.3-a 621 tune for cortex-a53 622 tune flags CO_PROC 623 base 8A 624 profile A 625 isa ARMv8_3a 626 option simd add FP_ARMv8 NEON 627 option fp16 add fp16 FP_ARMv8 NEON 628 option fp16fml add fp16fml fp16 FP_ARMv8 NEON 629 option crypto add FP_ARMv8 CRYPTO 630 option nocrypto remove ALL_CRYPTO 631 option nofp remove ALL_FP 632 option dotprod add FP_ARMv8 DOTPROD 633 option sb add sb 634 option predres add predres 635 option i8mm add i8mm FP_ARMv8 NEON 636 option bf16 add bf16 FP_ARMv8 NEON 637end arch armv8.3-a 638 639begin arch armv8.4-a 640 tune for cortex-a53 641 tune flags CO_PROC 642 base 8A 643 profile A 644 isa ARMv8_4a 645 option simd add FP_ARMv8 DOTPROD 646 option fp16 add fp16 fp16fml FP_ARMv8 DOTPROD 647 option crypto add FP_ARMv8 CRYPTO DOTPROD 648 option nocrypto remove ALL_CRYPTO 649 option nofp remove ALL_FP 650 option sb add sb 651 option predres add predres 652 option i8mm add i8mm FP_ARMv8 DOTPROD 653 option bf16 add bf16 FP_ARMv8 DOTPROD 654end arch armv8.4-a 655 656begin arch armv8.5-a 657 tune for cortex-a53 658 tune flags CO_PROC 659 base 8A 660 profile A 661 isa ARMv8_5a 662 option simd add FP_ARMv8 DOTPROD 663 option fp16 add fp16 fp16fml FP_ARMv8 DOTPROD 664 option crypto add FP_ARMv8 CRYPTO DOTPROD 665 option nocrypto remove ALL_CRYPTO 666 option nofp remove ALL_FP 667 option i8mm add i8mm FP_ARMv8 DOTPROD 668 option bf16 add bf16 FP_ARMv8 DOTPROD 669end arch armv8.5-a 670 671begin arch armv8.6-a 672 tune for cortex-a53 673 tune flags CO_PROC 674 base 8A 675 profile A 676 isa ARMv8_6a 677 option simd add FP_ARMv8 DOTPROD 678 option fp16 add fp16 fp16fml FP_ARMv8 DOTPROD 679 option crypto add FP_ARMv8 CRYPTO DOTPROD 680 option nocrypto remove ALL_CRYPTO 681 option nofp remove ALL_FP 682 option i8mm add i8mm FP_ARMv8 DOTPROD 683 option bf16 add bf16 FP_ARMv8 DOTPROD 684end arch armv8.6-a 685 686begin arch armv8-m.base 687 tune for cortex-m23 688 base 8M_BASE 689 profile M 690 isa ARMv8m_base 691end arch armv8-m.base 692 693begin arch armv8-m.main 694 tune for cortex-m7 695 tune flags CO_PROC 696 base 8M_MAIN 697 profile M 698 isa ARMv8m_main 699 option dsp add armv7em 700# fp => FPv5-sp-d16; fp.dp => FPv5-d16 701 option fp add FPv5 702 option fp.dp add FPv5 FP_DBL 703 option nofp remove ALL_FP 704 option nodsp remove armv7em 705 option cdecp0 add cdecp0 706 option cdecp1 add cdecp1 707 option cdecp2 add cdecp2 708 option cdecp3 add cdecp3 709 option cdecp4 add cdecp4 710 option cdecp5 add cdecp5 711 option cdecp6 add cdecp6 712 option cdecp7 add cdecp7 713end arch armv8-m.main 714 715begin arch armv8-r 716 tune for cortex-r52 717 tune flags CO_PROC 718 base 8R 719 profile R 720 isa ARMv8r 721 option crc add crc32 722# fp.sp => fp-armv8 (d16); simd => simd + fp-armv8 + d32 + double precision 723# note: no fp option for fp-armv8 (d16) + double precision at the moment 724 option fp.sp add FPv5 725 option simd add FP_ARMv8 NEON 726 option crypto add FP_ARMv8 CRYPTO 727 option nocrypto remove ALL_CRYPTO 728 option nofp remove ALL_FP 729end arch armv8-r 730 731begin arch armv8.1-m.main 732 tune for cortex-m7 733 tune flags CO_PROC 734 base 8M_MAIN 735 profile M 736 isa ARMv8_1m_main 737# fp => FPv5-sp-d16; fp.dp => FPv5-d16 738 option dsp add armv7em 739 option fp add FPv5 fp16 740 option fp.dp add FPv5 FP_DBL fp16 741 option nofp remove ALL_FP 742 option mve add MVE 743 option mve.fp add MVE_FP 744 option cdecp0 add cdecp0 745 option cdecp1 add cdecp1 746 option cdecp2 add cdecp2 747 option cdecp3 add cdecp3 748 option cdecp4 add cdecp4 749 option cdecp5 add cdecp5 750 option cdecp6 add cdecp6 751 option cdecp7 add cdecp7 752end arch armv8.1-m.main 753 754begin arch iwmmxt 755 tune for iwmmxt 756 tune flags LDSCHED STRONG XSCALE 757 base 5TE 758 isa ARMv5te xscale iwmmxt 759end arch iwmmxt 760 761begin arch iwmmxt2 762 tune for iwmmxt2 763 tune flags LDSCHED STRONG XSCALE 764 base 5TE 765 isa ARMv5te xscale iwmmxt iwmmxt2 766end arch iwmmxt2 767 768# CPU entries 769# format: 770# begin cpu <name> 771# [cname <c-compatible-name>] 772# [alias <name>+] 773# [tune for <cpu-name>] 774# [tune flags <list>] 775# architecture <name> 776# [isa <additional-isa-flags-list>] 777# [option <name> add|remove <isa-list>]* 778# [optalias <name> <optname>]* 779# [costs <name>] 780# [vendor <vendor-id> 781# [part <part-id> [minrev [maxrev]]] 782# end cpu <name> 783# 784# If omitted, cname is formed from transforming the cpuname to convert 785# non-valid punctuation characters to '_'. 786# Any number of alias names may be specified for a CPU. If the name starts 787# with a '!' then it will be recognized as a valid name, but will not 788# be printed in any help text listing permitted CPUs. 789# If specified, tune for specifies a CPU target to use for tuning this core. 790# isa flags are appended to those defined by the architecture. 791# Each add option must have a distinct feature set and each remove 792# option must similarly have a distinct feature set. Option aliases can be 793# added with the optalias statement. 794# Vendor, part and revision information is used for native CPU and architecture 795# detection. All values must be in hex (lower case) with the leading '0x' 796# omitted. For example the cortex-a9 will have vendor 41 and part c09. 797# Revision information is used to match a subrange of part 798# revisions: minrev <= detected <= maxrev. 799# If a minrev or maxrev are omitted then minrev defaults to zero and maxrev 800# to infinity. 801# Revision information is not implemented yet; no part uses it. 802 803# V4 Architecture Processors 804begin cpu arm8 805 tune flags LDSCHED 806 architecture armv4 807 costs fastmul 808end cpu arm8 809 810begin cpu arm810 811 tune flags LDSCHED 812 architecture armv4 813 costs fastmul 814end cpu arm810 815 816begin cpu strongarm 817 alias strongarm110 !strongarm1100 !strongarm1110 818 tune flags LDSCHED STRONG 819 architecture armv4 820 costs strongarm 821end cpu strongarm 822 823begin cpu fa526 824 tune flags LDSCHED 825 architecture armv4 826 costs fastmul 827end cpu fa526 828 829begin cpu fa626 830 tune flags LDSCHED 831 architecture armv4 832 costs fastmul 833end cpu fa626 834 835 836# V4T Architecture Processors 837begin cpu arm7tdmi 838 alias arm7tdmi-s 839 tune flags CO_PROC 840 architecture armv4t 841 costs fastmul 842end cpu arm7tdmi 843 844begin cpu arm710t 845 alias arm720t arm740t 846 tune flags WBUF 847 architecture armv4t 848 costs fastmul 849end cpu arm710t 850 851begin cpu arm9 852 tune flags LDSCHED 853 architecture armv4t 854 costs fastmul 855end cpu arm9 856 857begin cpu arm9tdmi 858 tune flags LDSCHED 859 architecture armv4t 860 costs fastmul 861end cpu arm9tdmi 862 863begin cpu arm920t 864 alias arm920 arm922t arm940t ep9312 865 tune flags LDSCHED 866 architecture armv4t 867 costs fastmul 868end cpu arm920t 869 870 871# V5T Architecture Processors 872# These used VFPv1 which isn't supported by GCC 873begin cpu arm10tdmi 874 alias arm1020t 875 tune flags LDSCHED 876 architecture armv5t 877 costs fastmul 878end cpu arm10tdmi 879 880 881# V5TE Architecture Processors 882begin cpu arm9e 883 alias arm946e-s arm966e-s arm968e-s 884 tune flags LDSCHED 885 architecture armv5te+fp 886 option nofp remove ALL_FP 887 costs 9e 888end cpu arm9e 889 890begin cpu arm10e 891 alias arm1020e arm1022e 892 tune flags LDSCHED 893 architecture armv5te+fp 894 option nofp remove ALL_FP 895 costs fastmul 896end cpu arm10e 897 898begin cpu xscale 899 tune flags LDSCHED XSCALE 900 architecture armv5te 901 isa xscale 902 costs xscale 903end cpu xscale 904 905begin cpu iwmmxt 906 tune flags LDSCHED XSCALE 907 architecture iwmmxt 908 costs xscale 909end cpu iwmmxt 910 911begin cpu iwmmxt2 912 tune flags LDSCHED XSCALE 913 architecture iwmmxt2 914 costs xscale 915end cpu iwmmxt2 916 917begin cpu fa606te 918 tune flags LDSCHED 919 architecture armv5te 920 costs 9e 921end cpu fa606te 922 923begin cpu fa626te 924 tune flags LDSCHED 925 architecture armv5te 926 costs 9e 927end cpu fa626te 928 929begin cpu fmp626 930 tune flags LDSCHED 931 architecture armv5te 932 costs 9e 933end cpu fmp626 934 935begin cpu fa726te 936 tune flags LDSCHED 937 architecture armv5te 938 costs fa726te 939end cpu fa726te 940 941 942# V5TEJ Architecture Processors 943begin cpu arm926ej-s 944 cname arm926ejs 945 tune flags LDSCHED 946 architecture armv5tej+fp 947 option nofp remove ALL_FP 948 costs 9e 949 vendor 41 950 part 926 951end cpu arm926ej-s 952 953begin cpu arm1026ej-s 954 cname arm1026ejs 955 tune flags LDSCHED 956 architecture armv5tej+fp 957 option nofp remove ALL_FP 958 costs 9e 959 vendor 41 960 part a26 961end cpu arm1026ej-s 962 963 964# V6 Architecture Processors 965begin cpu arm1136j-s 966 cname arm1136js 967 tune flags LDSCHED 968 architecture armv6j 969 costs 9e 970end cpu arm1136j-s 971 972begin cpu arm1136jf-s 973 cname arm1136jfs 974 tune flags LDSCHED 975 architecture armv6j+fp 976 costs 9e 977 vendor 41 978 part b36 979end cpu arm1136jf-s 980 981begin cpu arm1176jz-s 982 cname arm1176jzs 983 tune flags LDSCHED 984 architecture armv6kz 985 costs 9e 986end cpu arm1176jz-s 987 988begin cpu arm1176jzf-s 989 cname arm1176jzfs 990 tune flags LDSCHED 991 architecture armv6kz+fp 992 costs 9e 993 vendor 41 994 part b76 995end cpu arm1176jzf-s 996 997begin cpu mpcorenovfp 998 tune flags LDSCHED 999 architecture armv6k 1000 costs 9e 1001end cpu mpcorenovfp 1002 1003begin cpu mpcore 1004 tune flags LDSCHED 1005 architecture armv6k+fp 1006 costs 9e 1007 vendor 41 1008 part b02 1009end cpu mpcore 1010 1011begin cpu arm1156t2-s 1012 cname arm1156t2s 1013 tune flags LDSCHED 1014 architecture armv6t2 1015 costs v6t2 1016end cpu arm1156t2-s 1017 1018begin cpu arm1156t2f-s 1019 cname arm1156t2fs 1020 tune flags LDSCHED 1021 architecture armv6t2+fp 1022 costs v6t2 1023 vendor 41 1024 part b56 1025end cpu arm1156t2f-s 1026 1027 1028# V6M Architecture Processors 1029begin cpu cortex-m1 1030 cname cortexm1 1031 tune flags LDSCHED 1032 architecture armv6s-m 1033 costs v6m 1034 vendor 41 1035 part c21 1036end cpu cortex-m1 1037 1038begin cpu cortex-m0 1039 cname cortexm0 1040 tune flags LDSCHED 1041 architecture armv6s-m 1042 costs v6m 1043 vendor 41 1044 part c20 1045end cpu cortex-m0 1046 1047begin cpu cortex-m0plus 1048 cname cortexm0plus 1049 tune flags LDSCHED 1050 architecture armv6s-m 1051 costs v6m 1052end cpu cortex-m0plus 1053 1054 1055# V6M Architecture Processors for small-multiply implementations. 1056begin cpu cortex-m1.small-multiply 1057 cname cortexm1smallmultiply 1058 tune for cortex-m1 1059 tune flags LDSCHED SMALLMUL 1060 architecture armv6s-m 1061 costs v6m 1062end cpu cortex-m1.small-multiply 1063 1064begin cpu cortex-m0.small-multiply 1065 cname cortexm0smallmultiply 1066 tune for cortex-m0 1067 tune flags LDSCHED SMALLMUL 1068 architecture armv6s-m 1069 costs v6m 1070end cpu cortex-m0.small-multiply 1071 1072begin cpu cortex-m0plus.small-multiply 1073 cname cortexm0plussmallmultiply 1074 tune for cortex-m0plus 1075 tune flags LDSCHED SMALLMUL 1076 architecture armv6s-m 1077 costs v6m 1078end cpu cortex-m0plus.small-multiply 1079 1080 1081# V7 Architecture Processors 1082begin cpu generic-armv7-a 1083 cname genericv7a 1084 tune flags LDSCHED 1085 architecture armv7-a+fp 1086 isa quirk_no_asmcpu 1087 option mp add mp 1088 option sec add sec 1089 option vfpv3-d16 add VFPv3 FP_DBL 1090 option vfpv3 add VFPv3 FP_D32 1091 option vfpv3-d16-fp16 add VFPv3 FP_DBL fp16conv 1092 option vfpv3-fp16 add VFPv3 FP_D32 fp16conv 1093 option vfpv4-d16 add VFPv4 FP_DBL 1094 option vfpv4 add VFPv4 FP_D32 1095 option simd add VFPv3 NEON 1096 optalias neon simd 1097 optalias neon-vfpv3 simd 1098 option neon-fp16 add VFPv3 NEON fp16conv 1099 option neon-vfpv4 add VFPv4 NEON 1100 option nosimd remove ALL_SIMD 1101 option nofp remove ALL_FP 1102 costs cortex 1103end cpu generic-armv7-a 1104 1105begin cpu cortex-a5 1106 cname cortexa5 1107 tune flags LDSCHED 1108 architecture armv7-a+mp+sec+neon-fp16 1109 option nosimd remove ALL_SIMD 1110 option nofp remove ALL_FP 1111 costs cortex_a5 1112 vendor 41 1113 part c05 1114end cpu cortex-a5 1115 1116begin cpu cortex-a7 1117 cname cortexa7 1118 tune flags LDSCHED 1119 architecture armv7ve+simd 1120 option nosimd remove ALL_SIMD 1121 option nofp remove ALL_FP 1122 costs cortex_a7 1123 vendor 41 1124 part c07 1125end cpu cortex-a7 1126 1127begin cpu cortex-a8 1128 cname cortexa8 1129 tune flags LDSCHED 1130 architecture armv7-a+sec+simd 1131 option nofp remove ALL_FP 1132 costs cortex_a8 1133 vendor 41 1134 part c08 1135end cpu cortex-a8 1136 1137begin cpu cortex-a9 1138 cname cortexa9 1139 tune flags LDSCHED 1140 architecture armv7-a+mp+sec+neon-fp16 1141 option nosimd remove ALL_SIMD 1142 option nofp remove ALL_FP 1143 costs cortex_a9 1144 vendor 41 1145 part c09 1146end cpu cortex-a9 1147 1148begin cpu cortex-a12 1149 cname cortexa12 1150 tune for cortex-a17 1151 tune flags LDSCHED 1152 architecture armv7ve+simd 1153 option nofp remove ALL_FP 1154 costs cortex_a12 1155 vendor 41 1156 part c0d 1157end cpu cortex-a12 1158 1159begin cpu cortex-a15 1160 cname cortexa15 1161 tune flags LDSCHED 1162 architecture armv7ve+simd 1163 option nofp remove ALL_FP 1164 costs cortex_a15 1165 vendor 41 1166 part c0f 1167end cpu cortex-a15 1168 1169begin cpu cortex-a17 1170 cname cortexa17 1171 tune flags LDSCHED 1172 architecture armv7ve+simd 1173 option nofp remove ALL_FP 1174 costs cortex_a12 1175 vendor 41 1176 part c0e 1177end cpu cortex-a17 1178 1179begin cpu cortex-r4 1180 cname cortexr4 1181 tune flags LDSCHED 1182 architecture armv7-r 1183 costs cortex 1184end cpu cortex-r4 1185 1186begin cpu cortex-r4f 1187 cname cortexr4f 1188 tune flags LDSCHED 1189 architecture armv7-r+fp 1190 costs cortex 1191 vendor 41 1192 part c14 1193end cpu cortex-r4f 1194 1195begin cpu cortex-r5 1196 cname cortexr5 1197 tune flags LDSCHED 1198 architecture armv7-r+idiv+fp 1199 option nofp.dp remove FP_DBL 1200 option nofp remove ALL_FP 1201 costs cortex 1202 vendor 41 1203 part c15 1204end cpu cortex-r5 1205 1206begin cpu cortex-r7 1207 cname cortexr7 1208 tune flags LDSCHED 1209 architecture armv7-r+idiv+vfpv3-d16-fp16 1210 option nofp.dp remove FP_DBL 1211 option nofp remove ALL_FP 1212 costs cortex 1213 vendor 41 1214 part c17 1215end cpu cortex-r7 1216 1217begin cpu cortex-r8 1218 cname cortexr8 1219 tune for cortex-r7 1220 tune flags LDSCHED 1221 architecture armv7-r+idiv+vfpv3-d16-fp16 1222 option nofp.dp remove FP_DBL 1223 option nofp remove ALL_FP 1224 costs cortex 1225 vendor 41 1226 part c18 1227end cpu cortex-r8 1228 1229begin cpu cortex-m7 1230 cname cortexm7 1231 tune flags LDSCHED 1232 architecture armv7e-m+fp.dp 1233 isa quirk_no_volatile_ce 1234 option nofp.dp remove FP_DBL 1235 option nofp remove ALL_FP 1236 costs cortex_m7 1237end cpu cortex-m7 1238 1239begin cpu cortex-m4 1240 cname cortexm4 1241 tune flags LDSCHED 1242 architecture armv7e-m+fp 1243 option nofp remove ALL_FP 1244 costs v7m 1245 vendor 41 1246 part c24 1247end cpu cortex-m4 1248 1249begin cpu cortex-m3 1250 cname cortexm3 1251 tune flags LDSCHED 1252 architecture armv7-m 1253 isa quirk_cm3_ldrd 1254 costs v7m 1255 vendor 41 1256 part c23 1257end cpu cortex-m3 1258 1259begin cpu marvell-pj4 1260 tune flags LDSCHED 1261 architecture armv7-a+mp+sec+fp 1262 costs marvell_pj4 1263end cpu marvell-pj4 1264 1265 1266# V7 big.LITTLE implementations 1267begin cpu cortex-a15.cortex-a7 1268 cname cortexa15cortexa7 1269 tune for cortex-a7 1270 tune flags LDSCHED 1271 architecture armv7ve+simd 1272 option nofp remove ALL_FP 1273 costs cortex_a15 1274end cpu cortex-a15.cortex-a7 1275 1276begin cpu cortex-a17.cortex-a7 1277 cname cortexa17cortexa7 1278 tune for cortex-a7 1279 tune flags LDSCHED 1280 architecture armv7ve+simd 1281 option nofp remove ALL_FP 1282 costs cortex_a12 1283end cpu cortex-a17.cortex-a7 1284 1285 1286# V8 A-profile Architecture Processors 1287begin cpu cortex-a32 1288 cname cortexa32 1289 tune for cortex-a53 1290 tune flags LDSCHED 1291 architecture armv8-a+crc+simd 1292 option crypto add FP_ARMv8 CRYPTO 1293 option nofp remove ALL_FP 1294 costs cortex_a35 1295 vendor 41 1296 part d01 1297end cpu cortex-a32 1298 1299begin cpu cortex-a35 1300 cname cortexa35 1301 tune for cortex-a53 1302 tune flags LDSCHED 1303 architecture armv8-a+crc+simd 1304 option crypto add FP_ARMv8 CRYPTO 1305 option nofp remove ALL_FP 1306 costs cortex_a35 1307 vendor 41 1308 part d04 1309end cpu cortex-a35 1310 1311begin cpu cortex-a53 1312 cname cortexa53 1313 tune flags LDSCHED 1314 architecture armv8-a+crc+simd 1315 option crypto add FP_ARMv8 CRYPTO 1316 option nofp remove ALL_FP 1317 costs cortex_a53 1318 vendor 41 1319 part d03 1320end cpu cortex-a53 1321 1322begin cpu cortex-a57 1323 cname cortexa57 1324 tune flags LDSCHED 1325 architecture armv8-a+crc+simd 1326 option crypto add FP_ARMv8 CRYPTO 1327 costs cortex_a57 1328 vendor 41 1329 part d07 1330end cpu cortex-a57 1331 1332begin cpu cortex-a72 1333 cname cortexa72 1334 tune for cortex-a57 1335 tune flags LDSCHED 1336 architecture armv8-a+crc+simd 1337 option crypto add FP_ARMv8 CRYPTO 1338 costs cortex_a57 1339 vendor 41 1340 part d08 1341end cpu cortex-a72 1342 1343begin cpu cortex-a73 1344 cname cortexa73 1345 tune for cortex-a57 1346 tune flags LDSCHED 1347 architecture armv8-a+crc+simd 1348 option crypto add FP_ARMv8 CRYPTO 1349 costs cortex_a73 1350 vendor 41 1351 part d09 1352end cpu cortex-a73 1353 1354begin cpu exynos-m1 1355 cname exynosm1 1356 tune flags LDSCHED 1357 architecture armv8-a+crc+simd 1358 option crypto add FP_ARMv8 CRYPTO 1359 costs exynosm1 1360end cpu exynos-m1 1361 1362begin cpu xgene1 1363 tune flags LDSCHED 1364 architecture armv8-a+simd 1365 option crypto add FP_ARMv8 CRYPTO 1366 costs xgene1 1367end cpu xgene1 1368 1369# V8 A-profile big.LITTLE implementations 1370begin cpu cortex-a57.cortex-a53 1371 cname cortexa57cortexa53 1372 tune for cortex-a53 1373 tune flags LDSCHED 1374 architecture armv8-a+crc+simd 1375 option crypto add FP_ARMv8 CRYPTO 1376 costs cortex_a57 1377end cpu cortex-a57.cortex-a53 1378 1379begin cpu cortex-a72.cortex-a53 1380 cname cortexa72cortexa53 1381 tune for cortex-a53 1382 tune flags LDSCHED 1383 architecture armv8-a+crc+simd 1384 option crypto add FP_ARMv8 CRYPTO 1385 costs cortex_a57 1386end cpu cortex-a72.cortex-a53 1387 1388begin cpu cortex-a73.cortex-a35 1389 cname cortexa73cortexa35 1390 tune for cortex-a53 1391 tune flags LDSCHED 1392 architecture armv8-a+crc+simd 1393 option crypto add FP_ARMv8 CRYPTO 1394 costs cortex_a73 1395end cpu cortex-a73.cortex-a35 1396 1397begin cpu cortex-a73.cortex-a53 1398 cname cortexa73cortexa53 1399 tune for cortex-a53 1400 tune flags LDSCHED 1401 architecture armv8-a+crc+simd 1402 option crypto add FP_ARMv8 CRYPTO 1403 costs cortex_a73 1404end cpu cortex-a73.cortex-a53 1405 1406 1407# ARMv8.2 A-profile Architecture Processors 1408begin cpu cortex-a55 1409 cname cortexa55 1410 tune for cortex-a53 1411 tune flags LDSCHED 1412 architecture armv8.2-a+fp16+dotprod 1413 option crypto add FP_ARMv8 CRYPTO 1414 option nofp remove ALL_FP 1415 costs cortex_a53 1416 vendor 41 1417 part d05 1418end cpu cortex-a55 1419 1420begin cpu cortex-a75 1421 cname cortexa75 1422 tune for cortex-a57 1423 tune flags LDSCHED 1424 architecture armv8.2-a+fp16+dotprod 1425 option crypto add FP_ARMv8 CRYPTO 1426 costs cortex_a73 1427 vendor 41 1428 part d0a 1429end cpu cortex-a75 1430 1431begin cpu cortex-a76 1432 cname cortexa76 1433 tune for cortex-a57 1434 tune flags LDSCHED 1435 architecture armv8.2-a+fp16+dotprod 1436 option crypto add FP_ARMv8 CRYPTO 1437 costs cortex_a57 1438 vendor 41 1439 part d0b 1440end cpu cortex-a76 1441 1442begin cpu cortex-a76ae 1443 cname cortexa76ae 1444 tune for cortex-a57 1445 tune flags LDSCHED 1446 architecture armv8.2-a+fp16+dotprod 1447 option crypto add FP_ARMv8 CRYPTO 1448 costs cortex_a57 1449 vendor 41 1450 part d0e 1451end cpu cortex-a76ae 1452 1453begin cpu cortex-a77 1454 cname cortexa77 1455 tune for cortex-a57 1456 tune flags LDSCHED 1457 architecture armv8.2-a+fp16+dotprod 1458 option crypto add FP_ARMv8 CRYPTO 1459 costs cortex_a57 1460 vendor 41 1461 part d0d 1462end cpu cortex-a77 1463 1464begin cpu neoverse-n1 1465 cname neoversen1 1466 alias !ares 1467 tune for cortex-a57 1468 tune flags LDSCHED 1469 architecture armv8.2-a+fp16+dotprod 1470 option crypto add FP_ARMv8 CRYPTO 1471 costs cortex_a57 1472 vendor 41 1473 part d0c 1474end cpu neoverse-n1 1475 1476# ARMv8.2 A-profile ARM DynamIQ big.LITTLE implementations 1477begin cpu cortex-a75.cortex-a55 1478 cname cortexa75cortexa55 1479 tune for cortex-a53 1480 tune flags LDSCHED 1481 architecture armv8.2-a+fp16+dotprod 1482 option crypto add FP_ARMv8 CRYPTO 1483 costs cortex_a73 1484end cpu cortex-a75.cortex-a55 1485 1486begin cpu cortex-a76.cortex-a55 1487 cname cortexa76cortexa55 1488 tune for cortex-a53 1489 tune flags LDSCHED 1490 architecture armv8.2-a+fp16+dotprod 1491 option crypto add FP_ARMv8 CRYPTO 1492 costs cortex_a57 1493end cpu cortex-a76.cortex-a55 1494 1495# Armv8.4 A-profile Architecture Processors 1496begin cpu neoverse-v1 1497 cname neoversev1 1498 tune for cortex-a57 1499 tune flags LDSCHED 1500 architecture armv8.4-a+fp16+bf16+i8mm 1501 option crypto add FP_ARMv8 CRYPTO 1502 costs cortex_a57 1503 vendor 41 1504 part 0xd40 1505end cpu neoverse-v1 1506 1507# Armv8.5 A-profile Architecture Processors 1508begin cpu neoverse-n2 1509 cname neoversen2 1510 tune for cortex-a57 1511 tune flags LDSCHED 1512 architecture armv8.5-a+fp16+bf16+i8mm 1513 option crypto add FP_ARMv8 CRYPTO 1514 costs cortex_a57 1515 vendor 41 1516 part 0xd49 1517end cpu neoverse-n2 1518 1519# V8 M-profile implementations. 1520begin cpu cortex-m23 1521 cname cortexm23 1522 tune flags LDSCHED 1523 architecture armv8-m.base 1524 costs v6m 1525end cpu cortex-m23 1526 1527begin cpu cortex-m33 1528 cname cortexm33 1529 tune flags LDSCHED 1530 architecture armv8-m.main+dsp+fp 1531 option nofp remove ALL_FP 1532 option nodsp remove armv7em 1533 isa quirk_vlldm 1534 costs v7m 1535end cpu cortex-m33 1536 1537begin cpu cortex-m35p 1538 cname cortexm35p 1539 tune flags LDSCHED 1540 architecture armv8-m.main+dsp+fp 1541 option nofp remove ALL_FP 1542 option nodsp remove armv7em 1543 isa quirk_vlldm 1544 costs v7m 1545end cpu cortex-m35p 1546 1547begin cpu cortex-m55 1548 cname cortexm55 1549 tune flags LDSCHED 1550 architecture armv8.1-m.main+mve.fp+fp.dp 1551 option nomve.fp remove mve_float 1552 option nomve remove mve mve_float 1553 option nofp remove ALL_FP mve_float 1554 option nodsp remove MVE mve_float 1555 isa quirk_no_asmcpu quirk_vlldm 1556 costs v7m 1557 vendor 41 1558end cpu cortex-m55 1559 1560# V8 R-profile implementations. 1561begin cpu cortex-r52 1562 cname cortexr52 1563 tune flags LDSCHED 1564 architecture armv8-r+crc+simd 1565 option nofp.dp remove FP_DBL ALL_SIMD 1566 costs cortex 1567 vendor 41 1568 part d13 1569end cpu cortex-r52 1570 1571# FPU entries 1572# format: 1573# begin fpu <name> 1574# isa <isa-flags-list> 1575# end fpu <name> 1576 1577begin fpu vfp 1578 isa VFPv2 FP_DBL 1579end fpu vfp 1580 1581begin fpu vfpv2 1582 isa VFPv2 FP_DBL 1583end fpu vfpv2 1584 1585begin fpu vfpv3 1586 isa VFPv3 FP_D32 1587end fpu vfpv3 1588 1589begin fpu vfpv3-fp16 1590 isa VFPv3 FP_D32 fp16conv 1591end fpu vfpv3-fp16 1592 1593begin fpu vfpv3-d16 1594 isa VFPv3 FP_DBL 1595end fpu vfpv3-d16 1596 1597begin fpu vfpv3-d16-fp16 1598 isa VFPv3 FP_DBL fp16conv 1599end fpu vfpv3-d16-fp16 1600 1601begin fpu vfpv3xd 1602 isa VFPv3 1603end fpu vfpv3xd 1604 1605begin fpu vfpv3xd-fp16 1606 isa VFPv3 fp16conv 1607end fpu vfpv3xd-fp16 1608 1609begin fpu neon 1610 isa VFPv3 NEON 1611end fpu neon 1612 1613begin fpu neon-vfpv3 1614 isa VFPv3 NEON 1615end fpu neon-vfpv3 1616 1617begin fpu neon-fp16 1618 isa VFPv3 NEON fp16conv 1619end fpu neon-fp16 1620 1621begin fpu vfpv4 1622 isa VFPv4 FP_D32 1623end fpu vfpv4 1624 1625begin fpu neon-vfpv4 1626 isa VFPv4 NEON 1627end fpu neon-vfpv4 1628 1629begin fpu vfpv4-d16 1630 isa VFPv4 FP_DBL 1631end fpu vfpv4-d16 1632 1633begin fpu fpv4-sp-d16 1634 isa VFPv4 1635end fpu fpv4-sp-d16 1636 1637begin fpu fpv5-sp-d16 1638 isa FPv5 1639end fpu fpv5-sp-d16 1640 1641begin fpu fpv5-d16 1642 isa FPv5 FP_DBL 1643end fpu fpv5-d16 1644 1645begin fpu fp-armv8 1646 isa FP_ARMv8 1647end fpu fp-armv8 1648 1649begin fpu neon-fp-armv8 1650 isa FP_ARMv8 NEON 1651end fpu neon-fp-armv8 1652 1653begin fpu crypto-neon-fp-armv8 1654 isa FP_ARMv8 CRYPTO 1655end fpu crypto-neon-fp-armv8 1656 1657# Compatibility aliases. 1658begin fpu vfp3 1659 isa VFPv3 FP_D32 1660end fpu vfp3 1661