fpu.md revision 1.5
1;; :::::::::::::::::::: 2;; :: 3;; :: 32-bit floating point arithmetic 4;; :: 5;; :::::::::::::::::::: 6 7;; Addition 8(define_insn "*addsf3_fpu" 9 [(set (match_operand:SF 0 "register_operand" "=r,r, r,r,r,r") 10 (plus:SF (match_operand:SF 1 "nonmemory_operand" "%0,r, r,0,r,F") 11 (match_operand:SF 2 "nonmemory_operand" "r,r,CfZ,F,F,r")))] 12 "TARGET_FP_SP_BASE 13 && (register_operand (operands[1], SFmode) 14 || register_operand (operands[2], SFmode))" 15 "fsadd%?\\t%0,%1,%2" 16 [(set_attr "length" "4,4,4,8,8,8") 17 (set_attr "iscompact" "false") 18 (set_attr "type" "fpu") 19 (set_attr "predicable" "yes,no,no,yes,no,no") 20 (set_attr "cond" "canuse,nocond,nocond,canuse_limm,nocond,nocond") 21 ]) 22 23;; Subtraction 24(define_insn "*subsf3_fpu" 25 [(set (match_operand:SF 0 "register_operand" "=r,r, r,r,r,r") 26 (minus:SF (match_operand:SF 1 "nonmemory_operand" "0,r, r,0,r,F") 27 (match_operand:SF 2 "nonmemory_operand" "r,r,CfZ,F,F,r")))] 28 "TARGET_FP_SP_BASE 29 && (register_operand (operands[1], SFmode) 30 || register_operand (operands[2], SFmode))" 31 "fssub%?\\t%0,%1,%2" 32 [(set_attr "length" "4,4,4,8,8,8") 33 (set_attr "iscompact" "false") 34 (set_attr "type" "fpu") 35 (set_attr "predicable" "yes,no,no,yes,no,no") 36 (set_attr "cond" "canuse,nocond,nocond,canuse_limm,nocond,nocond") 37 ]) 38 39;; Multiplication 40(define_insn "*mulsf3_fpu" 41 [(set (match_operand:SF 0 "register_operand" "=r,r,r,r,r") 42 (mult:SF (match_operand:SF 1 "nonmemory_operand" "%0,r,0,r,F") 43 (match_operand:SF 2 "nonmemory_operand" "r,r,F,F,r")))] 44 "TARGET_FP_SP_BASE 45 && (register_operand (operands[1], SFmode) 46 || register_operand (operands[2], SFmode))" 47 "fsmul%?\\t%0,%1,%2" 48 [(set_attr "length" "4,4,8,8,8") 49 (set_attr "iscompact" "false") 50 (set_attr "type" "fpu") 51 (set_attr "predicable" "yes,no,yes,no,no") 52 (set_attr "cond" "canuse,nocond,canuse_limm,nocond,nocond") 53 ]) 54 55;; Multiplication with addition/subtraction 56(define_expand "fmasf4" 57 [(set (match_operand:SF 0 "register_operand" "") 58 (fma:SF (match_operand:SF 1 "nonmemory_operand" "") 59 (match_operand:SF 2 "nonmemory_operand" "") 60 (match_operand:SF 3 "nonmemory_operand" "")))] 61 "TARGET_FP_SP_FUSED" 62 "{ 63 rtx tmp; 64 tmp = gen_rtx_REG (SFmode, ACCL_REGNO); 65 emit_move_insn (tmp, operands[3]); 66 operands[3] = tmp; 67 if (!register_operand (operands[1], SFmode) 68 && !register_operand (operands[2], SFmode)) 69 operands[2] = force_reg (SFmode, operands[2]); 70 }") 71 72(define_expand "fnmasf4" 73 [(set (match_operand:SF 0 "register_operand" "") 74 (fma:SF (neg:SF (match_operand:SF 1 "nonmemory_operand" "")) 75 (match_operand:SF 2 "nonmemory_operand" "") 76 (match_operand:SF 3 "nonmemory_operand" "")))] 77 "TARGET_FP_SP_FUSED" 78 "{ 79 rtx tmp; 80 tmp = gen_rtx_REG (SFmode, ACCL_REGNO); 81 emit_move_insn (tmp, operands[3]); 82 operands[3] = tmp; 83 if (!register_operand (operands[1], SFmode) 84 && !register_operand (operands[2], SFmode)) 85 operands[2] = force_reg (SFmode, operands[2]); 86}") 87 88(define_insn "fmasf4_fpu" 89 [(set (match_operand:SF 0 "register_operand" "=r,r,r,r,r") 90 (fma:SF (match_operand:SF 1 "nonmemory_operand" "%0,r,0,r,F") 91 (match_operand:SF 2 "nonmemory_operand" "r,r,F,F,r") 92 (match_operand:SF 3 "accl_operand" "")))] 93 "TARGET_FP_SP_FUSED 94 && (register_operand (operands[1], SFmode) 95 || register_operand (operands[2], SFmode))" 96 "fsmadd%? %0,%1,%2" 97 [(set_attr "length" "4,4,8,8,8") 98 (set_attr "predicable" "yes,no,yes,no,no") 99 (set_attr "cond" "canuse,nocond,canuse_limm,nocond,nocond") 100 (set_attr "iscompact" "false") 101 (set_attr "type" "fpu_fuse")]) 102 103(define_insn "fnmasf4_fpu" 104 [(set (match_operand:SF 0 "register_operand" "=r,r,r,r,r") 105 (fma:SF (neg:SF (match_operand:SF 1 "nonmemory_operand" "%0,r,0,r,F")) 106 (match_operand:SF 2 "nonmemory_operand" "r,r,F,F,r") 107 (match_operand:SF 3 "accl_operand" "")))] 108 "TARGET_FP_SP_FUSED 109 && (register_operand (operands[1], SFmode) 110 || register_operand (operands[2], SFmode))" 111 "fsmsub%?\\t%0,%1,%2" 112 [(set_attr "length" "4,4,8,8,8") 113 (set_attr "predicable" "yes,no,yes,no,no") 114 (set_attr "cond" "canuse,nocond,canuse_limm,nocond,nocond") 115 (set_attr "iscompact" "false") 116 (set_attr "type" "fpu_fuse")]) 117 118(define_expand "fmadf4" 119 [(match_operand:DF 0 "even_register_operand" "") 120 (match_operand:DF 1 "even_register_operand" "") 121 (match_operand:DF 2 "even_register_operand" "") 122 (match_operand:DF 3 "even_register_operand" "")] 123 "TARGET_FP_DP_FUSED" 124 "{ 125 emit_insn (gen_fmadf4_split (operands[0], operands[1], operands[2], operands[3])); 126 DONE; 127 }") 128 129(define_insn_and_split "fmadf4_split" 130 [(set (match_operand:DF 0 "even_register_operand" "") 131 (fma:DF (match_operand:DF 1 "even_register_operand" "") 132 (match_operand:DF 2 "even_register_operand" "") 133 (match_operand:DF 3 "even_register_operand" ""))) 134 (clobber (reg:DF ARCV2_ACC))] 135 "TARGET_FP_DP_FUSED" 136 "#" 137 "TARGET_FP_DP_FUSED" 138 [(const_int 0)] 139 "{ 140 rtx acc_reg = gen_rtx_REG (DFmode, ACC_REG_FIRST); 141 emit_move_insn (acc_reg, operands[3]); 142 emit_insn (gen_fmadf4_fpu (operands[0], operands[1], operands[2])); 143 DONE; 144 }" 145) 146 147(define_expand "fnmadf4" 148 [(match_operand:DF 0 "even_register_operand" "") 149 (match_operand:DF 1 "even_register_operand" "") 150 (match_operand:DF 2 "even_register_operand" "") 151 (match_operand:DF 3 "even_register_operand" "")] 152 "TARGET_FP_DP_FUSED" 153 "{ 154 emit_insn (gen_fnmadf4_split (operands[0], operands[1], operands[2], operands[3])); 155 DONE; 156 }") 157 158(define_insn_and_split "fnmadf4_split" 159 [(set (match_operand:DF 0 "even_register_operand" "") 160 (fma:DF (neg:DF (match_operand:DF 1 "even_register_operand" "")) 161 (match_operand:DF 2 "even_register_operand" "") 162 (match_operand:DF 3 "even_register_operand" ""))) 163 (clobber (reg:DF ARCV2_ACC))] 164 "TARGET_FP_DP_FUSED" 165 "#" 166 "TARGET_FP_DP_FUSED" 167 [(const_int 0)] 168 "{ 169 rtx acc_reg = gen_rtx_REG (DFmode, ACC_REG_FIRST); 170 emit_move_insn (acc_reg, operands[3]); 171 emit_insn (gen_fnmadf4_fpu (operands[0], operands[1], operands[2])); 172 DONE; 173 }") 174 175(define_insn "fmadf4_fpu" 176 [(set (match_operand:DF 0 "even_register_operand" "=r,r") 177 (fma:DF (match_operand:DF 1 "even_register_operand" "%0,r") 178 (match_operand:DF 2 "even_register_operand" "r,r") 179 (reg:DF ARCV2_ACC)))] 180 "TARGET_FP_DP_FUSED" 181 "fdmadd%?\\t%0,%1,%2" 182 [(set_attr "length" "4,4") 183 (set_attr "predicable" "yes,no") 184 (set_attr "cond" "canuse,nocond") 185 (set_attr "iscompact" "false") 186 (set_attr "type" "fpu_fuse")]) 187 188(define_insn "fnmadf4_fpu" 189 [(set (match_operand:DF 0 "even_register_operand" "=r,r") 190 (fma:DF (neg:DF (match_operand:DF 1 "even_register_operand" "%0,r")) 191 (match_operand:DF 2 "even_register_operand" "r,r") 192 (reg:DF ARCV2_ACC)))] 193 "TARGET_FP_DP_FUSED" 194 "fdmsub%?\\t%0,%1,%2" 195 [(set_attr "length" "4,4") 196 (set_attr "predicable" "yes,no") 197 (set_attr "cond" "canuse,nocond") 198 (set_attr "iscompact" "false") 199 (set_attr "type" "fpu_fuse")]) 200 201;; Division 202(define_insn "*divsf3_fpu" 203 [(set (match_operand:SF 0 "register_operand" "=r,r,r,r,r") 204 (div:SF (match_operand:SF 1 "nonmemory_operand" "0,r,0,r,F") 205 (match_operand:SF 2 "nonmemory_operand" "r,r,F,F,r")))] 206 "TARGET_FP_SP_SQRT 207 && (register_operand (operands[1], SFmode) 208 || register_operand (operands[2], SFmode))" 209 "fsdiv%?\\t%0,%1,%2" 210 [(set_attr "length" "4,4,8,8,8") 211 (set_attr "iscompact" "false") 212 (set_attr "type" "fpu_sdiv") 213 (set_attr "predicable" "yes,no,yes,no,no") 214 (set_attr "cond" "canuse,nocond,canuse_limm,nocond,nocond") 215 ]) 216 217;; Negation 218;; see pattern in arc.md 219 220;; Absolute value 221;; see pattern in arc.md 222 223;; Square root 224(define_insn "sqrtsf2_fpu" 225 [(set (match_operand:SF 0 "register_operand" "=r,r") 226 (sqrt:SF (match_operand:SF 1 "nonmemory_operand" "r,F")))] 227 "TARGET_FP_SP_SQRT" 228 "fssqrt\\t%0,%1" 229 [(set_attr "length" "4,8") 230 (set_attr "type" "fpu_sdiv")]) 231 232;; Comparison 233(define_insn "*cmpsf_fpu" 234 [(set (reg:CC_FPU CC_REG) 235 (compare:CC_FPU (match_operand:SF 0 "register_operand" "r, r,r") 236 (match_operand:SF 1 "nonmemory_operand" "r,CfZ,F")))] 237 "TARGET_FP_SP_BASE" 238 "fscmp%?\\t%0,%1" 239 [(set_attr "length" "4,4,8") 240 (set_attr "iscompact" "false") 241 (set_attr "cond" "set") 242 (set_attr "type" "fpu") 243 (set_attr "predicable" "yes")]) 244 245(define_insn "*cmpsf_fpu_trap" 246 [(set (reg:CC_FPUE CC_REG) 247 (compare:CC_FPUE (match_operand:SF 0 "register_operand" "r, r,r") 248 (match_operand:SF 1 "nonmemory_operand" "r,CfZ,F")))] 249 "TARGET_FP_SP_BASE" 250 "fscmpf%?\\t%0,%1" 251 [(set_attr "length" "4,4,8") 252 (set_attr "iscompact" "false") 253 (set_attr "cond" "set") 254 (set_attr "type" "fpu") 255 (set_attr "predicable" "yes")]) 256 257(define_insn "*cmpsf_fpu_uneq" 258 [(set (reg:CC_FPU_UNEQ CC_REG) 259 (compare:CC_FPU_UNEQ 260 (match_operand:SF 0 "register_operand" "r, r,r") 261 (match_operand:SF 1 "nonmemory_operand" "r,CfZ,F")))] 262 "TARGET_FP_SP_BASE" 263 "fscmp\\t%0,%1\\n\\tmov.v.f\\t0,0\\t;set Z flag" 264 [(set_attr "length" "8,8,12") 265 (set_attr "iscompact" "false") 266 (set_attr "cond" "set") 267 (set_attr "type" "fpu")]) 268 269;; :::::::::::::::::::: 270;; :: 271;; :: 64-bit floating point arithmetic 272;; :: 273;; :::::::::::::::::::: 274 275;; Addition 276(define_insn "*adddf3_fpu" 277 [(set (match_operand:DF 0 "even_register_operand" "=r,r") 278 (plus:DF (match_operand:DF 1 "even_register_operand" "%0,r") 279 (match_operand:DF 2 "even_register_operand" "r,r")))] 280 "TARGET_FP_DP_BASE" 281 "fdadd%? %0,%1,%2" 282 [(set_attr "length" "4,4") 283 (set_attr "iscompact" "false") 284 (set_attr "type" "fpu") 285 (set_attr "predicable" "yes,no") 286 (set_attr "cond" "canuse,nocond") 287 ]) 288 289;; Subtraction 290(define_insn "*subdf3_fpu" 291 [(set (match_operand:DF 0 "even_register_operand" "=r,r") 292 (minus:DF (match_operand:DF 1 "even_register_operand" "0,r") 293 (match_operand:DF 2 "even_register_operand" "r,r")))] 294 "TARGET_FP_DP_BASE" 295 "fdsub%? %0,%1,%2" 296 [(set_attr "length" "4,4") 297 (set_attr "iscompact" "false") 298 (set_attr "type" "fpu") 299 (set_attr "predicable" "yes,no") 300 (set_attr "cond" "canuse,nocond") 301 ]) 302 303;; Multiplication 304(define_insn "*muldf3_fpu" 305 [(set (match_operand:DF 0 "even_register_operand" "=r,r") 306 (mult:DF (match_operand:DF 1 "even_register_operand" "%0,r") 307 (match_operand:DF 2 "even_register_operand" "r,r")))] 308 "TARGET_FP_DP_BASE" 309 "fdmul%? %0,%1,%2" 310 [(set_attr "length" "4,4") 311 (set_attr "iscompact" "false") 312 (set_attr "type" "fpu") 313 (set_attr "predicable" "yes,no") 314 (set_attr "cond" "canuse,nocond") 315 ]) 316 317;; Division 318(define_insn "divdf3" 319 [(set (match_operand:DF 0 "even_register_operand" "=r,r") 320 (div:DF (match_operand:DF 1 "even_register_operand" "0,r") 321 (match_operand:DF 2 "even_register_operand" "r,r")))] 322 "TARGET_FP_DP_SQRT" 323 "fddiv%? %0,%1,%2" 324 [(set_attr "length" "4,4") 325 (set_attr "iscompact" "false") 326 (set_attr "type" "fpu_ddiv") 327 (set_attr "predicable" "yes,no") 328 (set_attr "cond" "canuse,nocond") 329 ]) 330 331;; Square root 332(define_insn "sqrtdf2" 333 [(set (match_operand:DF 0 "even_register_operand" "=r") 334 (sqrt:DF (match_operand:DF 1 "even_register_operand" "r")))] 335 "TARGET_FP_DP_SQRT" 336 "fdsqrt %0,%1" 337 [(set_attr "length" "4") 338 (set_attr "type" "fpu_ddiv")]) 339 340;; Comparison 341(define_insn "*cmpdf_fpu" 342 [(set (reg:CC_FPU CC_REG) 343 (compare:CC_FPU (match_operand:DF 0 "even_register_operand" "r") 344 (match_operand:DF 1 "even_register_operand" "r")))] 345 "TARGET_FP_DP_BASE" 346 "fdcmp%? %0, %1" 347 [(set_attr "length" "4") 348 (set_attr "iscompact" "false") 349 (set_attr "cond" "set") 350 (set_attr "type" "fpu") 351 (set_attr "predicable" "yes")]) 352 353(define_insn "*cmpdf_fpu_trap" 354 [(set (reg:CC_FPUE CC_REG) 355 (compare:CC_FPUE (match_operand:DF 0 "even_register_operand" "r") 356 (match_operand:DF 1 "even_register_operand" "r")))] 357 "TARGET_FP_DP_BASE" 358 "fdcmpf%? %0, %1" 359 [(set_attr "length" "4") 360 (set_attr "iscompact" "false") 361 (set_attr "cond" "set") 362 (set_attr "type" "fpu") 363 (set_attr "predicable" "yes")]) 364 365(define_insn "*cmpdf_fpu_uneq" 366 [(set (reg:CC_FPU_UNEQ CC_REG) 367 (compare:CC_FPU_UNEQ 368 (match_operand:DF 0 "even_register_operand" "r") 369 (match_operand:DF 1 "even_register_operand" "r")))] 370 "TARGET_FP_DP_BASE" 371 "fdcmp %0, %1\\n\\tmov.v.f 0,0\\t;set Z flag" 372 [(set_attr "length" "8") 373 (set_attr "iscompact" "false") 374 (set_attr "cond" "set") 375 (set_attr "type" "fpu")]) 376 377;; :::::::::::::::::::: 378;; :: 379;; :: Conversion routines 380;; :: 381;; :::::::::::::::::::: 382 383;; SF->DF 384(define_insn "extendsfdf2" 385 [(set (match_operand:DF 0 "even_register_operand" "=r,r") 386 (float_extend:DF (match_operand:SF 1 "register_operand" "0,r")))] 387 "TARGET_FP_DP_CONV" 388 "fcvt32_64%? %0,%1,0x04\\t;fs2d %0,%1" 389 [(set_attr "length" "4,4") 390 (set_attr "iscompact" "false") 391 (set_attr "type" "fpu") 392 (set_attr "predicable" "yes,no")] 393) 394 395;; SI->DF 396(define_insn "floatsidf2" 397 [(set (match_operand:DF 0 "even_register_operand" "=r,r") 398 (float:DF (match_operand:SI 1 "register_operand" "0,r")))] 399 "TARGET_FP_DP_CONV" 400 "fcvt32_64%? %0,%1,0x02\\t;fint2d %0,%1" 401 [(set_attr "length" "4,4") 402 (set_attr "iscompact" "false") 403 (set_attr "type" "fpu") 404 (set_attr "predicable" "yes,no")] 405) 406 407;; uSI->DF 408(define_insn "floatunssidf2" 409 [(set (match_operand:DF 0 "even_register_operand" "=r,r") 410 (unsigned_float:DF (match_operand:SI 1 "register_operand" "0,r")))] 411 "TARGET_FP_DP_CONV" 412 "fcvt32_64%? %0,%1,0x00\\t;fuint2d %0,%1" 413 [(set_attr "length" "4,4") 414 (set_attr "iscompact" "false") 415 (set_attr "type" "fpu") 416 (set_attr "predicable" "yes,no")] 417) 418 419;; SF->uDI (using rounding towards zero) 420(define_insn "fixuns_truncsfdi2" 421 [(set (match_operand:DI 0 "even_register_operand" "=r,r") 422 (unsigned_fix:DI (fix:SF (match_operand:SF 1 "register_operand" "0,r"))))] 423 "TARGET_FP_DP_CONV" 424 "fcvt32_64%? %0,%1,0x09\\t;fs2ul_rz %0,%1" 425 [(set_attr "length" "4,4") 426 (set_attr "iscompact" "false") 427 (set_attr "type" "fpu") 428 (set_attr "predicable" "yes,no")] 429) 430 431;; SF->DI (using rounding towards zero) 432(define_insn "fix_truncsfdi2" 433 [(set (match_operand:DI 0 "even_register_operand" "=r,r") 434 (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "0,r"))))] 435 "TARGET_FP_DP_CONV" 436 "fcvt32_64%? %0,%1,0x0B\\t;fs2l_rz %0,%1" 437 [(set_attr "length" "4,4") 438 (set_attr "iscompact" "false") 439 (set_attr "type" "fpu") 440 (set_attr "predicable" "yes,no")] 441) 442 443;; SI->SF 444(define_insn "floatsisf2_fpu" 445 [(set (match_operand:SF 0 "register_operand" "=r,r") 446 (float:SF (match_operand:SI 1 "register_operand" "0,r")))] 447 "TARGET_FP_SP_CONV" 448 "fcvt32%? %0,%1,0x02\\t;fint2s %0,%1" 449 [(set_attr "length" "4,4") 450 (set_attr "iscompact" "false") 451 (set_attr "type" "fpu") 452 (set_attr "predicable" "yes,no")] 453) 454 455;; uSI->SF 456(define_insn "floatunssisf2" 457 [(set (match_operand:SF 0 "register_operand" "=r,r") 458 (unsigned_float:SF (match_operand:SI 1 "register_operand" "0,r")))] 459 "TARGET_FP_SP_CONV" 460 "fcvt32%? %0,%1,0x00\\t;fuint2s %0,%1" 461 [(set_attr "length" "4,4") 462 (set_attr "iscompact" "false") 463 (set_attr "type" "fpu") 464 (set_attr "predicable" "yes,no")] 465) 466 467;; SF->uSI (using rounding towards zero) 468(define_insn "fixuns_truncsfsi2" 469 [(set (match_operand:SI 0 "register_operand" "=r,r") 470 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "register_operand" "0,r"))))] 471 "TARGET_FP_SP_CONV" 472 "fcvt32%? %0,%1,0x09\\t;fs2uint_rz %0,%1" 473 [(set_attr "length" "4,4") 474 (set_attr "iscompact" "false") 475 (set_attr "type" "fpu") 476 (set_attr "predicable" "yes,no")] 477) 478 479;; SF->SI (using rounding towards zero) 480(define_insn "fix_truncsfsi2_fpu" 481 [(set (match_operand:SI 0 "register_operand" "=r,r") 482 (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "0,r"))))] 483 "TARGET_FP_SP_CONV" 484 "fcvt32%? %0,%1,0x0B\\t;fs2int_rz %0,%1" 485 [(set_attr "length" "4,4") 486 (set_attr "iscompact" "false") 487 (set_attr "type" "fpu") 488 (set_attr "predicable" "yes,no")] 489) 490 491;; DI->DF 492(define_insn "floatdidf2" 493 [(set (match_operand:DF 0 "even_register_operand" "=r,r") 494 (float:DF (match_operand:DI 1 "even_register_operand" "0,r")))] 495 "TARGET_FP_DP_CONV" 496 "fcvt64%? %0,%1,0x02\\t;fl2d %0,%1" 497 [(set_attr "length" "4,4") 498 (set_attr "iscompact" "false") 499 (set_attr "type" "fpu") 500 (set_attr "predicable" "yes,no")] 501) 502 503;; uDI->DF 504(define_insn "floatunsdidf2" 505 [(set (match_operand:DF 0 "even_register_operand" "=r,r") 506 (unsigned_float:DF (match_operand:DI 1 "even_register_operand" "0,r")))] 507 "TARGET_FP_DP_CONV" 508 "fcvt64%? %0,%1,0x00\\t;ful2d %0,%1" 509 [(set_attr "length" "4,4") 510 (set_attr "iscompact" "false") 511 (set_attr "type" "fpu") 512 (set_attr "predicable" "yes,no")] 513) 514 515;; DF->uDI (using rounding towards zero) 516(define_insn "fixuns_truncdfdi2" 517 [(set (match_operand:DI 0 "even_register_operand" "=r,r") 518 (unsigned_fix:DI (fix:DF (match_operand:DF 1 "even_register_operand" "0,r"))))] 519 "TARGET_FP_DP_CONV" 520 "fcvt64%? %0,%1,0x09\\t;fd2ul_rz %0,%1" 521 [(set_attr "length" "4,4") 522 (set_attr "iscompact" "false") 523 (set_attr "type" "fpu") 524 (set_attr "predicable" "yes,no")] 525) 526 527;; DF->DI (using rounding towards zero) 528(define_insn "fix_truncdfdi2" 529 [(set (match_operand:DI 0 "even_register_operand" "=r,r") 530 (fix:DI (fix:DF (match_operand:DF 1 "even_register_operand" "0,r"))))] 531 "TARGET_FP_DP_CONV" 532 "fcvt64%? %0,%1,0x0B\\t;fd2l_rz %0,%1" 533 [(set_attr "length" "4,4") 534 (set_attr "iscompact" "false") 535 (set_attr "type" "fpu") 536 (set_attr "predicable" "yes,no")] 537) 538 539;; DF->SF 540(define_insn "truncdfsf2" 541 [(set (match_operand:SF 0 "register_operand" "=r,r") 542 (float_truncate:SF (match_operand:DF 1 "even_register_operand" "0,r")))] 543 "TARGET_FP_DP_CONV" 544 "fcvt64_32%? %0,%1,0x04\\t;fd2s %0,%1" 545 [(set_attr "length" "4,4") 546 (set_attr "iscompact" "false") 547 (set_attr "type" "fpu") 548 (set_attr "predicable" "yes,no")] 549) 550 551;; DI->SF 552(define_insn "floatdisf2" 553 [(set (match_operand:SF 0 "register_operand" "=r,r") 554 (float:SF (match_operand:DI 1 "even_register_operand" "0,r")))] 555 "TARGET_FP_DP_CONV" 556 "fcvt64_32%? %0,%1,0x02\\t;fl2s %0,%1" 557 [(set_attr "length" "4,4") 558 (set_attr "iscompact" "false") 559 (set_attr "type" "fpu") 560 (set_attr "predicable" "yes,no")] 561) 562 563;; uDI->SF 564(define_insn "floatunsdisf2" 565 [(set (match_operand:SF 0 "register_operand" "=r,r") 566 (unsigned_float:SF (match_operand:DI 1 "even_register_operand" "0,r")))] 567 "TARGET_FP_DP_CONV" 568 "fcvt64_32%? %0,%1,0x00\\t;ful2s %0,%1" 569 [(set_attr "length" "4,4") 570 (set_attr "iscompact" "false") 571 (set_attr "type" "fpu") 572 (set_attr "predicable" "yes,no")] 573) 574 575;; DF->uSI (using rounding towards zero) 576(define_insn "fixuns_truncdfsi2" 577 [(set (match_operand:SI 0 "register_operand" "=r,r") 578 (unsigned_fix:SI (fix:DF (match_operand:DF 1 "even_register_operand" "0,r"))))] 579 "TARGET_FP_DP_CONV" 580 "fcvt64_32%? %0,%1,0x09\\t;fd2uint_rz %0,%1" 581 [(set_attr "length" "4,4") 582 (set_attr "iscompact" "false") 583 (set_attr "type" "fpu") 584 (set_attr "predicable" "yes,no")] 585) 586 587;; DF->SI (using rounding towards zero) 588(define_insn "fix_truncdfsi2" 589 [(set (match_operand:SI 0 "register_operand" "=r,r") 590 (fix:SI (fix:DF (match_operand:DF 1 "even_register_operand" "0,r"))))] 591 "TARGET_FP_DP_CONV" 592 "fcvt64_32%? %0,%1,0x0B\\t;fd2int_rz %0,%1" 593 [(set_attr "length" "4,4") 594 (set_attr "iscompact" "false") 595 (set_attr "type" "fpu") 596 (set_attr "predicable" "yes,no")] 597) 598