fpu.md revision 1.3
1;; :::::::::::::::::::: 2;; :: 3;; :: 32-bit floating point arithmetic 4;; :: 5;; :::::::::::::::::::: 6 7;; Addition 8(define_insn "*addsf3_fpu" 9 [(set (match_operand:SF 0 "register_operand" "=r,r,r,r,r") 10 (plus:SF (match_operand:SF 1 "nonmemory_operand" "%0,r,0,r,F") 11 (match_operand:SF 2 "nonmemory_operand" "r,r,F,F,r")))] 12 "TARGET_FP_SP_BASE 13 && (register_operand (operands[1], SFmode) 14 || register_operand (operands[2], SFmode))" 15 "fsadd%? %0,%1,%2" 16 [(set_attr "length" "4,4,8,8,8") 17 (set_attr "iscompact" "false") 18 (set_attr "type" "fpu") 19 (set_attr "predicable" "yes,no,yes,no,no") 20 (set_attr "cond" "canuse,nocond,canuse_limm,nocond,nocond") 21 ]) 22 23;; Subtraction 24(define_insn "*subsf3_fpu" 25 [(set (match_operand:SF 0 "register_operand" "=r,r,r,r,r") 26 (minus:SF (match_operand:SF 1 "nonmemory_operand" "0,r,0,r,F") 27 (match_operand:SF 2 "nonmemory_operand" "r,r,F,F,r")))] 28 "TARGET_FP_SP_BASE 29 && (register_operand (operands[1], SFmode) 30 || register_operand (operands[2], SFmode))" 31 "fssub%? %0,%1,%2" 32 [(set_attr "length" "4,4,8,8,8") 33 (set_attr "iscompact" "false") 34 (set_attr "type" "fpu") 35 (set_attr "predicable" "yes,no,yes,no,no") 36 (set_attr "cond" "canuse,nocond,canuse_limm,nocond,nocond") 37 ]) 38 39;; Multiplication 40(define_insn "*mulsf3_fpu" 41 [(set (match_operand:SF 0 "register_operand" "=r,r,r,r,r") 42 (mult:SF (match_operand:SF 1 "nonmemory_operand" "%0,r,0,r,F") 43 (match_operand:SF 2 "nonmemory_operand" "r,r,F,F,r")))] 44 "TARGET_FP_SP_BASE 45 && (register_operand (operands[1], SFmode) 46 || register_operand (operands[2], SFmode))" 47 "fsmul%? %0,%1,%2" 48 [(set_attr "length" "4,4,8,8,8") 49 (set_attr "iscompact" "false") 50 (set_attr "type" "fpu") 51 (set_attr "predicable" "yes,no,yes,no,no") 52 (set_attr "cond" "canuse,nocond,canuse_limm,nocond,nocond") 53 ]) 54 55;; Multiplication with addition/subtraction 56(define_expand "fmasf4" 57 [(set (match_operand:SF 0 "register_operand" "") 58 (fma:SF (match_operand:SF 1 "nonmemory_operand" "") 59 (match_operand:SF 2 "nonmemory_operand" "") 60 (match_operand:SF 3 "nonmemory_operand" "")))] 61 "TARGET_FP_SP_FUSED" 62 "{ 63 rtx tmp; 64 tmp = gen_rtx_REG (SFmode, ACCL_REGNO); 65 emit_move_insn (tmp, operands[3]); 66 operands[3] = tmp; 67 }") 68 69(define_expand "fnmasf4" 70 [(set (match_operand:SF 0 "register_operand" "") 71 (fma:SF (neg:SF (match_operand:SF 1 "nonmemory_operand" "")) 72 (match_operand:SF 2 "nonmemory_operand" "") 73 (match_operand:SF 3 "nonmemory_operand" "")))] 74 "TARGET_FP_SP_FUSED" 75 "{ 76 rtx tmp; 77 tmp = gen_rtx_REG (SFmode, ACCL_REGNO); 78 emit_move_insn (tmp, operands[3]); 79 operands[3] = tmp; 80}") 81 82(define_insn "fmasf4_fpu" 83 [(set (match_operand:SF 0 "register_operand" "=r,r,r,r,r") 84 (fma:SF (match_operand:SF 1 "nonmemory_operand" "%0,r,0,r,F") 85 (match_operand:SF 2 "nonmemory_operand" "r,r,F,F,r") 86 (match_operand:SF 3 "mlo_operand" "")))] 87 "TARGET_FP_SP_FUSED 88 && (register_operand (operands[1], SFmode) 89 || register_operand (operands[2], SFmode))" 90 "fsmadd%? %0,%1,%2" 91 [(set_attr "length" "4,4,8,8,8") 92 (set_attr "predicable" "yes,no,yes,no,no") 93 (set_attr "cond" "canuse,nocond,canuse_limm,nocond,nocond") 94 (set_attr "iscompact" "false") 95 (set_attr "type" "fpu")]) 96 97(define_insn "fnmasf4_fpu" 98 [(set (match_operand:SF 0 "register_operand" "=r,r,r,r,r") 99 (fma:SF (neg:SF (match_operand:SF 1 "nonmemory_operand" "%0,r,0,r,F")) 100 (match_operand:SF 2 "nonmemory_operand" "r,r,F,F,r") 101 (match_operand:SF 3 "mlo_operand" "")))] 102 "TARGET_FP_SP_FUSED 103 && (register_operand (operands[1], SFmode) 104 || register_operand (operands[2], SFmode))" 105 "fsmsub%? %0,%1,%2" 106 [(set_attr "length" "4,4,8,8,8") 107 (set_attr "predicable" "yes,no,yes,no,no") 108 (set_attr "cond" "canuse,nocond,canuse_limm,nocond,nocond") 109 (set_attr "iscompact" "false") 110 (set_attr "type" "fpu")]) 111 112(define_expand "fmadf4" 113 [(match_operand:DF 0 "even_register_operand" "") 114 (match_operand:DF 1 "even_register_operand" "") 115 (match_operand:DF 2 "even_register_operand" "") 116 (match_operand:DF 3 "even_register_operand" "")] 117 "TARGET_FP_DP_FUSED" 118 "{ 119 emit_insn (gen_fmadf4_split (operands[0], operands[1], operands[2], operands[3])); 120 DONE; 121 }") 122 123(define_insn_and_split "fmadf4_split" 124 [(set (match_operand:DF 0 "even_register_operand" "") 125 (fma:DF (match_operand:DF 1 "even_register_operand" "") 126 (match_operand:DF 2 "even_register_operand" "") 127 (match_operand:DF 3 "even_register_operand" ""))) 128 (clobber (reg:DF ARCV2_ACC))] 129 "TARGET_FP_DP_FUSED" 130 "#" 131 "TARGET_FP_DP_FUSED" 132 [(const_int 0)] 133 "{ 134 rtx acc_reg = gen_rtx_REG (DFmode, ACC_REG_FIRST); 135 emit_move_insn (acc_reg, operands[3]); 136 emit_insn (gen_fmadf4_fpu (operands[0], operands[1], operands[2])); 137 DONE; 138 }" 139) 140 141(define_expand "fnmadf4" 142 [(match_operand:DF 0 "even_register_operand" "") 143 (match_operand:DF 1 "even_register_operand" "") 144 (match_operand:DF 2 "even_register_operand" "") 145 (match_operand:DF 3 "even_register_operand" "")] 146 "TARGET_FP_DP_FUSED" 147 "{ 148 emit_insn (gen_fnmadf4_split (operands[0], operands[1], operands[2], operands[3])); 149 DONE; 150 }") 151 152(define_insn_and_split "fnmadf4_split" 153 [(set (match_operand:DF 0 "even_register_operand" "") 154 (fma:DF (neg:DF (match_operand:DF 1 "even_register_operand" "")) 155 (match_operand:DF 2 "even_register_operand" "") 156 (match_operand:DF 3 "even_register_operand" ""))) 157 (clobber (reg:DF ARCV2_ACC))] 158 "TARGET_FP_DP_FUSED" 159 "#" 160 "TARGET_FP_DP_FUSED" 161 [(const_int 0)] 162 "{ 163 rtx acc_reg = gen_rtx_REG (DFmode, ACC_REG_FIRST); 164 emit_move_insn (acc_reg, operands[3]); 165 emit_insn (gen_fnmadf4_fpu (operands[0], operands[1], operands[2])); 166 DONE; 167 }") 168 169(define_insn "fmadf4_fpu" 170 [(set (match_operand:DF 0 "even_register_operand" "=r,r") 171 (fma:DF (match_operand:DF 1 "even_register_operand" "%0,r") 172 (match_operand:DF 2 "even_register_operand" "r,r") 173 (reg:DF ARCV2_ACC)))] 174 "TARGET_FP_DP_FUSED" 175 "fdmadd%? %0,%1,%2" 176 [(set_attr "length" "4,4") 177 (set_attr "predicable" "yes,no") 178 (set_attr "cond" "canuse,nocond") 179 (set_attr "iscompact" "false") 180 (set_attr "type" "fpu")]) 181 182(define_insn "fnmadf4_fpu" 183 [(set (match_operand:DF 0 "even_register_operand" "=r,r") 184 (fma:DF (neg:DF (match_operand:DF 1 "even_register_operand" "%0,r")) 185 (match_operand:DF 2 "even_register_operand" "r,r") 186 (reg:DF ARCV2_ACC)))] 187 "TARGET_FP_DP_FUSED" 188 "fdmsub%? %0,%1,%2" 189 [(set_attr "length" "4,4") 190 (set_attr "predicable" "yes,no") 191 (set_attr "cond" "canuse,nocond") 192 (set_attr "iscompact" "false") 193 (set_attr "type" "fpu")]) 194 195;; Division 196(define_insn "*divsf3_fpu" 197 [(set (match_operand:SF 0 "register_operand" "=r,r,r,r,r") 198 (div:SF (match_operand:SF 1 "nonmemory_operand" "0,r,0,r,F") 199 (match_operand:SF 2 "nonmemory_operand" "r,r,F,F,r")))] 200 "TARGET_FP_SP_SQRT 201 && (register_operand (operands[1], SFmode) 202 || register_operand (operands[2], SFmode))" 203 "fsdiv%? %0,%1,%2" 204 [(set_attr "length" "4,4,8,8,8") 205 (set_attr "iscompact" "false") 206 (set_attr "type" "fpu") 207 (set_attr "predicable" "yes,no,yes,no,no") 208 (set_attr "cond" "canuse,nocond,canuse_limm,nocond,nocond") 209 ]) 210 211;; Negation 212;; see pattern in arc.md 213 214;; Absolute value 215;; see pattern in arc.md 216 217;; Square root 218(define_insn "sqrtsf2_fpu" 219 [(set (match_operand:SF 0 "register_operand" "=r,r") 220 (sqrt:SF (match_operand:SF 1 "nonmemory_operand" "r,F")))] 221 "TARGET_FP_SP_SQRT" 222 "fssqrt %0,%1" 223 [(set_attr "length" "4,8") 224 (set_attr "type" "fpu")]) 225 226;; Comparison 227(define_insn "*cmpsf_fpu" 228 [(set (reg:CC_FPU CC_REG) 229 (compare:CC_FPU (match_operand:SF 0 "register_operand" "r,r") 230 (match_operand:SF 1 "nonmemory_operand" "r,F")))] 231 "TARGET_FP_SP_BASE" 232 "fscmp%? %0, %1" 233 [(set_attr "length" "4,8") 234 (set_attr "iscompact" "false") 235 (set_attr "cond" "set") 236 (set_attr "type" "fpu") 237 (set_attr "predicable" "yes,yes")]) 238 239(define_insn "*cmpsf_fpu_uneq" 240 [(set (reg:CC_FPU_UNEQ CC_REG) 241 (compare:CC_FPU_UNEQ 242 (match_operand:SF 0 "register_operand" "r,r") 243 (match_operand:SF 1 "nonmemory_operand" "r,F")))] 244 "TARGET_FP_SP_BASE" 245 "fscmp %0, %1\\n\\tmov.v.f 0,0\\t;set Z flag" 246 [(set_attr "length" "8,12") 247 (set_attr "iscompact" "false") 248 (set_attr "cond" "set") 249 (set_attr "type" "fpu")]) 250 251;; :::::::::::::::::::: 252;; :: 253;; :: 64-bit floating point arithmetic 254;; :: 255;; :::::::::::::::::::: 256 257;; Addition 258(define_insn "*adddf3_fpu" 259 [(set (match_operand:DF 0 "even_register_operand" "=r,r") 260 (plus:DF (match_operand:DF 1 "even_register_operand" "%0,r") 261 (match_operand:DF 2 "even_register_operand" "r,r")))] 262 "TARGET_FP_DP_BASE" 263 "fdadd%? %0,%1,%2" 264 [(set_attr "length" "4,4") 265 (set_attr "iscompact" "false") 266 (set_attr "type" "fpu") 267 (set_attr "predicable" "yes,no") 268 (set_attr "cond" "canuse,nocond") 269 ]) 270 271 272;; Subtraction 273(define_insn "*subdf3_fpu" 274 [(set (match_operand:DF 0 "even_register_operand" "=r,r") 275 (minus:DF (match_operand:DF 1 "even_register_operand" "0,r") 276 (match_operand:DF 2 "even_register_operand" "r,r")))] 277 "TARGET_FP_DP_BASE" 278 "fdsub%? %0,%1,%2" 279 [(set_attr "length" "4,4") 280 (set_attr "iscompact" "false") 281 (set_attr "type" "fpu") 282 (set_attr "predicable" "yes,no") 283 (set_attr "cond" "canuse,nocond") 284 ]) 285 286;; Multiplication 287(define_insn "*muldf3_fpu" 288 [(set (match_operand:DF 0 "even_register_operand" "=r,r") 289 (mult:DF (match_operand:DF 1 "even_register_operand" "%0,r") 290 (match_operand:DF 2 "even_register_operand" "r,r")))] 291 "TARGET_FP_DP_BASE" 292 "fdmul%? %0,%1,%2" 293 [(set_attr "length" "4,4") 294 (set_attr "iscompact" "false") 295 (set_attr "type" "fpu") 296 (set_attr "predicable" "yes,no") 297 (set_attr "cond" "canuse,nocond") 298 ]) 299 300;; Division 301(define_insn "divdf3" 302 [(set (match_operand:DF 0 "even_register_operand" "=r,r") 303 (div:DF (match_operand:DF 1 "even_register_operand" "0,r") 304 (match_operand:DF 2 "even_register_operand" "r,r")))] 305 "TARGET_FP_DP_SQRT" 306 "fddiv%? %0,%1,%2" 307 [(set_attr "length" "4,4") 308 (set_attr "iscompact" "false") 309 (set_attr "type" "fpu") 310 (set_attr "predicable" "yes,no") 311 (set_attr "cond" "canuse,nocond") 312 ]) 313 314;; Square root 315(define_insn "sqrtdf2" 316 [(set (match_operand:DF 0 "even_register_operand" "=r") 317 (sqrt:DF (match_operand:DF 1 "even_register_operand" "r")))] 318 "TARGET_FP_DP_SQRT" 319 "fdsqrt %0,%1" 320 [(set_attr "length" "4") 321 (set_attr "type" "fpu")]) 322 323;; Comparison 324(define_insn "*cmpdf_fpu" 325 [(set (reg:CC_FPU CC_REG) 326 (compare:CC_FPU (match_operand:DF 0 "even_register_operand" "r") 327 (match_operand:DF 1 "even_register_operand" "r")))] 328 "TARGET_FP_DP_BASE" 329 "fdcmp%? %0, %1" 330 [(set_attr "length" "4") 331 (set_attr "iscompact" "false") 332 (set_attr "cond" "set") 333 (set_attr "type" "fpu") 334 (set_attr "predicable" "yes")]) 335 336(define_insn "*cmpdf_fpu_uneq" 337 [(set (reg:CC_FPU_UNEQ CC_REG) 338 (compare:CC_FPU_UNEQ 339 (match_operand:DF 0 "even_register_operand" "r") 340 (match_operand:DF 1 "even_register_operand" "r")))] 341 "TARGET_FP_DP_BASE" 342 "fdcmp %0, %1\\n\\tmov.v.f 0,0\\t;set Z flag" 343 [(set_attr "length" "8") 344 (set_attr "iscompact" "false") 345 (set_attr "cond" "set") 346 (set_attr "type" "fpu")]) 347 348;; :::::::::::::::::::: 349;; :: 350;; :: Conversion routines 351;; :: 352;; :::::::::::::::::::: 353 354;; SF->DF 355(define_insn "extendsfdf2" 356 [(set (match_operand:DF 0 "even_register_operand" "=r,r") 357 (float_extend:DF (match_operand:SF 1 "register_operand" "0,r")))] 358 "TARGET_FP_DP_CONV" 359 "fcvt32_64%? %0,%1,0x04\\t;fs2d %0,%1" 360 [(set_attr "length" "4,4") 361 (set_attr "iscompact" "false") 362 (set_attr "type" "fpu") 363 (set_attr "predicable" "yes,no")] 364) 365 366;; SI->DF 367(define_insn "floatsidf2" 368 [(set (match_operand:DF 0 "even_register_operand" "=r,r") 369 (float:DF (match_operand:SI 1 "register_operand" "0,r")))] 370 "TARGET_FP_DP_CONV" 371 "fcvt32_64%? %0,%1,0x02\\t;fint2d %0,%1" 372 [(set_attr "length" "4,4") 373 (set_attr "iscompact" "false") 374 (set_attr "type" "fpu") 375 (set_attr "predicable" "yes,no")] 376) 377 378;; uSI->DF 379(define_insn "floatunssidf2" 380 [(set (match_operand:DF 0 "even_register_operand" "=r,r") 381 (unsigned_float:DF (match_operand:SI 1 "register_operand" "0,r")))] 382 "TARGET_FP_DP_CONV" 383 "fcvt32_64%? %0,%1,0x00\\t;fuint2d %0,%1" 384 [(set_attr "length" "4,4") 385 (set_attr "iscompact" "false") 386 (set_attr "type" "fpu") 387 (set_attr "predicable" "yes,no")] 388) 389 390;; SF->uDI (using rounding towards zero) 391(define_insn "fixuns_truncsfdi2" 392 [(set (match_operand:DI 0 "even_register_operand" "=r,r") 393 (unsigned_fix:DI (fix:SF (match_operand:SF 1 "register_operand" "0,r"))))] 394 "TARGET_FP_DP_CONV" 395 "fcvt32_64%? %0,%1,0x09\\t;fs2ul_rz %0,%1" 396 [(set_attr "length" "4,4") 397 (set_attr "iscompact" "false") 398 (set_attr "type" "fpu") 399 (set_attr "predicable" "yes,no")] 400) 401 402;; SF->DI (using rounding towards zero) 403(define_insn "fix_truncsfdi2" 404 [(set (match_operand:DI 0 "even_register_operand" "=r,r") 405 (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "0,r"))))] 406 "TARGET_FP_DP_CONV" 407 "fcvt32_64%? %0,%1,0x0B\\t;fs2l_rz %0,%1" 408 [(set_attr "length" "4,4") 409 (set_attr "iscompact" "false") 410 (set_attr "type" "fpu") 411 (set_attr "predicable" "yes,no")] 412) 413 414;; SI->SF 415(define_insn "floatsisf2_fpu" 416 [(set (match_operand:SF 0 "register_operand" "=r,r") 417 (float:SF (match_operand:SI 1 "register_operand" "0,r")))] 418 "TARGET_FP_SP_CONV" 419 "fcvt32%? %0,%1,0x02\\t;fint2s %0,%1" 420 [(set_attr "length" "4,4") 421 (set_attr "iscompact" "false") 422 (set_attr "type" "fpu") 423 (set_attr "predicable" "yes,no")] 424) 425 426;; uSI->SF 427(define_insn "floatunssisf2" 428 [(set (match_operand:SF 0 "register_operand" "=r,r") 429 (unsigned_float:SF (match_operand:SI 1 "register_operand" "0,r")))] 430 "TARGET_FP_SP_CONV" 431 "fcvt32%? %0,%1,0x00\\t;fuint2s %0,%1" 432 [(set_attr "length" "4,4") 433 (set_attr "iscompact" "false") 434 (set_attr "type" "fpu") 435 (set_attr "predicable" "yes,no")] 436) 437 438;; SF->uSI (using rounding towards zero) 439(define_insn "fixuns_truncsfsi2" 440 [(set (match_operand:SI 0 "register_operand" "=r,r") 441 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "register_operand" "0,r"))))] 442 "TARGET_FP_SP_CONV" 443 "fcvt32%? %0,%1,0x09\\t;fs2uint_rz %0,%1" 444 [(set_attr "length" "4,4") 445 (set_attr "iscompact" "false") 446 (set_attr "type" "fpu") 447 (set_attr "predicable" "yes,no")] 448) 449 450;; SF->SI (using rounding towards zero) 451(define_insn "fix_truncsfsi2_fpu" 452 [(set (match_operand:SI 0 "register_operand" "=r,r") 453 (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "0,r"))))] 454 "TARGET_FP_SP_CONV" 455 "fcvt32%? %0,%1,0x0B\\t;fs2int_rz %0,%1" 456 [(set_attr "length" "4,4") 457 (set_attr "iscompact" "false") 458 (set_attr "type" "fpu") 459 (set_attr "predicable" "yes,no")] 460) 461 462;; DI->DF 463(define_insn "floatdidf2" 464 [(set (match_operand:DF 0 "even_register_operand" "=r,r") 465 (float:DF (match_operand:DI 1 "even_register_operand" "0,r")))] 466 "TARGET_FP_DP_CONV" 467 "fcvt64%? %0,%1,0x02\\t;fl2d %0,%1" 468 [(set_attr "length" "4,4") 469 (set_attr "iscompact" "false") 470 (set_attr "type" "fpu") 471 (set_attr "predicable" "yes,no")] 472) 473 474;; uDI->DF 475(define_insn "floatunsdidf2" 476 [(set (match_operand:DF 0 "even_register_operand" "=r,r") 477 (unsigned_float:DF (match_operand:DI 1 "even_register_operand" "0,r")))] 478 "TARGET_FP_DP_CONV" 479 "fcvt64%? %0,%1,0x00\\t;ful2d %0,%1" 480 [(set_attr "length" "4,4") 481 (set_attr "iscompact" "false") 482 (set_attr "type" "fpu") 483 (set_attr "predicable" "yes,no")] 484) 485 486;; DF->uDI (using rounding towards zero) 487(define_insn "fixuns_truncdfdi2" 488 [(set (match_operand:DI 0 "even_register_operand" "=r,r") 489 (unsigned_fix:DI (fix:DF (match_operand:DF 1 "even_register_operand" "0,r"))))] 490 "TARGET_FP_DP_CONV" 491 "fcvt64%? %0,%1,0x09\\t;fd2ul_rz %0,%1" 492 [(set_attr "length" "4,4") 493 (set_attr "iscompact" "false") 494 (set_attr "type" "fpu") 495 (set_attr "predicable" "yes,no")] 496) 497 498;; DF->DI (using rounding towards zero) 499(define_insn "fix_truncdfdi2" 500 [(set (match_operand:DI 0 "even_register_operand" "=r,r") 501 (fix:DI (fix:DF (match_operand:DF 1 "even_register_operand" "0,r"))))] 502 "TARGET_FP_DP_CONV" 503 "fcvt64%? %0,%1,0x0B\\t;fd2l_rz %0,%1" 504 [(set_attr "length" "4,4") 505 (set_attr "iscompact" "false") 506 (set_attr "type" "fpu") 507 (set_attr "predicable" "yes,no")] 508) 509 510;; DF->SF 511(define_insn "truncdfsf2" 512 [(set (match_operand:SF 0 "register_operand" "=r,r") 513 (float_truncate:SF (match_operand:DF 1 "even_register_operand" "0,r")))] 514 "TARGET_FP_DP_CONV" 515 "fcvt64_32%? %0,%1,0x04\\t;fd2s %0,%1" 516 [(set_attr "length" "4,4") 517 (set_attr "iscompact" "false") 518 (set_attr "type" "fpu") 519 (set_attr "predicable" "yes,no")] 520) 521 522;; DI->SF 523(define_insn "floatdisf2" 524 [(set (match_operand:SF 0 "register_operand" "=r,r") 525 (float:SF (match_operand:DI 1 "even_register_operand" "0,r")))] 526 "TARGET_FP_DP_CONV" 527 "fcvt64_32%? %0,%1,0x02\\t;fl2s %0,%1" 528 [(set_attr "length" "4,4") 529 (set_attr "iscompact" "false") 530 (set_attr "type" "fpu") 531 (set_attr "predicable" "yes,no")] 532) 533 534;; uDI->SF 535(define_insn "floatunsdisf2" 536 [(set (match_operand:SF 0 "register_operand" "=r,r") 537 (unsigned_float:SF (match_operand:DI 1 "even_register_operand" "0,r")))] 538 "TARGET_FP_DP_CONV" 539 "fcvt64_32%? %0,%1,0x00\\t;ful2s %0,%1" 540 [(set_attr "length" "4,4") 541 (set_attr "iscompact" "false") 542 (set_attr "type" "fpu") 543 (set_attr "predicable" "yes,no")] 544) 545 546;; DF->uSI (using rounding towards zero) 547(define_insn "fixuns_truncdfsi2" 548 [(set (match_operand:SI 0 "register_operand" "=r,r") 549 (unsigned_fix:SI (fix:DF (match_operand:DF 1 "even_register_operand" "0,r"))))] 550 "TARGET_FP_DP_CONV" 551 "fcvt64_32%? %0,%1,0x09\\t;fd2uint_rz %0,%1" 552 [(set_attr "length" "4,4") 553 (set_attr "iscompact" "false") 554 (set_attr "type" "fpu") 555 (set_attr "predicable" "yes,no")] 556) 557 558;; DF->SI (using rounding towards zero) 559(define_insn "fix_truncdfsi2" 560 [(set (match_operand:SI 0 "register_operand" "=r,r") 561 (fix:SI (fix:DF (match_operand:DF 1 "even_register_operand" "0,r"))))] 562 "TARGET_FP_DP_CONV" 563 "fcvt64_32%? %0,%1,0x0B\\t;fd2int_rz %0,%1" 564 [(set_attr "length" "4,4") 565 (set_attr "iscompact" "false") 566 (set_attr "type" "fpu") 567 (set_attr "predicable" "yes,no")] 568) 569