1;; DFA scheduling description of the Synopsys DesignWare ARC HS cpu
2;; for GNU C compiler
3;; Copyright (C) 2007-2020 Free Software Foundation, Inc.
4;; Contributor: Claudiu Zissulescu <claudiu.zissulescu@synopsys.com>
5
6;; This file is part of GCC.
7
8;; GCC is free software; you can redistribute it and/or modify
9;; it under the terms of the GNU General Public License as published by
10;; the Free Software Foundation; either version 3, or (at your option)
11;; any later version.
12
13;; GCC is distributed in the hope that it will be useful,
14;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16;; GNU General Public License for more details.
17
18;; You should have received a copy of the GNU General Public License
19;; along with GCC; see the file COPYING3.  If not see
20;; <http://www.gnu.org/licenses/>.
21
22(define_automaton "ARCHS")
23
24(define_cpu_unit "hs_issue, hs_ld_st, divrem_hs, mul_hs, x1, x2" "ARCHS")
25
26(define_insn_reservation "hs_data_load" 4
27  (and (match_test "TARGET_HS")
28       (eq_attr "tune" "none")
29       (eq_attr "type" "load"))
30  "hs_issue+hs_ld_st,hs_ld_st,nothing*2")
31
32(define_insn_reservation "hs_data_store" 1
33  (and (match_test "TARGET_HS")
34       (eq_attr "tune" "none")
35       (eq_attr "type" "store"))
36  "hs_issue+hs_ld_st")
37
38;; Advanced ALU
39(define_insn_reservation "hs_alu0" 4
40  (and (match_test "TARGET_HS")
41       (eq_attr "tune" "none")
42       (eq_attr "type" "cc_arith, two_cycle_core, shift, lr, sr"))
43  "hs_issue+x1,x2, nothing*2")
44
45;; Basic ALU
46(define_insn_reservation "hs_alu1" 4
47  (and (match_test "TARGET_HS")
48       (eq_attr "tune" "none")
49       (eq_attr "type" "move, cmove, unary, binary, compare, misc"))
50  "hs_issue+x1, nothing*3")
51
52(define_insn_reservation "hs_divrem" 13
53  (and (match_test "TARGET_HS")
54       (match_test "TARGET_DIVREM")
55       (eq_attr "tune" "none")
56       (eq_attr "type" "div_rem"))
57  "hs_issue+divrem_hs, (divrem_hs)*12")
58
59(define_insn_reservation "hs_mul" 4
60  (and (match_test "TARGET_HS")
61       (eq_attr "tune" "none")
62       (eq_attr "type" "mul16_em, multi, umulti"))
63  "hs_issue+mul_hs, nothing*3")
64
65;; BYPASS Advanced ALU ->
66(define_bypass 1 "hs_alu0" "hs_divrem")
67(define_bypass 1 "hs_alu0" "hs_mul")
68(define_bypass 2 "hs_alu0" "hs_alu0")
69(define_bypass 1 "hs_alu0" "hs_alu1")
70(define_bypass 1 "hs_alu0" "hs_data_load")
71(define_bypass 1 "hs_alu0" "hs_data_store" "store_data_bypass_p")
72(define_bypass 2 "hs_alu0" "hs_data_store")
73
74;; BYPASS Basic ALU ->
75(define_bypass 1 "hs_alu1" "hs_alu1")
76(define_bypass 1 "hs_alu1" "hs_data_store" "store_data_bypass_p")
77(define_bypass 3 "hs_alu1" "hs_mul")
78(define_bypass 3 "hs_alu1" "hs_divrem")
79
80;; BYPASS LD ->
81(define_bypass 1 "hs_data_load" "hs_alu1")
82(define_bypass 3 "hs_data_load" "hs_divrem")
83(define_bypass 3 "hs_data_load" "hs_data_load")
84(define_bypass 3 "hs_data_load" "hs_mul")
85(define_bypass 1 "hs_data_load" "hs_data_store" "store_data_bypass_p")
86
87;; BYPASS MPY ->
88(define_bypass 3 "hs_mul" "hs_mul")
89(define_bypass 1 "hs_mul" "hs_alu1")
90(define_bypass 3 "hs_mul" "hs_divrem")
91(define_bypass 1 "hs_mul" "hs_data_store" "store_data_bypass_p")
92