1;; Machine description for AArch64 architecture. 2;; Copyright (C) 2009-2020 Free Software Foundation, Inc. 3;; Contributed by ARM Ltd. 4;; 5;; This file is part of GCC. 6;; 7;; GCC is free software; you can redistribute it and/or modify it 8;; under the terms of the GNU General Public License as published by 9;; the Free Software Foundation; either version 3, or (at your option) 10;; any later version. 11;; 12;; GCC is distributed in the hope that it will be useful, but 13;; WITHOUT ANY WARRANTY; without even the implied warranty of 14;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15;; General Public License for more details. 16;; 17;; You should have received a copy of the GNU General Public License 18;; along with GCC; see the file COPYING3. If not see 19;; <http://www.gnu.org/licenses/>. 20 21(define_special_predicate "cc_register" 22 (and (match_code "reg") 23 (and (match_test "REGNO (op) == CC_REGNUM") 24 (ior (match_test "mode == GET_MODE (op)") 25 (match_test "mode == VOIDmode 26 && GET_MODE_CLASS (GET_MODE (op)) == MODE_CC")))) 27) 28 29(define_predicate "aarch64_call_insn_operand" 30 (ior (match_code "symbol_ref") 31 (match_operand 0 "register_operand"))) 32 33(define_predicate "aarch64_general_reg" 34 (and (match_operand 0 "register_operand") 35 (match_test "REGNO_REG_CLASS (REGNO (op)) == STUB_REGS 36 || REGNO_REG_CLASS (REGNO (op)) == GENERAL_REGS"))) 37 38;; Return true if OP a (const_int 0) operand. 39(define_predicate "const0_operand" 40 (and (match_code "const_int") 41 (match_test "op == CONST0_RTX (mode)"))) 42 43(define_predicate "const_1_to_3_operand" 44 (match_code "const_int,const_vector") 45{ 46 op = unwrap_const_vec_duplicate (op); 47 return CONST_INT_P (op) && IN_RANGE (INTVAL (op), 1, 3); 48}) 49 50(define_predicate "subreg_lowpart_operator" 51 (ior (match_code "truncate") 52 (and (match_code "subreg") 53 (match_test "subreg_lowpart_p (op)")))) 54 55(define_predicate "aarch64_ccmp_immediate" 56 (and (match_code "const_int") 57 (match_test "IN_RANGE (INTVAL (op), -31, 31)"))) 58 59(define_predicate "aarch64_ccmp_operand" 60 (ior (match_operand 0 "register_operand") 61 (match_operand 0 "aarch64_ccmp_immediate"))) 62 63(define_predicate "aarch64_simd_register" 64 (and (match_code "reg") 65 (match_test "FP_REGNUM_P (REGNO (op))"))) 66 67(define_predicate "aarch64_reg_or_zero" 68 (and (match_code "reg,subreg,const_int,const_double") 69 (ior (match_operand 0 "register_operand") 70 (match_test "op == CONST0_RTX (GET_MODE (op))")))) 71 72(define_predicate "aarch64_reg_or_fp_zero" 73 (ior (match_operand 0 "register_operand") 74 (and (match_code "const_double") 75 (match_test "aarch64_float_const_zero_rtx_p (op)")))) 76 77(define_predicate "aarch64_reg_zero_or_fp_zero" 78 (ior (match_operand 0 "aarch64_reg_or_fp_zero") 79 (match_operand 0 "aarch64_reg_or_zero"))) 80 81(define_predicate "aarch64_reg_zero_or_m1_or_1" 82 (and (match_code "reg,subreg,const_int") 83 (ior (match_operand 0 "register_operand") 84 (ior (match_test "op == const0_rtx") 85 (ior (match_test "op == constm1_rtx") 86 (match_test "op == const1_rtx")))))) 87 88(define_predicate "aarch64_reg_or_orr_imm" 89 (ior (match_operand 0 "register_operand") 90 (and (match_code "const_vector") 91 (match_test "aarch64_simd_valid_immediate (op, NULL, 92 AARCH64_CHECK_ORR)")))) 93 94(define_predicate "aarch64_reg_or_bic_imm" 95 (ior (match_operand 0 "register_operand") 96 (and (match_code "const_vector") 97 (match_test "aarch64_simd_valid_immediate (op, NULL, 98 AARCH64_CHECK_BIC)")))) 99 100(define_predicate "aarch64_fp_compare_operand" 101 (ior (match_operand 0 "register_operand") 102 (and (match_code "const_double") 103 (match_test "aarch64_float_const_zero_rtx_p (op)")))) 104 105(define_predicate "aarch64_fp_pow2" 106 (and (match_code "const_double") 107 (match_test "aarch64_fpconst_pow_of_2 (op) > 0"))) 108 109(define_predicate "aarch64_fp_pow2_recip" 110 (and (match_code "const_double") 111 (match_test "aarch64_fpconst_pow2_recip (op) > 0"))) 112 113(define_predicate "aarch64_fp_vec_pow2" 114 (match_test "aarch64_vec_fpconst_pow_of_2 (op) > 0")) 115 116(define_predicate "aarch64_sve_cnt_immediate" 117 (and (match_code "const_poly_int") 118 (match_test "aarch64_sve_cnt_immediate_p (op)"))) 119 120(define_predicate "aarch64_sub_immediate" 121 (and (match_code "const_int") 122 (match_test "aarch64_uimm12_shift (-INTVAL (op))"))) 123 124(define_predicate "aarch64_plus_immediate" 125 (and (match_code "const_int") 126 (ior (match_test "aarch64_uimm12_shift (INTVAL (op))") 127 (match_test "aarch64_uimm12_shift (-INTVAL (op))")))) 128 129(define_predicate "aarch64_plus_operand" 130 (ior (match_operand 0 "register_operand") 131 (match_operand 0 "aarch64_plus_immediate"))) 132 133(define_predicate "aarch64_plushi_immediate" 134 (match_code "const_int") 135{ 136 HOST_WIDE_INT val = INTVAL (op); 137 /* The HImode value must be zero-extendable to an SImode plus_operand. */ 138 return ((val & 0xfff) == val || sext_hwi (val & 0xf000, 16) == val); 139}) 140 141(define_predicate "aarch64_plushi_operand" 142 (ior (match_operand 0 "register_operand") 143 (match_operand 0 "aarch64_plushi_immediate"))) 144 145(define_predicate "aarch64_pluslong_immediate" 146 (and (match_code "const_int") 147 (match_test "(INTVAL (op) < 0xffffff && INTVAL (op) > -0xffffff)"))) 148 149(define_predicate "aarch64_pluslong_strict_immedate" 150 (and (match_operand 0 "aarch64_pluslong_immediate") 151 (not (match_operand 0 "aarch64_plus_immediate")))) 152 153(define_predicate "aarch64_sve_scalar_inc_dec_immediate" 154 (and (match_code "const_poly_int") 155 (match_test "aarch64_sve_scalar_inc_dec_immediate_p (op)"))) 156 157(define_predicate "aarch64_sve_addvl_addpl_immediate" 158 (and (match_code "const_poly_int") 159 (match_test "aarch64_sve_addvl_addpl_immediate_p (op)"))) 160 161(define_predicate "aarch64_sve_plus_immediate" 162 (ior (match_operand 0 "aarch64_sve_scalar_inc_dec_immediate") 163 (match_operand 0 "aarch64_sve_addvl_addpl_immediate"))) 164 165(define_predicate "aarch64_split_add_offset_immediate" 166 (and (match_code "const_poly_int") 167 (match_test "aarch64_add_offset_temporaries (op) == 1"))) 168 169(define_predicate "aarch64_pluslong_operand" 170 (ior (match_operand 0 "register_operand") 171 (match_operand 0 "aarch64_pluslong_immediate") 172 (and (match_test "TARGET_SVE") 173 (match_operand 0 "aarch64_sve_plus_immediate")))) 174 175(define_predicate "aarch64_pluslong_or_poly_operand" 176 (ior (match_operand 0 "aarch64_pluslong_operand") 177 (match_operand 0 "aarch64_split_add_offset_immediate"))) 178 179(define_predicate "aarch64_logical_immediate" 180 (and (match_code "const_int") 181 (match_test "aarch64_bitmask_imm (INTVAL (op), mode)"))) 182 183(define_predicate "aarch64_logical_operand" 184 (ior (match_operand 0 "register_operand") 185 (match_operand 0 "aarch64_logical_immediate"))) 186 187(define_predicate "aarch64_mov_imm_operand" 188 (and (match_code "const_int") 189 (match_test "aarch64_move_imm (INTVAL (op), mode)"))) 190 191(define_predicate "aarch64_logical_and_immediate" 192 (and (match_code "const_int") 193 (match_test "aarch64_and_bitmask_imm (INTVAL (op), mode)"))) 194 195(define_predicate "aarch64_shift_imm_si" 196 (and (match_code "const_int") 197 (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) < 32"))) 198 199(define_predicate "aarch64_shift_imm_di" 200 (and (match_code "const_int") 201 (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) < 64"))) 202 203(define_predicate "aarch64_shift_imm64_di" 204 (and (match_code "const_int") 205 (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) <= 64"))) 206 207(define_predicate "aarch64_reg_or_shift_imm_si" 208 (ior (match_operand 0 "register_operand") 209 (match_operand 0 "aarch64_shift_imm_si"))) 210 211(define_predicate "aarch64_reg_or_shift_imm_di" 212 (ior (match_operand 0 "register_operand") 213 (match_operand 0 "aarch64_shift_imm_di"))) 214 215;; The imm3 field is a 3-bit field that only accepts immediates in the 216;; range 0..4. 217(define_predicate "aarch64_imm3" 218 (and (match_code "const_int") 219 (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) <= 4"))) 220 221;; The imm2 field is a 2-bit field that only accepts immediates in the 222;; range 0..3. 223(define_predicate "aarch64_imm2" 224 (and (match_code "const_int") 225 (match_test "UINTVAL (op) <= 3"))) 226 227;; The imm3 field is a 3-bit field that only accepts immediates in the 228;; range 0..7. 229(define_predicate "aarch64_lane_imm3" 230 (and (match_code "const_int") 231 (match_test "UINTVAL (op) <= 7"))) 232 233;; An immediate that fits into 24 bits. 234(define_predicate "aarch64_imm24" 235 (and (match_code "const_int") 236 (match_test "IN_RANGE (UINTVAL (op), 0, 0xffffff)"))) 237 238(define_predicate "aarch64_pwr_imm3" 239 (and (match_code "const_int") 240 (match_test "INTVAL (op) != 0 241 && (unsigned) exact_log2 (INTVAL (op)) <= 4"))) 242 243(define_predicate "aarch64_pwr_2_si" 244 (and (match_code "const_int") 245 (match_test "INTVAL (op) != 0 246 && (unsigned) exact_log2 (INTVAL (op)) < 32"))) 247 248(define_predicate "aarch64_pwr_2_di" 249 (and (match_code "const_int") 250 (match_test "INTVAL (op) != 0 251 && (unsigned) exact_log2 (INTVAL (op)) < 64"))) 252 253(define_predicate "aarch64_mem_pair_offset" 254 (and (match_code "const_int") 255 (match_test "aarch64_offset_7bit_signed_scaled_p (mode, INTVAL (op))"))) 256 257(define_predicate "aarch64_mem_pair_operand" 258 (and (match_code "mem") 259 (match_test "aarch64_legitimate_address_p (mode, XEXP (op, 0), false, 260 ADDR_QUERY_LDP_STP)"))) 261 262;; Used for storing two 64-bit values in an AdvSIMD register using an STP 263;; as a 128-bit vec_concat. 264(define_predicate "aarch64_mem_pair_lanes_operand" 265 (and (match_code "mem") 266 (match_test "aarch64_legitimate_address_p (GET_MODE (op), XEXP (op, 0), 267 false, 268 ADDR_QUERY_LDP_STP_N)"))) 269 270(define_predicate "aarch64_prefetch_operand" 271 (match_test "aarch64_address_valid_for_prefetch_p (op, false)")) 272 273(define_predicate "aarch64_valid_symref" 274 (match_code "const, symbol_ref, label_ref") 275{ 276 return (aarch64_classify_symbolic_expression (op) 277 != SYMBOL_FORCE_TO_MEM); 278}) 279 280(define_predicate "aarch64_tls_ie_symref" 281 (match_code "const, symbol_ref, label_ref") 282{ 283 switch (GET_CODE (op)) 284 { 285 case CONST: 286 op = XEXP (op, 0); 287 if (GET_CODE (op) != PLUS 288 || GET_CODE (XEXP (op, 0)) != SYMBOL_REF 289 || GET_CODE (XEXP (op, 1)) != CONST_INT) 290 return false; 291 op = XEXP (op, 0); 292 /* FALLTHRU */ 293 294 case SYMBOL_REF: 295 return SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_INITIAL_EXEC; 296 297 default: 298 gcc_unreachable (); 299 } 300}) 301 302(define_predicate "aarch64_tls_le_symref" 303 (match_code "const, symbol_ref, label_ref") 304{ 305 switch (GET_CODE (op)) 306 { 307 case CONST: 308 op = XEXP (op, 0); 309 if (GET_CODE (op) != PLUS 310 || GET_CODE (XEXP (op, 0)) != SYMBOL_REF 311 || GET_CODE (XEXP (op, 1)) != CONST_INT) 312 return false; 313 op = XEXP (op, 0); 314 /* FALLTHRU */ 315 316 case SYMBOL_REF: 317 return SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_LOCAL_EXEC; 318 319 default: 320 gcc_unreachable (); 321 } 322}) 323 324(define_predicate "aarch64_mov_operand" 325 (and (match_code "reg,subreg,mem,const,const_int,symbol_ref,label_ref,high, 326 const_poly_int,const_vector") 327 (ior (match_operand 0 "register_operand") 328 (ior (match_operand 0 "memory_operand") 329 (match_test "aarch64_mov_operand_p (op, mode)"))))) 330 331(define_predicate "aarch64_nonmemory_operand" 332 (and (match_code "reg,subreg,const,const_int,symbol_ref,label_ref,high, 333 const_poly_int,const_vector") 334 (ior (match_operand 0 "register_operand") 335 (match_test "aarch64_mov_operand_p (op, mode)")))) 336 337(define_predicate "aarch64_movti_operand" 338 (ior (match_operand 0 "register_operand") 339 (match_operand 0 "memory_operand") 340 (and (match_operand 0 "const_scalar_int_operand") 341 (match_test "aarch64_mov128_immediate (op)")))) 342 343(define_predicate "aarch64_reg_or_imm" 344 (ior (match_operand 0 "register_operand") 345 (match_operand 0 "const_scalar_int_operand"))) 346 347;; True for integer comparisons and for FP comparisons other than LTGT or UNEQ. 348(define_special_predicate "aarch64_comparison_operator" 349 (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered, 350 ordered,unlt,unle,unge,ungt")) 351 352;; Same as aarch64_comparison_operator but don't ignore the mode. 353;; RTL SET operations require their operands source and destination have 354;; the same modes, so we can't ignore the modes there. See PR target/69161. 355(define_predicate "aarch64_comparison_operator_mode" 356 (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered, 357 ordered,unlt,unle,unge,ungt")) 358 359(define_special_predicate "aarch64_comparison_operation" 360 (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered, 361 ordered,unlt,unle,unge,ungt") 362{ 363 if (XEXP (op, 1) != const0_rtx) 364 return false; 365 rtx op0 = XEXP (op, 0); 366 if (!REG_P (op0) || REGNO (op0) != CC_REGNUM) 367 return false; 368 return aarch64_get_condition_code (op) >= 0; 369}) 370 371(define_special_predicate "aarch64_equality_operator" 372 (match_code "eq,ne")) 373 374(define_special_predicate "aarch64_carry_operation" 375 (match_code "ltu,geu") 376{ 377 if (XEXP (op, 1) != const0_rtx) 378 return false; 379 rtx op0 = XEXP (op, 0); 380 if (!REG_P (op0) || REGNO (op0) != CC_REGNUM) 381 return false; 382 machine_mode ccmode = GET_MODE (op0); 383 if (ccmode == CC_Cmode) 384 return GET_CODE (op) == LTU; 385 if (ccmode == CC_ADCmode || ccmode == CCmode) 386 return GET_CODE (op) == GEU; 387 return false; 388}) 389 390; borrow is essentially the inverse of carry since the sense of the C flag 391; is inverted during subtraction. See the note in aarch64-modes.def. 392(define_special_predicate "aarch64_borrow_operation" 393 (match_code "geu,ltu") 394{ 395 if (XEXP (op, 1) != const0_rtx) 396 return false; 397 rtx op0 = XEXP (op, 0); 398 if (!REG_P (op0) || REGNO (op0) != CC_REGNUM) 399 return false; 400 machine_mode ccmode = GET_MODE (op0); 401 if (ccmode == CC_Cmode) 402 return GET_CODE (op) == GEU; 403 if (ccmode == CC_ADCmode || ccmode == CCmode) 404 return GET_CODE (op) == LTU; 405 return false; 406}) 407 408;; True if the operand is memory reference suitable for a load/store exclusive. 409(define_predicate "aarch64_sync_memory_operand" 410 (and (match_operand 0 "memory_operand") 411 (match_code "reg" "0"))) 412 413(define_predicate "aarch64_9bit_offset_memory_operand" 414 (and (match_operand 0 "memory_operand") 415 (ior (match_code "reg" "0") 416 (and (match_code "plus" "0") 417 (match_code "reg" "00") 418 (match_code "const_int" "01")))) 419{ 420 rtx mem_op = XEXP (op, 0); 421 422 if (REG_P (mem_op)) 423 return GET_MODE (mem_op) == DImode; 424 425 rtx plus_op0 = XEXP (mem_op, 0); 426 rtx plus_op1 = XEXP (mem_op, 1); 427 428 if (GET_MODE (plus_op0) != DImode) 429 return false; 430 431 poly_int64 offset; 432 if (!poly_int_rtx_p (plus_op1, &offset)) 433 gcc_unreachable (); 434 435 return aarch64_offset_9bit_signed_unscaled_p (mode, offset); 436}) 437 438(define_predicate "aarch64_rcpc_memory_operand" 439 (if_then_else (match_test "AARCH64_ISA_RCPC8_4") 440 (match_operand 0 "aarch64_9bit_offset_memory_operand") 441 (match_operand 0 "aarch64_sync_memory_operand"))) 442 443;; Predicates for parallel expanders based on mode. 444(define_special_predicate "vect_par_cnst_hi_half" 445 (match_code "parallel") 446{ 447 return aarch64_simd_check_vect_par_cnst_half (op, mode, true); 448}) 449 450(define_special_predicate "vect_par_cnst_lo_half" 451 (match_code "parallel") 452{ 453 return aarch64_simd_check_vect_par_cnst_half (op, mode, false); 454}) 455 456(define_predicate "descending_int_parallel" 457 (match_code "parallel") 458{ 459 return aarch64_stepped_int_parallel_p (op, -1); 460}) 461 462(define_predicate "ascending_int_parallel" 463 (match_code "parallel") 464{ 465 return aarch64_stepped_int_parallel_p (op, 1); 466}) 467 468(define_special_predicate "aarch64_simd_lshift_imm" 469 (match_code "const,const_vector") 470{ 471 return aarch64_simd_shift_imm_p (op, mode, true); 472}) 473 474(define_special_predicate "aarch64_simd_rshift_imm" 475 (match_code "const,const_vector") 476{ 477 return aarch64_simd_shift_imm_p (op, mode, false); 478}) 479 480(define_predicate "aarch64_simd_imm_zero" 481 (and (match_code "const,const_vector") 482 (match_test "op == CONST0_RTX (GET_MODE (op))"))) 483 484(define_predicate "aarch64_simd_imm_one" 485 (and (match_code "const_vector") 486 (match_test "op == CONST1_RTX (GET_MODE (op))"))) 487 488(define_predicate "aarch64_simd_or_scalar_imm_zero" 489 (and (match_code "const_int,const_double,const,const_vector") 490 (match_test "op == CONST0_RTX (GET_MODE (op))"))) 491 492(define_predicate "aarch64_simd_imm_minus_one" 493 (and (match_code "const,const_vector") 494 (match_test "op == CONSTM1_RTX (GET_MODE (op))"))) 495 496(define_predicate "aarch64_simd_reg_or_zero" 497 (and (match_code "reg,subreg,const_int,const_double,const,const_vector") 498 (ior (match_operand 0 "register_operand") 499 (match_test "op == const0_rtx") 500 (match_operand 0 "aarch64_simd_or_scalar_imm_zero")))) 501 502(define_predicate "aarch64_simd_reg_or_minus_one" 503 (ior (match_operand 0 "register_operand") 504 (match_operand 0 "aarch64_simd_imm_minus_one"))) 505 506(define_predicate "aarch64_simd_struct_operand" 507 (and (match_code "mem") 508 (match_test "TARGET_SIMD && aarch64_simd_mem_operand_p (op)"))) 509 510;; Like general_operand but allow only valid SIMD addressing modes. 511(define_predicate "aarch64_simd_general_operand" 512 (and (match_operand 0 "general_operand") 513 (match_test "!MEM_P (op) 514 || GET_CODE (XEXP (op, 0)) == POST_INC 515 || GET_CODE (XEXP (op, 0)) == REG"))) 516 517;; Like nonimmediate_operand but allow only valid SIMD addressing modes. 518(define_predicate "aarch64_simd_nonimmediate_operand" 519 (and (match_operand 0 "nonimmediate_operand") 520 (match_test "!MEM_P (op) 521 || GET_CODE (XEXP (op, 0)) == POST_INC 522 || GET_CODE (XEXP (op, 0)) == REG"))) 523 524;; Predicates used by the various SIMD shift operations. These 525;; fall in to 3 categories. 526;; Shifts with a range 0-(bit_size - 1) (aarch64_simd_shift_imm) 527;; Shifts with a range 1-bit_size (aarch64_simd_shift_imm_offset) 528;; Shifts with a range 0-bit_size (aarch64_simd_shift_imm_bitsize) 529(define_predicate "aarch64_simd_shift_imm_qi" 530 (and (match_code "const_int") 531 (match_test "IN_RANGE (INTVAL (op), 0, 7)"))) 532 533(define_predicate "aarch64_simd_shift_imm_hi" 534 (and (match_code "const_int") 535 (match_test "IN_RANGE (INTVAL (op), 0, 15)"))) 536 537(define_predicate "aarch64_simd_shift_imm_si" 538 (and (match_code "const_int") 539 (match_test "IN_RANGE (INTVAL (op), 0, 31)"))) 540 541(define_predicate "aarch64_simd_shift_imm_di" 542 (and (match_code "const_int") 543 (match_test "IN_RANGE (INTVAL (op), 0, 63)"))) 544 545(define_predicate "aarch64_simd_shift_imm_offset_qi" 546 (and (match_code "const_int") 547 (match_test "IN_RANGE (INTVAL (op), 1, 8)"))) 548 549(define_predicate "aarch64_simd_shift_imm_offset_hi" 550 (and (match_code "const_int") 551 (match_test "IN_RANGE (INTVAL (op), 1, 16)"))) 552 553(define_predicate "aarch64_simd_shift_imm_offset_si" 554 (and (match_code "const_int") 555 (match_test "IN_RANGE (INTVAL (op), 1, 32)"))) 556 557(define_predicate "aarch64_simd_shift_imm_offset_di" 558 (and (match_code "const_int") 559 (match_test "IN_RANGE (INTVAL (op), 1, 64)"))) 560 561(define_predicate "aarch64_simd_shift_imm_bitsize_qi" 562 (and (match_code "const_int") 563 (match_test "IN_RANGE (INTVAL (op), 0, 8)"))) 564 565(define_predicate "aarch64_simd_shift_imm_bitsize_hi" 566 (and (match_code "const_int") 567 (match_test "IN_RANGE (INTVAL (op), 0, 16)"))) 568 569(define_predicate "aarch64_simd_shift_imm_bitsize_si" 570 (and (match_code "const_int") 571 (match_test "IN_RANGE (INTVAL (op), 0, 32)"))) 572 573(define_predicate "aarch64_simd_shift_imm_bitsize_di" 574 (and (match_code "const_int") 575 (match_test "IN_RANGE (INTVAL (op), 0, 64)"))) 576 577(define_predicate "aarch64_constant_pool_symref" 578 (and (match_code "symbol_ref") 579 (match_test "CONSTANT_POOL_ADDRESS_P (op)"))) 580 581(define_predicate "aarch64_constant_vector_operand" 582 (match_code "const,const_vector")) 583 584(define_predicate "aarch64_sve_ld1r_operand" 585 (and (match_operand 0 "memory_operand") 586 (match_test "aarch64_sve_ld1r_operand_p (op)"))) 587 588(define_predicate "aarch64_sve_ld1rq_operand" 589 (and (match_code "mem") 590 (match_test "aarch64_sve_ld1rq_operand_p (op)"))) 591 592(define_predicate "aarch64_sve_ld1ro_operand_b" 593 (and (match_code "mem") 594 (match_test "aarch64_sve_ld1ro_operand_p (op, QImode)"))) 595 596(define_predicate "aarch64_sve_ld1ro_operand_h" 597 (and (match_code "mem") 598 (match_test "aarch64_sve_ld1ro_operand_p (op, HImode)"))) 599 600(define_predicate "aarch64_sve_ld1ro_operand_w" 601 (and (match_code "mem") 602 (match_test "aarch64_sve_ld1ro_operand_p (op, SImode)"))) 603 604(define_predicate "aarch64_sve_ld1ro_operand_d" 605 (and (match_code "mem") 606 (match_test "aarch64_sve_ld1ro_operand_p (op, DImode)"))) 607 608(define_predicate "aarch64_sve_ldff1_operand" 609 (and (match_code "mem") 610 (match_test "aarch64_sve_ldff1_operand_p (op)"))) 611 612(define_predicate "aarch64_sve_ldnf1_operand" 613 (and (match_code "mem") 614 (match_test "aarch64_sve_ldnf1_operand_p (op)"))) 615 616;; Like memory_operand, but restricted to addresses that are valid for 617;; SVE LDR and STR instructions. 618(define_predicate "aarch64_sve_ldr_operand" 619 (and (match_code "mem") 620 (match_test "aarch64_sve_ldr_operand_p (op)"))) 621 622(define_special_predicate "aarch64_sve_prefetch_operand" 623 (and (match_code "reg, plus") 624 (match_test "aarch64_sve_prefetch_operand_p (op, mode)"))) 625 626(define_predicate "aarch64_sve_nonimmediate_operand" 627 (ior (match_operand 0 "register_operand") 628 (match_operand 0 "aarch64_sve_ldr_operand"))) 629 630(define_predicate "aarch64_sve_general_operand" 631 (and (match_code "reg,subreg,mem,const,const_vector") 632 (ior (match_operand 0 "register_operand") 633 (match_operand 0 "aarch64_sve_ldr_operand") 634 (match_test "aarch64_mov_operand_p (op, mode)")))) 635 636(define_predicate "aarch64_sve_struct_memory_operand" 637 (and (match_code "mem") 638 (match_test "aarch64_sve_struct_memory_operand_p (op)"))) 639 640(define_predicate "aarch64_sve_struct_nonimmediate_operand" 641 (ior (match_operand 0 "register_operand") 642 (match_operand 0 "aarch64_sve_struct_memory_operand"))) 643 644;; Doesn't include immediates, since those are handled by the move 645;; patterns instead. 646(define_predicate "aarch64_sve_dup_operand" 647 (ior (match_operand 0 "register_operand") 648 (match_operand 0 "aarch64_sve_ld1r_operand"))) 649 650(define_predicate "aarch64_sve_ptrue_svpattern_immediate" 651 (and (match_code "const") 652 (match_test "aarch64_sve_ptrue_svpattern_p (op, NULL)"))) 653 654(define_predicate "aarch64_sve_arith_immediate" 655 (and (match_code "const,const_vector") 656 (match_test "aarch64_sve_arith_immediate_p (mode, op, false)"))) 657 658(define_predicate "aarch64_sve_sub_arith_immediate" 659 (and (match_code "const,const_vector") 660 (match_test "aarch64_sve_arith_immediate_p (mode, op, true)"))) 661 662(define_predicate "aarch64_sve_qadd_immediate" 663 (and (match_code "const,const_vector") 664 (match_test "aarch64_sve_sqadd_sqsub_immediate_p (mode, op, false)"))) 665 666(define_predicate "aarch64_sve_qsub_immediate" 667 (and (match_code "const,const_vector") 668 (match_test "aarch64_sve_sqadd_sqsub_immediate_p (mode, op, true)"))) 669 670(define_predicate "aarch64_sve_vector_inc_dec_immediate" 671 (and (match_code "const,const_vector") 672 (match_test "aarch64_sve_vector_inc_dec_immediate_p (op)"))) 673 674(define_predicate "aarch64_sve_gather_immediate_b" 675 (and (match_code "const_int") 676 (match_test "IN_RANGE (INTVAL (op), 0, 31)"))) 677 678(define_predicate "aarch64_sve_gather_immediate_h" 679 (and (match_code "const_int") 680 (match_test "IN_RANGE (INTVAL (op), 0, 62)") 681 (match_test "(INTVAL (op) & 1) == 0"))) 682 683(define_predicate "aarch64_sve_gather_immediate_w" 684 (and (match_code "const_int") 685 (match_test "IN_RANGE (INTVAL (op), 0, 124)") 686 (match_test "(INTVAL (op) & 3) == 0"))) 687 688(define_predicate "aarch64_sve_gather_immediate_d" 689 (and (match_code "const_int") 690 (match_test "IN_RANGE (INTVAL (op), 0, 248)") 691 (match_test "(INTVAL (op) & 7) == 0"))) 692 693(define_predicate "aarch64_sve_uxtb_immediate" 694 (and (match_code "const_vector") 695 (match_test "GET_MODE_UNIT_BITSIZE (GET_MODE (op)) > 8") 696 (match_test "aarch64_const_vec_all_same_int_p (op, 0xff)"))) 697 698(define_predicate "aarch64_sve_uxth_immediate" 699 (and (match_code "const_vector") 700 (match_test "GET_MODE_UNIT_BITSIZE (GET_MODE (op)) > 16") 701 (match_test "aarch64_const_vec_all_same_int_p (op, 0xffff)"))) 702 703(define_predicate "aarch64_sve_uxtw_immediate" 704 (and (match_code "const_vector") 705 (match_test "GET_MODE_UNIT_BITSIZE (GET_MODE (op)) > 32") 706 (match_test "aarch64_const_vec_all_same_int_p (op, 0xffffffff)"))) 707 708(define_predicate "aarch64_sve_uxt_immediate" 709 (ior (match_operand 0 "aarch64_sve_uxtb_immediate") 710 (match_operand 0 "aarch64_sve_uxth_immediate") 711 (match_operand 0 "aarch64_sve_uxtw_immediate"))) 712 713(define_predicate "aarch64_sve_logical_immediate" 714 (and (match_code "const,const_vector") 715 (match_test "aarch64_sve_bitmask_immediate_p (op)"))) 716 717;; Used for SVE UMAX and UMIN. 718(define_predicate "aarch64_sve_vsb_immediate" 719 (and (match_code "const_vector") 720 (match_test "GET_MODE_INNER (GET_MODE (op)) == QImode 721 ? aarch64_const_vec_all_same_in_range_p (op, -128, 127) 722 : aarch64_const_vec_all_same_in_range_p (op, 0, 255)"))) 723 724;; Used for SVE MUL, SMAX and SMIN. 725(define_predicate "aarch64_sve_vsm_immediate" 726 (and (match_code "const,const_vector") 727 (match_test "aarch64_const_vec_all_same_in_range_p (op, -128, 127)"))) 728 729(define_predicate "aarch64_sve_dup_immediate" 730 (and (match_code "const,const_vector") 731 (ior (match_test "aarch64_sve_dup_immediate_p (op)") 732 (match_test "aarch64_float_const_representable_p (op)")))) 733 734(define_predicate "aarch64_sve_cmp_vsc_immediate" 735 (and (match_code "const_int,const_vector") 736 (match_test "aarch64_sve_cmp_immediate_p (op, true)"))) 737 738(define_predicate "aarch64_sve_cmp_vsd_immediate" 739 (and (match_code "const_int,const_vector") 740 (match_test "aarch64_sve_cmp_immediate_p (op, false)"))) 741 742(define_predicate "aarch64_sve_index_immediate" 743 (and (match_code "const_int") 744 (match_test "aarch64_sve_index_immediate_p (op)"))) 745 746(define_predicate "aarch64_sve_float_arith_immediate" 747 (and (match_code "const,const_vector") 748 (match_test "aarch64_sve_float_arith_immediate_p (op, false)"))) 749 750(define_predicate "aarch64_sve_float_negated_arith_immediate" 751 (and (match_code "const,const_vector") 752 (match_test "aarch64_sve_float_arith_immediate_p (op, true)"))) 753 754(define_predicate "aarch64_sve_float_arith_with_sub_immediate" 755 (ior (match_operand 0 "aarch64_sve_float_arith_immediate") 756 (match_operand 0 "aarch64_sve_float_negated_arith_immediate"))) 757 758(define_predicate "aarch64_sve_float_mul_immediate" 759 (and (match_code "const,const_vector") 760 (match_test "aarch64_sve_float_mul_immediate_p (op)"))) 761 762(define_predicate "aarch64_sve_float_maxmin_immediate" 763 (and (match_code "const_vector") 764 (ior (match_test "op == CONST0_RTX (GET_MODE (op))") 765 (match_test "op == CONST1_RTX (GET_MODE (op))")))) 766 767(define_predicate "aarch64_sve_arith_operand" 768 (ior (match_operand 0 "register_operand") 769 (match_operand 0 "aarch64_sve_arith_immediate"))) 770 771(define_predicate "aarch64_sve_add_operand" 772 (ior (match_operand 0 "aarch64_sve_arith_operand") 773 (match_operand 0 "aarch64_sve_sub_arith_immediate") 774 (match_operand 0 "aarch64_sve_vector_inc_dec_immediate"))) 775 776(define_predicate "aarch64_sve_sqadd_operand" 777 (ior (match_operand 0 "register_operand") 778 (match_operand 0 "aarch64_sve_qadd_immediate") 779 (match_operand 0 "aarch64_sve_qsub_immediate"))) 780 781(define_predicate "aarch64_sve_pred_and_operand" 782 (ior (match_operand 0 "register_operand") 783 (match_operand 0 "aarch64_sve_uxt_immediate"))) 784 785(define_predicate "aarch64_sve_logical_operand" 786 (ior (match_operand 0 "register_operand") 787 (match_operand 0 "aarch64_sve_logical_immediate"))) 788 789(define_predicate "aarch64_sve_gather_offset_b" 790 (ior (match_operand 0 "register_operand") 791 (match_operand 0 "aarch64_sve_gather_immediate_b"))) 792 793(define_predicate "aarch64_sve_gather_offset_h" 794 (ior (match_operand 0 "register_operand") 795 (match_operand 0 "aarch64_sve_gather_immediate_h"))) 796 797(define_predicate "aarch64_sve_gather_offset_w" 798 (ior (match_operand 0 "register_operand") 799 (match_operand 0 "aarch64_sve_gather_immediate_w"))) 800 801(define_predicate "aarch64_sve_gather_offset_d" 802 (ior (match_operand 0 "register_operand") 803 (match_operand 0 "aarch64_sve_gather_immediate_d"))) 804 805(define_predicate "aarch64_sve_lshift_operand" 806 (ior (match_operand 0 "register_operand") 807 (match_operand 0 "aarch64_simd_lshift_imm"))) 808 809(define_predicate "aarch64_sve_rshift_operand" 810 (ior (match_operand 0 "register_operand") 811 (match_operand 0 "aarch64_simd_rshift_imm"))) 812 813(define_predicate "aarch64_sve_vsb_operand" 814 (ior (match_operand 0 "register_operand") 815 (match_operand 0 "aarch64_sve_vsb_immediate"))) 816 817(define_predicate "aarch64_sve_vsm_operand" 818 (ior (match_operand 0 "register_operand") 819 (match_operand 0 "aarch64_sve_vsm_immediate"))) 820 821(define_predicate "aarch64_sve_reg_or_dup_imm" 822 (ior (match_operand 0 "register_operand") 823 (match_operand 0 "aarch64_sve_dup_immediate"))) 824 825(define_predicate "aarch64_sve_cmp_vsc_operand" 826 (ior (match_operand 0 "register_operand") 827 (match_operand 0 "aarch64_sve_cmp_vsc_immediate"))) 828 829(define_predicate "aarch64_sve_cmp_vsd_operand" 830 (ior (match_operand 0 "register_operand") 831 (match_operand 0 "aarch64_sve_cmp_vsd_immediate"))) 832 833(define_predicate "aarch64_sve_index_operand" 834 (ior (match_operand 0 "register_operand") 835 (match_operand 0 "aarch64_sve_index_immediate"))) 836 837(define_predicate "aarch64_sve_float_arith_operand" 838 (ior (match_operand 0 "register_operand") 839 (match_operand 0 "aarch64_sve_float_arith_immediate"))) 840 841(define_predicate "aarch64_sve_float_arith_with_sub_operand" 842 (ior (match_operand 0 "register_operand") 843 (match_operand 0 "aarch64_sve_float_arith_with_sub_immediate"))) 844 845(define_predicate "aarch64_sve_float_mul_operand" 846 (ior (match_operand 0 "register_operand") 847 (match_operand 0 "aarch64_sve_float_mul_immediate"))) 848 849(define_predicate "aarch64_sve_float_maxmin_operand" 850 (ior (match_operand 0 "register_operand") 851 (match_operand 0 "aarch64_sve_float_maxmin_immediate"))) 852 853(define_predicate "aarch64_sve_vec_perm_operand" 854 (ior (match_operand 0 "register_operand") 855 (match_operand 0 "aarch64_constant_vector_operand"))) 856 857(define_predicate "aarch64_sve_ptrue_flag" 858 (and (match_code "const_int") 859 (ior (match_test "INTVAL (op) == SVE_MAYBE_NOT_PTRUE") 860 (match_test "INTVAL (op) == SVE_KNOWN_PTRUE")))) 861 862(define_predicate "aarch64_sve_gp_strictness" 863 (and (match_code "const_int") 864 (ior (match_test "INTVAL (op) == SVE_RELAXED_GP") 865 (match_test "INTVAL (op) == SVE_STRICT_GP")))) 866 867(define_predicate "aarch64_gather_scale_operand_b" 868 (and (match_code "const_int") 869 (match_test "INTVAL (op) == 1"))) 870 871(define_predicate "aarch64_gather_scale_operand_h" 872 (and (match_code "const_int") 873 (match_test "INTVAL (op) == 1 || INTVAL (op) == 2"))) 874 875(define_predicate "aarch64_gather_scale_operand_w" 876 (and (match_code "const_int") 877 (match_test "INTVAL (op) == 1 || INTVAL (op) == 4"))) 878 879(define_predicate "aarch64_gather_scale_operand_d" 880 (and (match_code "const_int") 881 (match_test "INTVAL (op) == 1 || INTVAL (op) == 8"))) 882 883;; A special predicate that doesn't match a particular mode. 884(define_special_predicate "aarch64_any_register_operand" 885 (match_code "reg")) 886 887(define_predicate "aarch64_sve_any_binary_operator" 888 (match_code "plus,minus,mult,div,udiv,smax,umax,smin,umin,and,ior,xor")) 889 890(define_predicate "aarch64_bytes_per_sve_vector_operand" 891 (and (match_code "const_int,const_poly_int") 892 (match_test "known_eq (wi::to_poly_wide (op, mode), 893 BYTES_PER_SVE_VECTOR)"))) 894 895(define_predicate "aarch64_memtag_tag_offset" 896 (and (match_code "const_int") 897 (match_test "IN_RANGE (INTVAL (op), 0, 15)"))) 898 899(define_predicate "aarch64_granule16_uimm6" 900 (and (match_code "const_int") 901 (match_test "IN_RANGE (INTVAL (op), 0, 1008) 902 && !(INTVAL (op) & 0xf)"))) 903 904(define_predicate "aarch64_granule16_simm9" 905 (and (match_code "const_int") 906 (match_test "IN_RANGE (INTVAL (op), -4096, 4080) 907 && !(INTVAL (op) & 0xf)"))) 908