1;; Machine description for AArch64 architecture. 2;; Copyright (C) 2009-2020 Free Software Foundation, Inc. 3;; Contributed by ARM Ltd. 4;; 5;; This file is part of GCC. 6;; 7;; GCC is free software; you can redistribute it and/or modify it 8;; under the terms of the GNU General Public License as published by 9;; the Free Software Foundation; either version 3, or (at your option) 10;; any later version. 11;; 12;; GCC is distributed in the hope that it will be useful, but 13;; WITHOUT ANY WARRANTY; without even the implied warranty of 14;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15;; General Public License for more details. 16;; 17;; You should have received a copy of the GNU General Public License 18;; along with GCC; see the file COPYING3. If not see 19;; <http://www.gnu.org/licenses/>. 20 21;; ------------------------------------------------------------------- 22;; Mode Iterators 23;; ------------------------------------------------------------------- 24 25;; Condition-code iterators. 26(define_mode_iterator CC_ONLY [CC]) 27(define_mode_iterator CCFP_CCFPE [CCFP CCFPE]) 28 29;; Iterator for General Purpose Integer registers (32- and 64-bit modes) 30(define_mode_iterator GPI [SI DI]) 31 32;; Iterator for HI, SI, DI, some instructions can only work on these modes. 33(define_mode_iterator GPI_I16 [(HI "AARCH64_ISA_F16") SI DI]) 34 35;; "Iterator" for just TI -- features like @pattern only work with iterators. 36(define_mode_iterator JUST_TI [TI]) 37 38;; Iterator for QI and HI modes 39(define_mode_iterator SHORT [QI HI]) 40 41;; Iterators for single modes, for "@" patterns. 42(define_mode_iterator SI_ONLY [SI]) 43(define_mode_iterator DI_ONLY [DI]) 44 45;; Iterator for all integer modes (up to 64-bit) 46(define_mode_iterator ALLI [QI HI SI DI]) 47 48;; Iterator for all integer modes (up to 128-bit) 49(define_mode_iterator ALLI_TI [QI HI SI DI TI]) 50 51;; Iterator for all integer modes that can be extended (up to 64-bit) 52(define_mode_iterator ALLX [QI HI SI]) 53 54;; Iterator for General Purpose Floating-point registers (32- and 64-bit modes) 55(define_mode_iterator GPF [SF DF]) 56 57;; Iterator for all scalar floating point modes (HF, SF, DF) 58(define_mode_iterator GPF_F16 [(HF "AARCH64_ISA_F16") SF DF]) 59 60;; Iterator for all scalar floating point modes (HF, SF, DF) 61(define_mode_iterator GPF_HF [HF SF DF]) 62 63;; Iterator for all 16-bit scalar floating point modes (HF, BF) 64(define_mode_iterator HFBF [HF BF]) 65 66;; Iterator for all scalar floating point modes (HF, SF, DF and TF) 67(define_mode_iterator GPF_TF_F16 [HF SF DF TF]) 68 69;; Iterator for all scalar floating point modes suitable for moving, including 70;; special BF type (HF, SF, DF, TF and BF) 71(define_mode_iterator GPF_TF_F16_MOV [HF BF SF DF TF]) 72 73;; Double vector modes. 74(define_mode_iterator VDF [V2SF V4HF]) 75 76;; Iterator for all scalar floating point modes (SF, DF and TF) 77(define_mode_iterator GPF_TF [SF DF TF]) 78 79;; Integer Advanced SIMD modes. 80(define_mode_iterator VDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI]) 81 82;; Advanced SIMD and scalar, 64 & 128-bit container, all integer modes. 83(define_mode_iterator VSDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI QI HI SI DI]) 84 85;; Advanced SIMD and scalar, 64 & 128-bit container: all Advanced SIMD 86;; integer modes; 64-bit scalar integer mode. 87(define_mode_iterator VSDQ_I_DI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI DI]) 88 89;; Double vector modes. 90(define_mode_iterator VD [V8QI V4HI V4HF V2SI V2SF V4BF]) 91 92;; Double vector modes suitable for moving. Includes BFmode. 93(define_mode_iterator VDMOV [V8QI V4HI V4HF V4BF V2SI V2SF]) 94 95;; All modes stored in registers d0-d31. 96(define_mode_iterator DREG [V8QI V4HI V4HF V2SI V2SF DF]) 97 98;; Copy of the above. 99(define_mode_iterator DREG2 [V8QI V4HI V4HF V2SI V2SF DF]) 100 101;; Advanced SIMD, 64-bit container, all integer modes. 102(define_mode_iterator VD_BHSI [V8QI V4HI V2SI]) 103 104;; 128 and 64-bit container; 8, 16, 32-bit vector integer modes 105(define_mode_iterator VDQ_BHSI [V8QI V16QI V4HI V8HI V2SI V4SI]) 106 107;; Quad vector modes. 108(define_mode_iterator VQ [V16QI V8HI V4SI V2DI V8HF V4SF V2DF V8BF]) 109 110;; Copy of the above. 111(define_mode_iterator VQ2 [V16QI V8HI V4SI V2DI V8HF V8BF V4SF V2DF]) 112 113;; Quad vector modes suitable for moving. Includes BFmode. 114(define_mode_iterator VQMOV [V16QI V8HI V4SI V2DI V8HF V8BF V4SF V2DF]) 115 116;; VQMOV without 2-element modes. 117(define_mode_iterator VQMOV_NO2E [V16QI V8HI V4SI V8HF V8BF V4SF]) 118 119;; Quad integer vector modes. 120(define_mode_iterator VQ_I [V16QI V8HI V4SI V2DI]) 121 122;; VQ without 2 element modes. 123(define_mode_iterator VQ_NO2E [V16QI V8HI V4SI V8HF V4SF V8BF]) 124 125;; BFmode vector modes. 126(define_mode_iterator VBF [V4BF V8BF]) 127 128;; This mode iterator allows :P to be used for patterns that operate on 129;; addresses in different modes. In LP64, only DI will match, while in 130;; ILP32, either can match. 131(define_mode_iterator P [(SI "ptr_mode == SImode || Pmode == SImode") 132 (DI "ptr_mode == DImode || Pmode == DImode")]) 133 134;; This mode iterator allows :PTR to be used for patterns that operate on 135;; pointer-sized quantities. Exactly one of the two alternatives will match. 136(define_mode_iterator PTR [(SI "ptr_mode == SImode") (DI "ptr_mode == DImode")]) 137 138;; Advanced SIMD Float modes suitable for moving, loading and storing. 139(define_mode_iterator VDQF_F16 [V4HF V8HF V2SF V4SF V2DF 140 V4BF V8BF]) 141 142;; Advanced SIMD Float modes. 143(define_mode_iterator VDQF [V2SF V4SF V2DF]) 144(define_mode_iterator VHSDF [(V4HF "TARGET_SIMD_F16INST") 145 (V8HF "TARGET_SIMD_F16INST") 146 V2SF V4SF V2DF]) 147 148;; Advanced SIMD Float modes, and DF. 149(define_mode_iterator VHSDF_DF [(V4HF "TARGET_SIMD_F16INST") 150 (V8HF "TARGET_SIMD_F16INST") 151 V2SF V4SF V2DF DF]) 152(define_mode_iterator VHSDF_HSDF [(V4HF "TARGET_SIMD_F16INST") 153 (V8HF "TARGET_SIMD_F16INST") 154 V2SF V4SF V2DF 155 (HF "TARGET_SIMD_F16INST") 156 SF DF]) 157 158;; Scalar and vetor modes for SF, DF. 159(define_mode_iterator VSFDF [V2SF V4SF V2DF DF SF]) 160 161;; Advanced SIMD single Float modes. 162(define_mode_iterator VDQSF [V2SF V4SF]) 163 164;; Quad vector Float modes with half/single elements. 165(define_mode_iterator VQ_HSF [V8HF V4SF]) 166 167;; Modes suitable to use as the return type of a vcond expression. 168(define_mode_iterator VDQF_COND [V2SF V2SI V4SF V4SI V2DF V2DI]) 169 170;; All scalar and Advanced SIMD Float modes. 171(define_mode_iterator VALLF [V2SF V4SF V2DF SF DF]) 172 173;; Advanced SIMD Float modes with 2 elements. 174(define_mode_iterator V2F [V2SF V2DF]) 175 176;; All Advanced SIMD modes on which we support any arithmetic operations. 177(define_mode_iterator VALL [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF]) 178 179;; All Advanced SIMD modes suitable for moving, loading, and storing. 180(define_mode_iterator VALL_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI 181 V4HF V8HF V4BF V8BF V2SF V4SF V2DF]) 182 183;; All Advanced SIMD modes suitable for moving, loading, and storing, 184;; including special Bfloat vector types. 185(define_mode_iterator VALL_F16MOV [V8QI V16QI V4HI V8HI V2SI V4SI V2DI 186 V4HF V8HF V4BF V8BF V2SF V4SF V2DF]) 187 188;; The VALL_F16 modes except the 128-bit 2-element ones. 189(define_mode_iterator VALL_F16_NO_V2Q [V8QI V16QI V4HI V8HI V2SI V4SI 190 V4HF V8HF V2SF V4SF]) 191 192;; All Advanced SIMD modes barring HF modes, plus DI. 193(define_mode_iterator VALLDI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF DI]) 194 195;; All Advanced SIMD modes and DI. 196(define_mode_iterator VALLDI_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI 197 V4HF V8HF V4BF V8BF V2SF V4SF V2DF DI]) 198 199;; All Advanced SIMD modes, plus DI and DF. 200(define_mode_iterator VALLDIF [V8QI V16QI V4HI V8HI V2SI V4SI V4BF V8BF 201 V2DI V4HF V8HF V2SF V4SF V2DF DI DF]) 202 203;; Advanced SIMD modes for Integer reduction across lanes. 204(define_mode_iterator VDQV [V8QI V16QI V4HI V8HI V4SI V2DI]) 205 206;; Advanced SIMD modes (except V2DI) for Integer reduction across lanes. 207(define_mode_iterator VDQV_S [V8QI V16QI V4HI V8HI V4SI]) 208 209;; Advanced SIMD modes for Integer reduction across lanes (zero/sign extended). 210(define_mode_iterator VDQV_E [V8QI V16QI V4HI V8HI]) 211 212;; All double integer narrow-able modes. 213(define_mode_iterator VDN [V4HI V2SI DI]) 214 215;; All quad integer narrow-able modes. 216(define_mode_iterator VQN [V8HI V4SI V2DI]) 217 218;; Advanced SIMD and scalar 128-bit container: narrowable 16, 32, 64-bit 219;; integer modes 220(define_mode_iterator VSQN_HSDI [V8HI V4SI V2DI HI SI DI]) 221 222;; All quad integer widen-able modes. 223(define_mode_iterator VQW [V16QI V8HI V4SI]) 224 225;; Double vector modes for combines. 226(define_mode_iterator VDC [V8QI V4HI V4BF V4HF V2SI V2SF DI DF]) 227 228;; Advanced SIMD modes except double int. 229(define_mode_iterator VDQIF [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DF]) 230(define_mode_iterator VDQIF_F16 [V8QI V16QI V4HI V8HI V2SI V4SI 231 V4HF V8HF V2SF V4SF V2DF]) 232 233;; Advanced SIMD modes for S type. 234(define_mode_iterator VDQ_SI [V2SI V4SI]) 235 236;; Advanced SIMD modes for S and D. 237(define_mode_iterator VDQ_SDI [V2SI V4SI V2DI]) 238 239;; Advanced SIMD modes for H, S and D. 240(define_mode_iterator VDQ_HSDI [(V4HI "TARGET_SIMD_F16INST") 241 (V8HI "TARGET_SIMD_F16INST") 242 V2SI V4SI V2DI]) 243 244;; Scalar and Advanced SIMD modes for S and D. 245(define_mode_iterator VSDQ_SDI [V2SI V4SI V2DI SI DI]) 246 247;; Scalar and Advanced SIMD modes for S and D, Advanced SIMD modes for H. 248(define_mode_iterator VSDQ_HSDI [(V4HI "TARGET_SIMD_F16INST") 249 (V8HI "TARGET_SIMD_F16INST") 250 V2SI V4SI V2DI 251 (HI "TARGET_SIMD_F16INST") 252 SI DI]) 253 254;; Advanced SIMD modes for Q and H types. 255(define_mode_iterator VDQQH [V8QI V16QI V4HI V8HI]) 256 257;; Advanced SIMD modes for H and S types. 258(define_mode_iterator VDQHS [V4HI V8HI V2SI V4SI]) 259 260;; Advanced SIMD modes for H, S and D types. 261(define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI]) 262 263;; Advanced SIMD and scalar integer modes for H and S. 264(define_mode_iterator VSDQ_HSI [V4HI V8HI V2SI V4SI HI SI]) 265 266;; Advanced SIMD and scalar 64-bit container: 16, 32-bit integer modes. 267(define_mode_iterator VSD_HSI [V4HI V2SI HI SI]) 268 269;; Advanced SIMD 64-bit container: 16, 32-bit integer modes. 270(define_mode_iterator VD_HSI [V4HI V2SI]) 271 272;; Scalar 64-bit container: 16, 32-bit integer modes 273(define_mode_iterator SD_HSI [HI SI]) 274 275;; Advanced SIMD 64-bit container: 16, 32-bit integer modes. 276(define_mode_iterator VQ_HSI [V8HI V4SI]) 277 278;; All byte modes. 279(define_mode_iterator VB [V8QI V16QI]) 280 281;; 2 and 4 lane SI modes. 282(define_mode_iterator VS [V2SI V4SI]) 283 284(define_mode_iterator TX [TI TF]) 285 286;; Advanced SIMD opaque structure modes. 287(define_mode_iterator VSTRUCT [OI CI XI]) 288 289;; Double scalar modes 290(define_mode_iterator DX [DI DF]) 291 292;; Duplicate of the above 293(define_mode_iterator DX2 [DI DF]) 294 295;; Single scalar modes 296(define_mode_iterator SX [SI SF]) 297 298;; Duplicate of the above 299(define_mode_iterator SX2 [SI SF]) 300 301;; Single and double integer and float modes 302(define_mode_iterator DSX [DF DI SF SI]) 303 304 305;; Modes available for Advanced SIMD <f>mul lane operations. 306(define_mode_iterator VMUL [V4HI V8HI V2SI V4SI 307 (V4HF "TARGET_SIMD_F16INST") 308 (V8HF "TARGET_SIMD_F16INST") 309 V2SF V4SF V2DF]) 310 311;; Modes available for Advanced SIMD <f>mul lane operations changing lane 312;; count. 313(define_mode_iterator VMUL_CHANGE_NLANES [V4HI V8HI V2SI V4SI V2SF V4SF]) 314 315;; Iterators for single modes, for "@" patterns. 316(define_mode_iterator VNx16QI_ONLY [VNx16QI]) 317(define_mode_iterator VNx8HI_ONLY [VNx8HI]) 318(define_mode_iterator VNx8BF_ONLY [VNx8BF]) 319(define_mode_iterator VNx4SI_ONLY [VNx4SI]) 320(define_mode_iterator VNx4SF_ONLY [VNx4SF]) 321(define_mode_iterator VNx2DI_ONLY [VNx2DI]) 322(define_mode_iterator VNx2DF_ONLY [VNx2DF]) 323 324;; All SVE vector structure modes. 325(define_mode_iterator SVE_STRUCT [VNx32QI VNx16HI VNx8SI VNx4DI 326 VNx16BF VNx16HF VNx8SF VNx4DF 327 VNx48QI VNx24HI VNx12SI VNx6DI 328 VNx24BF VNx24HF VNx12SF VNx6DF 329 VNx64QI VNx32HI VNx16SI VNx8DI 330 VNx32BF VNx32HF VNx16SF VNx8DF]) 331 332;; All fully-packed SVE vector modes. 333(define_mode_iterator SVE_FULL [VNx16QI VNx8HI VNx4SI VNx2DI 334 VNx8BF VNx8HF VNx4SF VNx2DF]) 335 336;; All fully-packed SVE integer vector modes. 337(define_mode_iterator SVE_FULL_I [VNx16QI VNx8HI VNx4SI VNx2DI]) 338 339;; All fully-packed SVE floating-point vector modes. 340(define_mode_iterator SVE_FULL_F [VNx8HF VNx4SF VNx2DF]) 341 342;; Fully-packed SVE integer vector modes that have 8-bit or 16-bit elements. 343(define_mode_iterator SVE_FULL_BHI [VNx16QI VNx8HI]) 344 345;; Fully-packed SVE integer vector modes that have 8-bit, 16-bit or 32-bit 346;; elements. 347(define_mode_iterator SVE_FULL_BHSI [VNx16QI VNx8HI VNx4SI]) 348 349;; Fully-packed SVE vector modes that have 16-bit, 32-bit or 64-bit elements. 350(define_mode_iterator SVE_FULL_HSD [VNx8HI VNx4SI VNx2DI 351 VNx8BF VNx8HF VNx4SF VNx2DF]) 352 353;; Fully-packed SVE integer vector modes that have 16-bit, 32-bit or 64-bit 354;; elements. 355(define_mode_iterator SVE_FULL_HSDI [VNx8HI VNx4SI VNx2DI]) 356 357;; Fully-packed SVE integer vector modes that have 16-bit or 32-bit 358;; elements. 359(define_mode_iterator SVE_FULL_HSI [VNx8HI VNx4SI]) 360 361;; Fully-packed SVE floating-point vector modes that have 16-bit or 32-bit 362;; elements. 363(define_mode_iterator SVE_FULL_HSF [VNx8HF VNx4SF]) 364 365;; Fully-packed SVE integer vector modes that have 16-bit or 64-bit elements. 366(define_mode_iterator SVE_FULL_HDI [VNx8HI VNx2DI]) 367 368;; Fully-packed SVE vector modes that have 32-bit or 64-bit elements. 369(define_mode_iterator SVE_FULL_SD [VNx4SI VNx2DI VNx4SF VNx2DF]) 370 371;; Fully-packed SVE integer vector modes that have 32-bit or 64-bit elements. 372(define_mode_iterator SVE_FULL_SDI [VNx4SI VNx2DI]) 373 374;; Fully-packed SVE floating-point vector modes that have 32-bit or 64-bit 375;; elements. 376(define_mode_iterator SVE_FULL_SDF [VNx4SF VNx2DF]) 377 378;; Same, but with the appropriate conditions for FMMLA support. 379(define_mode_iterator SVE_MATMULF [(VNx4SF "TARGET_SVE_F32MM") 380 (VNx2DF "TARGET_SVE_F64MM")]) 381 382;; Fully-packed SVE vector modes that have 32-bit elements. 383(define_mode_iterator SVE_FULL_S [VNx4SI VNx4SF]) 384 385;; Fully-packed SVE vector modes that have 64-bit elements. 386(define_mode_iterator SVE_FULL_D [VNx2DI VNx2DF]) 387 388;; All partial SVE integer modes. 389(define_mode_iterator SVE_PARTIAL_I [VNx8QI VNx4QI VNx2QI 390 VNx4HI VNx2HI 391 VNx2SI]) 392 393;; All SVE vector modes. 394(define_mode_iterator SVE_ALL [VNx16QI VNx8QI VNx4QI VNx2QI 395 VNx8HI VNx4HI VNx2HI 396 VNx8HF VNx4HF VNx2HF 397 VNx8BF 398 VNx4SI VNx2SI 399 VNx4SF VNx2SF 400 VNx2DI 401 VNx2DF]) 402 403;; All SVE integer vector modes. 404(define_mode_iterator SVE_I [VNx16QI VNx8QI VNx4QI VNx2QI 405 VNx8HI VNx4HI VNx2HI 406 VNx4SI VNx2SI 407 VNx2DI]) 408 409;; SVE integer vector modes whose elements are 16 bits or wider. 410(define_mode_iterator SVE_HSDI [VNx8HI VNx4HI VNx2HI 411 VNx4SI VNx2SI 412 VNx2DI]) 413 414;; SVE modes with 2 or 4 elements. 415(define_mode_iterator SVE_24 [VNx2QI VNx2HI VNx2HF VNx2SI VNx2SF VNx2DI VNx2DF 416 VNx4QI VNx4HI VNx4HF VNx4SI VNx4SF]) 417 418;; SVE modes with 2 elements. 419(define_mode_iterator SVE_2 [VNx2QI VNx2HI VNx2HF VNx2SI VNx2SF VNx2DI VNx2DF]) 420 421;; SVE integer modes with 2 elements, excluding the widest element. 422(define_mode_iterator SVE_2BHSI [VNx2QI VNx2HI VNx2SI]) 423 424;; SVE integer modes with 2 elements, excluding the narrowest element. 425(define_mode_iterator SVE_2HSDI [VNx2HI VNx2SI VNx2DI]) 426 427;; SVE modes with 4 elements. 428(define_mode_iterator SVE_4 [VNx4QI VNx4HI VNx4HF VNx4SI VNx4SF]) 429 430;; SVE integer modes with 4 elements, excluding the widest element. 431(define_mode_iterator SVE_4BHI [VNx4QI VNx4HI]) 432 433;; SVE integer modes with 4 elements, excluding the narrowest element. 434(define_mode_iterator SVE_4HSI [VNx4HI VNx4SI]) 435 436;; SVE integer modes that can form the input to an SVE2 PMULL[BT] instruction. 437(define_mode_iterator SVE2_PMULL_PAIR_I [VNx16QI VNx4SI 438 (VNx2DI "TARGET_SVE2_AES")]) 439 440;; Modes involved in extending or truncating SVE data, for 8 elements per 441;; 128-bit block. 442(define_mode_iterator VNx8_NARROW [VNx8QI]) 443(define_mode_iterator VNx8_WIDE [VNx8HI]) 444 445;; ...same for 4 elements per 128-bit block. 446(define_mode_iterator VNx4_NARROW [VNx4QI VNx4HI]) 447(define_mode_iterator VNx4_WIDE [VNx4SI]) 448 449;; ...same for 2 elements per 128-bit block. 450(define_mode_iterator VNx2_NARROW [VNx2QI VNx2HI VNx2SI]) 451(define_mode_iterator VNx2_WIDE [VNx2DI]) 452 453;; All SVE predicate modes. 454(define_mode_iterator PRED_ALL [VNx16BI VNx8BI VNx4BI VNx2BI]) 455 456;; SVE predicate modes that control 8-bit, 16-bit or 32-bit elements. 457(define_mode_iterator PRED_BHS [VNx16BI VNx8BI VNx4BI]) 458 459;; SVE predicate modes that control 16-bit, 32-bit or 64-bit elements. 460(define_mode_iterator PRED_HSD [VNx8BI VNx4BI VNx2BI]) 461 462;; Bfloat16 modes to which V4SF can be converted 463(define_mode_iterator V4SF_TO_BF [V4BF V8BF]) 464 465;; ------------------------------------------------------------------ 466;; Unspec enumerations for Advance SIMD. These could well go into 467;; aarch64.md but for their use in int_iterators here. 468;; ------------------------------------------------------------------ 469 470(define_c_enum "unspec" 471 [ 472 UNSPEC_ASHIFT_SIGNED ; Used in aarch-simd.md. 473 UNSPEC_ASHIFT_UNSIGNED ; Used in aarch64-simd.md. 474 UNSPEC_ABS ; Used in aarch64-simd.md. 475 UNSPEC_FMAX ; Used in aarch64-simd.md. 476 UNSPEC_FMAXNMV ; Used in aarch64-simd.md. 477 UNSPEC_FMAXV ; Used in aarch64-simd.md. 478 UNSPEC_FMIN ; Used in aarch64-simd.md. 479 UNSPEC_FMINNMV ; Used in aarch64-simd.md. 480 UNSPEC_FMINV ; Used in aarch64-simd.md. 481 UNSPEC_FADDV ; Used in aarch64-simd.md. 482 UNSPEC_ADDV ; Used in aarch64-simd.md. 483 UNSPEC_SMAXV ; Used in aarch64-simd.md. 484 UNSPEC_SMINV ; Used in aarch64-simd.md. 485 UNSPEC_UMAXV ; Used in aarch64-simd.md. 486 UNSPEC_UMINV ; Used in aarch64-simd.md. 487 UNSPEC_SHADD ; Used in aarch64-simd.md. 488 UNSPEC_UHADD ; Used in aarch64-simd.md. 489 UNSPEC_SRHADD ; Used in aarch64-simd.md. 490 UNSPEC_URHADD ; Used in aarch64-simd.md. 491 UNSPEC_SHSUB ; Used in aarch64-simd.md. 492 UNSPEC_UHSUB ; Used in aarch64-simd.md. 493 UNSPEC_ADDHN ; Used in aarch64-simd.md. 494 UNSPEC_RADDHN ; Used in aarch64-simd.md. 495 UNSPEC_SUBHN ; Used in aarch64-simd.md. 496 UNSPEC_RSUBHN ; Used in aarch64-simd.md. 497 UNSPEC_ADDHN2 ; Used in aarch64-simd.md. 498 UNSPEC_RADDHN2 ; Used in aarch64-simd.md. 499 UNSPEC_SUBHN2 ; Used in aarch64-simd.md. 500 UNSPEC_RSUBHN2 ; Used in aarch64-simd.md. 501 UNSPEC_SQDMULH ; Used in aarch64-simd.md. 502 UNSPEC_SQRDMULH ; Used in aarch64-simd.md. 503 UNSPEC_PMUL ; Used in aarch64-simd.md. 504 UNSPEC_FMULX ; Used in aarch64-simd.md. 505 UNSPEC_USQADD ; Used in aarch64-simd.md. 506 UNSPEC_SUQADD ; Used in aarch64-simd.md. 507 UNSPEC_SQXTUN ; Used in aarch64-simd.md. 508 UNSPEC_SQXTN ; Used in aarch64-simd.md. 509 UNSPEC_UQXTN ; Used in aarch64-simd.md. 510 UNSPEC_SSRA ; Used in aarch64-simd.md. 511 UNSPEC_USRA ; Used in aarch64-simd.md. 512 UNSPEC_SRSRA ; Used in aarch64-simd.md. 513 UNSPEC_URSRA ; Used in aarch64-simd.md. 514 UNSPEC_SRSHR ; Used in aarch64-simd.md. 515 UNSPEC_URSHR ; Used in aarch64-simd.md. 516 UNSPEC_SQSHLU ; Used in aarch64-simd.md. 517 UNSPEC_SQSHL ; Used in aarch64-simd.md. 518 UNSPEC_UQSHL ; Used in aarch64-simd.md. 519 UNSPEC_SQSHRUN ; Used in aarch64-simd.md. 520 UNSPEC_SQRSHRUN ; Used in aarch64-simd.md. 521 UNSPEC_SQSHRN ; Used in aarch64-simd.md. 522 UNSPEC_UQSHRN ; Used in aarch64-simd.md. 523 UNSPEC_SQRSHRN ; Used in aarch64-simd.md. 524 UNSPEC_UQRSHRN ; Used in aarch64-simd.md. 525 UNSPEC_SSHL ; Used in aarch64-simd.md. 526 UNSPEC_USHL ; Used in aarch64-simd.md. 527 UNSPEC_SRSHL ; Used in aarch64-simd.md. 528 UNSPEC_URSHL ; Used in aarch64-simd.md. 529 UNSPEC_SQRSHL ; Used in aarch64-simd.md. 530 UNSPEC_UQRSHL ; Used in aarch64-simd.md. 531 UNSPEC_SSLI ; Used in aarch64-simd.md. 532 UNSPEC_USLI ; Used in aarch64-simd.md. 533 UNSPEC_SSRI ; Used in aarch64-simd.md. 534 UNSPEC_USRI ; Used in aarch64-simd.md. 535 UNSPEC_SSHLL ; Used in aarch64-simd.md. 536 UNSPEC_USHLL ; Used in aarch64-simd.md. 537 UNSPEC_ADDP ; Used in aarch64-simd.md. 538 UNSPEC_TBL ; Used in vector permute patterns. 539 UNSPEC_TBX ; Used in vector permute patterns. 540 UNSPEC_CONCAT ; Used in vector permute patterns. 541 542 ;; The following permute unspecs are generated directly by 543 ;; aarch64_expand_vec_perm_const, so any changes to the underlying 544 ;; instructions would need a corresponding change there. 545 UNSPEC_ZIP1 ; Used in vector permute patterns. 546 UNSPEC_ZIP2 ; Used in vector permute patterns. 547 UNSPEC_UZP1 ; Used in vector permute patterns. 548 UNSPEC_UZP2 ; Used in vector permute patterns. 549 UNSPEC_TRN1 ; Used in vector permute patterns. 550 UNSPEC_TRN2 ; Used in vector permute patterns. 551 UNSPEC_EXT ; Used in vector permute patterns. 552 UNSPEC_REV64 ; Used in vector reverse patterns (permute). 553 UNSPEC_REV32 ; Used in vector reverse patterns (permute). 554 UNSPEC_REV16 ; Used in vector reverse patterns (permute). 555 556 UNSPEC_AESE ; Used in aarch64-simd.md. 557 UNSPEC_AESD ; Used in aarch64-simd.md. 558 UNSPEC_AESMC ; Used in aarch64-simd.md. 559 UNSPEC_AESIMC ; Used in aarch64-simd.md. 560 UNSPEC_SHA1C ; Used in aarch64-simd.md. 561 UNSPEC_SHA1M ; Used in aarch64-simd.md. 562 UNSPEC_SHA1P ; Used in aarch64-simd.md. 563 UNSPEC_SHA1H ; Used in aarch64-simd.md. 564 UNSPEC_SHA1SU0 ; Used in aarch64-simd.md. 565 UNSPEC_SHA1SU1 ; Used in aarch64-simd.md. 566 UNSPEC_SHA256H ; Used in aarch64-simd.md. 567 UNSPEC_SHA256H2 ; Used in aarch64-simd.md. 568 UNSPEC_SHA256SU0 ; Used in aarch64-simd.md. 569 UNSPEC_SHA256SU1 ; Used in aarch64-simd.md. 570 UNSPEC_PMULL ; Used in aarch64-simd.md. 571 UNSPEC_PMULL2 ; Used in aarch64-simd.md. 572 UNSPEC_REV_REGLIST ; Used in aarch64-simd.md. 573 UNSPEC_VEC_SHR ; Used in aarch64-simd.md. 574 UNSPEC_SQRDMLAH ; Used in aarch64-simd.md. 575 UNSPEC_SQRDMLSH ; Used in aarch64-simd.md. 576 UNSPEC_FMAXNM ; Used in aarch64-simd.md. 577 UNSPEC_FMINNM ; Used in aarch64-simd.md. 578 UNSPEC_SDOT ; Used in aarch64-simd.md. 579 UNSPEC_UDOT ; Used in aarch64-simd.md. 580 UNSPEC_SM3SS1 ; Used in aarch64-simd.md. 581 UNSPEC_SM3TT1A ; Used in aarch64-simd.md. 582 UNSPEC_SM3TT1B ; Used in aarch64-simd.md. 583 UNSPEC_SM3TT2A ; Used in aarch64-simd.md. 584 UNSPEC_SM3TT2B ; Used in aarch64-simd.md. 585 UNSPEC_SM3PARTW1 ; Used in aarch64-simd.md. 586 UNSPEC_SM3PARTW2 ; Used in aarch64-simd.md. 587 UNSPEC_SM4E ; Used in aarch64-simd.md. 588 UNSPEC_SM4EKEY ; Used in aarch64-simd.md. 589 UNSPEC_SHA512H ; Used in aarch64-simd.md. 590 UNSPEC_SHA512H2 ; Used in aarch64-simd.md. 591 UNSPEC_SHA512SU0 ; Used in aarch64-simd.md. 592 UNSPEC_SHA512SU1 ; Used in aarch64-simd.md. 593 UNSPEC_FMLAL ; Used in aarch64-simd.md. 594 UNSPEC_FMLSL ; Used in aarch64-simd.md. 595 UNSPEC_FMLAL2 ; Used in aarch64-simd.md. 596 UNSPEC_FMLSL2 ; Used in aarch64-simd.md. 597 UNSPEC_ADR ; Used in aarch64-sve.md. 598 UNSPEC_SEL ; Used in aarch64-sve.md. 599 UNSPEC_BRKA ; Used in aarch64-sve.md. 600 UNSPEC_BRKB ; Used in aarch64-sve.md. 601 UNSPEC_BRKN ; Used in aarch64-sve.md. 602 UNSPEC_BRKPA ; Used in aarch64-sve.md. 603 UNSPEC_BRKPB ; Used in aarch64-sve.md. 604 UNSPEC_PFIRST ; Used in aarch64-sve.md. 605 UNSPEC_PNEXT ; Used in aarch64-sve.md. 606 UNSPEC_CNTP ; Used in aarch64-sve.md. 607 UNSPEC_SADDV ; Used in aarch64-sve.md. 608 UNSPEC_UADDV ; Used in aarch64-sve.md. 609 UNSPEC_ANDV ; Used in aarch64-sve.md. 610 UNSPEC_IORV ; Used in aarch64-sve.md. 611 UNSPEC_XORV ; Used in aarch64-sve.md. 612 UNSPEC_ANDF ; Used in aarch64-sve.md. 613 UNSPEC_IORF ; Used in aarch64-sve.md. 614 UNSPEC_XORF ; Used in aarch64-sve.md. 615 UNSPEC_REVB ; Used in aarch64-sve.md. 616 UNSPEC_REVH ; Used in aarch64-sve.md. 617 UNSPEC_REVW ; Used in aarch64-sve.md. 618 UNSPEC_SMUL_HIGHPART ; Used in aarch64-sve.md. 619 UNSPEC_UMUL_HIGHPART ; Used in aarch64-sve.md. 620 UNSPEC_FMLA ; Used in aarch64-sve.md. 621 UNSPEC_FMLS ; Used in aarch64-sve.md. 622 UNSPEC_FEXPA ; Used in aarch64-sve.md. 623 UNSPEC_FMMLA ; Used in aarch64-sve.md. 624 UNSPEC_FTMAD ; Used in aarch64-sve.md. 625 UNSPEC_FTSMUL ; Used in aarch64-sve.md. 626 UNSPEC_FTSSEL ; Used in aarch64-sve.md. 627 UNSPEC_SMATMUL ; Used in aarch64-sve.md. 628 UNSPEC_UMATMUL ; Used in aarch64-sve.md. 629 UNSPEC_USMATMUL ; Used in aarch64-sve.md. 630 UNSPEC_TRN1Q ; Used in aarch64-sve.md. 631 UNSPEC_TRN2Q ; Used in aarch64-sve.md. 632 UNSPEC_UZP1Q ; Used in aarch64-sve.md. 633 UNSPEC_UZP2Q ; Used in aarch64-sve.md. 634 UNSPEC_ZIP1Q ; Used in aarch64-sve.md. 635 UNSPEC_ZIP2Q ; Used in aarch64-sve.md. 636 UNSPEC_TRN1_CONV ; Used in aarch64-sve.md. 637 UNSPEC_COND_CMPEQ_WIDE ; Used in aarch64-sve.md. 638 UNSPEC_COND_CMPGE_WIDE ; Used in aarch64-sve.md. 639 UNSPEC_COND_CMPGT_WIDE ; Used in aarch64-sve.md. 640 UNSPEC_COND_CMPHI_WIDE ; Used in aarch64-sve.md. 641 UNSPEC_COND_CMPHS_WIDE ; Used in aarch64-sve.md. 642 UNSPEC_COND_CMPLE_WIDE ; Used in aarch64-sve.md. 643 UNSPEC_COND_CMPLO_WIDE ; Used in aarch64-sve.md. 644 UNSPEC_COND_CMPLS_WIDE ; Used in aarch64-sve.md. 645 UNSPEC_COND_CMPLT_WIDE ; Used in aarch64-sve.md. 646 UNSPEC_COND_CMPNE_WIDE ; Used in aarch64-sve.md. 647 UNSPEC_COND_FABS ; Used in aarch64-sve.md. 648 UNSPEC_COND_FADD ; Used in aarch64-sve.md. 649 UNSPEC_COND_FCADD90 ; Used in aarch64-sve.md. 650 UNSPEC_COND_FCADD270 ; Used in aarch64-sve.md. 651 UNSPEC_COND_FCMEQ ; Used in aarch64-sve.md. 652 UNSPEC_COND_FCMGE ; Used in aarch64-sve.md. 653 UNSPEC_COND_FCMGT ; Used in aarch64-sve.md. 654 UNSPEC_COND_FCMLA ; Used in aarch64-sve.md. 655 UNSPEC_COND_FCMLA90 ; Used in aarch64-sve.md. 656 UNSPEC_COND_FCMLA180 ; Used in aarch64-sve.md. 657 UNSPEC_COND_FCMLA270 ; Used in aarch64-sve.md. 658 UNSPEC_COND_FCMLE ; Used in aarch64-sve.md. 659 UNSPEC_COND_FCMLT ; Used in aarch64-sve.md. 660 UNSPEC_COND_FCMNE ; Used in aarch64-sve.md. 661 UNSPEC_COND_FCMUO ; Used in aarch64-sve.md. 662 UNSPEC_COND_FCVT ; Used in aarch64-sve.md. 663 UNSPEC_COND_FCVTZS ; Used in aarch64-sve.md. 664 UNSPEC_COND_FCVTZU ; Used in aarch64-sve.md. 665 UNSPEC_COND_FDIV ; Used in aarch64-sve.md. 666 UNSPEC_COND_FMAX ; Used in aarch64-sve.md. 667 UNSPEC_COND_FMAXNM ; Used in aarch64-sve.md. 668 UNSPEC_COND_FMIN ; Used in aarch64-sve.md. 669 UNSPEC_COND_FMINNM ; Used in aarch64-sve.md. 670 UNSPEC_COND_FMLA ; Used in aarch64-sve.md. 671 UNSPEC_COND_FMLS ; Used in aarch64-sve.md. 672 UNSPEC_COND_FMUL ; Used in aarch64-sve.md. 673 UNSPEC_COND_FMULX ; Used in aarch64-sve.md. 674 UNSPEC_COND_FNEG ; Used in aarch64-sve.md. 675 UNSPEC_COND_FNMLA ; Used in aarch64-sve.md. 676 UNSPEC_COND_FNMLS ; Used in aarch64-sve.md. 677 UNSPEC_COND_FRECPX ; Used in aarch64-sve.md. 678 UNSPEC_COND_FRINTA ; Used in aarch64-sve.md. 679 UNSPEC_COND_FRINTI ; Used in aarch64-sve.md. 680 UNSPEC_COND_FRINTM ; Used in aarch64-sve.md. 681 UNSPEC_COND_FRINTN ; Used in aarch64-sve.md. 682 UNSPEC_COND_FRINTP ; Used in aarch64-sve.md. 683 UNSPEC_COND_FRINTX ; Used in aarch64-sve.md. 684 UNSPEC_COND_FRINTZ ; Used in aarch64-sve.md. 685 UNSPEC_COND_FSCALE ; Used in aarch64-sve.md. 686 UNSPEC_COND_FSQRT ; Used in aarch64-sve.md. 687 UNSPEC_COND_FSUB ; Used in aarch64-sve.md. 688 UNSPEC_COND_SCVTF ; Used in aarch64-sve.md. 689 UNSPEC_COND_UCVTF ; Used in aarch64-sve.md. 690 UNSPEC_LASTA ; Used in aarch64-sve.md. 691 UNSPEC_LASTB ; Used in aarch64-sve.md. 692 UNSPEC_ASHIFT_WIDE ; Used in aarch64-sve.md. 693 UNSPEC_ASHIFTRT_WIDE ; Used in aarch64-sve.md. 694 UNSPEC_LSHIFTRT_WIDE ; Used in aarch64-sve.md. 695 UNSPEC_LDFF1 ; Used in aarch64-sve.md. 696 UNSPEC_LDNF1 ; Used in aarch64-sve.md. 697 UNSPEC_FCADD90 ; Used in aarch64-simd.md. 698 UNSPEC_FCADD270 ; Used in aarch64-simd.md. 699 UNSPEC_FCMLA ; Used in aarch64-simd.md. 700 UNSPEC_FCMLA90 ; Used in aarch64-simd.md. 701 UNSPEC_FCMLA180 ; Used in aarch64-simd.md. 702 UNSPEC_FCMLA270 ; Used in aarch64-simd.md. 703 UNSPEC_ASRD ; Used in aarch64-sve.md. 704 UNSPEC_ADCLB ; Used in aarch64-sve2.md. 705 UNSPEC_ADCLT ; Used in aarch64-sve2.md. 706 UNSPEC_ADDHNB ; Used in aarch64-sve2.md. 707 UNSPEC_ADDHNT ; Used in aarch64-sve2.md. 708 UNSPEC_BDEP ; Used in aarch64-sve2.md. 709 UNSPEC_BEXT ; Used in aarch64-sve2.md. 710 UNSPEC_BGRP ; Used in aarch64-sve2.md. 711 UNSPEC_CADD270 ; Used in aarch64-sve2.md. 712 UNSPEC_CADD90 ; Used in aarch64-sve2.md. 713 UNSPEC_CDOT ; Used in aarch64-sve2.md. 714 UNSPEC_CDOT180 ; Used in aarch64-sve2.md. 715 UNSPEC_CDOT270 ; Used in aarch64-sve2.md. 716 UNSPEC_CDOT90 ; Used in aarch64-sve2.md. 717 UNSPEC_CMLA ; Used in aarch64-sve2.md. 718 UNSPEC_CMLA180 ; Used in aarch64-sve2.md. 719 UNSPEC_CMLA270 ; Used in aarch64-sve2.md. 720 UNSPEC_CMLA90 ; Used in aarch64-sve2.md. 721 UNSPEC_COND_FCVTLT ; Used in aarch64-sve2.md. 722 UNSPEC_COND_FCVTNT ; Used in aarch64-sve2.md. 723 UNSPEC_COND_FCVTX ; Used in aarch64-sve2.md. 724 UNSPEC_COND_FCVTXNT ; Used in aarch64-sve2.md. 725 UNSPEC_COND_FLOGB ; Used in aarch64-sve2.md. 726 UNSPEC_EORBT ; Used in aarch64-sve2.md. 727 UNSPEC_EORTB ; Used in aarch64-sve2.md. 728 UNSPEC_FADDP ; Used in aarch64-sve2.md. 729 UNSPEC_FMAXNMP ; Used in aarch64-sve2.md. 730 UNSPEC_FMAXP ; Used in aarch64-sve2.md. 731 UNSPEC_FMINNMP ; Used in aarch64-sve2.md. 732 UNSPEC_FMINP ; Used in aarch64-sve2.md. 733 UNSPEC_FMLALB ; Used in aarch64-sve2.md. 734 UNSPEC_FMLALT ; Used in aarch64-sve2.md. 735 UNSPEC_FMLSLB ; Used in aarch64-sve2.md. 736 UNSPEC_FMLSLT ; Used in aarch64-sve2.md. 737 UNSPEC_HISTCNT ; Used in aarch64-sve2.md. 738 UNSPEC_HISTSEG ; Used in aarch64-sve2.md. 739 UNSPEC_MATCH ; Used in aarch64-sve2.md. 740 UNSPEC_NMATCH ; Used in aarch64-sve2.md. 741 UNSPEC_PMULLB ; Used in aarch64-sve2.md. 742 UNSPEC_PMULLB_PAIR ; Used in aarch64-sve2.md. 743 UNSPEC_PMULLT ; Used in aarch64-sve2.md. 744 UNSPEC_PMULLT_PAIR ; Used in aarch64-sve2.md. 745 UNSPEC_RADDHNB ; Used in aarch64-sve2.md. 746 UNSPEC_RADDHNT ; Used in aarch64-sve2.md. 747 UNSPEC_RSHRNB ; Used in aarch64-sve2.md. 748 UNSPEC_RSHRNT ; Used in aarch64-sve2.md. 749 UNSPEC_RSUBHNB ; Used in aarch64-sve2.md. 750 UNSPEC_RSUBHNT ; Used in aarch64-sve2.md. 751 UNSPEC_SABDLB ; Used in aarch64-sve2.md. 752 UNSPEC_SABDLT ; Used in aarch64-sve2.md. 753 UNSPEC_SADDLB ; Used in aarch64-sve2.md. 754 UNSPEC_SADDLBT ; Used in aarch64-sve2.md. 755 UNSPEC_SADDLT ; Used in aarch64-sve2.md. 756 UNSPEC_SADDWB ; Used in aarch64-sve2.md. 757 UNSPEC_SADDWT ; Used in aarch64-sve2.md. 758 UNSPEC_SBCLB ; Used in aarch64-sve2.md. 759 UNSPEC_SBCLT ; Used in aarch64-sve2.md. 760 UNSPEC_SHRNB ; Used in aarch64-sve2.md. 761 UNSPEC_SHRNT ; Used in aarch64-sve2.md. 762 UNSPEC_SLI ; Used in aarch64-sve2.md. 763 UNSPEC_SMAXP ; Used in aarch64-sve2.md. 764 UNSPEC_SMINP ; Used in aarch64-sve2.md. 765 UNSPEC_SMULHRS ; Used in aarch64-sve2.md. 766 UNSPEC_SMULHS ; Used in aarch64-sve2.md. 767 UNSPEC_SMULLB ; Used in aarch64-sve2.md. 768 UNSPEC_SMULLT ; Used in aarch64-sve2.md. 769 UNSPEC_SQCADD270 ; Used in aarch64-sve2.md. 770 UNSPEC_SQCADD90 ; Used in aarch64-sve2.md. 771 UNSPEC_SQDMULLB ; Used in aarch64-sve2.md. 772 UNSPEC_SQDMULLBT ; Used in aarch64-sve2.md. 773 UNSPEC_SQDMULLT ; Used in aarch64-sve2.md. 774 UNSPEC_SQRDCMLAH ; Used in aarch64-sve2.md. 775 UNSPEC_SQRDCMLAH180 ; Used in aarch64-sve2.md. 776 UNSPEC_SQRDCMLAH270 ; Used in aarch64-sve2.md. 777 UNSPEC_SQRDCMLAH90 ; Used in aarch64-sve2.md. 778 UNSPEC_SQRSHRNB ; Used in aarch64-sve2.md. 779 UNSPEC_SQRSHRNT ; Used in aarch64-sve2.md. 780 UNSPEC_SQRSHRUNB ; Used in aarch64-sve2.md. 781 UNSPEC_SQRSHRUNT ; Used in aarch64-sve2.md. 782 UNSPEC_SQSHRNB ; Used in aarch64-sve2.md. 783 UNSPEC_SQSHRNT ; Used in aarch64-sve2.md. 784 UNSPEC_SQSHRUNB ; Used in aarch64-sve2.md. 785 UNSPEC_SQSHRUNT ; Used in aarch64-sve2.md. 786 UNSPEC_SQXTNB ; Used in aarch64-sve2.md. 787 UNSPEC_SQXTNT ; Used in aarch64-sve2.md. 788 UNSPEC_SQXTUNB ; Used in aarch64-sve2.md. 789 UNSPEC_SQXTUNT ; Used in aarch64-sve2.md. 790 UNSPEC_SRI ; Used in aarch64-sve2.md. 791 UNSPEC_SSHLLB ; Used in aarch64-sve2.md. 792 UNSPEC_SSHLLT ; Used in aarch64-sve2.md. 793 UNSPEC_SSUBLB ; Used in aarch64-sve2.md. 794 UNSPEC_SSUBLBT ; Used in aarch64-sve2.md. 795 UNSPEC_SSUBLT ; Used in aarch64-sve2.md. 796 UNSPEC_SSUBLTB ; Used in aarch64-sve2.md. 797 UNSPEC_SSUBWB ; Used in aarch64-sve2.md. 798 UNSPEC_SSUBWT ; Used in aarch64-sve2.md. 799 UNSPEC_SUBHNB ; Used in aarch64-sve2.md. 800 UNSPEC_SUBHNT ; Used in aarch64-sve2.md. 801 UNSPEC_TBL2 ; Used in aarch64-sve2.md. 802 UNSPEC_UABDLB ; Used in aarch64-sve2.md. 803 UNSPEC_UABDLT ; Used in aarch64-sve2.md. 804 UNSPEC_UADDLB ; Used in aarch64-sve2.md. 805 UNSPEC_UADDLT ; Used in aarch64-sve2.md. 806 UNSPEC_UADDWB ; Used in aarch64-sve2.md. 807 UNSPEC_UADDWT ; Used in aarch64-sve2.md. 808 UNSPEC_UMAXP ; Used in aarch64-sve2.md. 809 UNSPEC_UMINP ; Used in aarch64-sve2.md. 810 UNSPEC_UMULHRS ; Used in aarch64-sve2.md. 811 UNSPEC_UMULHS ; Used in aarch64-sve2.md. 812 UNSPEC_UMULLB ; Used in aarch64-sve2.md. 813 UNSPEC_UMULLT ; Used in aarch64-sve2.md. 814 UNSPEC_UQRSHRNB ; Used in aarch64-sve2.md. 815 UNSPEC_UQRSHRNT ; Used in aarch64-sve2.md. 816 UNSPEC_UQSHRNB ; Used in aarch64-sve2.md. 817 UNSPEC_UQSHRNT ; Used in aarch64-sve2.md. 818 UNSPEC_UQXTNB ; Used in aarch64-sve2.md. 819 UNSPEC_UQXTNT ; Used in aarch64-sve2.md. 820 UNSPEC_USHLLB ; Used in aarch64-sve2.md. 821 UNSPEC_USHLLT ; Used in aarch64-sve2.md. 822 UNSPEC_USUBLB ; Used in aarch64-sve2.md. 823 UNSPEC_USUBLT ; Used in aarch64-sve2.md. 824 UNSPEC_USUBWB ; Used in aarch64-sve2.md. 825 UNSPEC_USUBWT ; Used in aarch64-sve2.md. 826 UNSPEC_USDOT ; Used in aarch64-simd.md. 827 UNSPEC_SUDOT ; Used in aarch64-simd.md. 828 UNSPEC_BFDOT ; Used in aarch64-simd.md. 829 UNSPEC_BFMLALB ; Used in aarch64-sve.md. 830 UNSPEC_BFMLALT ; Used in aarch64-sve.md. 831 UNSPEC_BFMMLA ; Used in aarch64-sve.md. 832 UNSPEC_BFCVTN ; Used in aarch64-simd.md. 833 UNSPEC_BFCVTN2 ; Used in aarch64-simd.md. 834 UNSPEC_BFCVT ; Used in aarch64-simd.md. 835]) 836 837;; ------------------------------------------------------------------ 838;; Unspec enumerations for Atomics. They are here so that they can be 839;; used in the int_iterators for atomic operations. 840;; ------------------------------------------------------------------ 841 842(define_c_enum "unspecv" 843 [ 844 UNSPECV_LX ; Represent a load-exclusive. 845 UNSPECV_SX ; Represent a store-exclusive. 846 UNSPECV_LDA ; Represent an atomic load or load-acquire. 847 UNSPECV_STL ; Represent an atomic store or store-release. 848 UNSPECV_ATOMIC_CMPSW ; Represent an atomic compare swap. 849 UNSPECV_ATOMIC_EXCHG ; Represent an atomic exchange. 850 UNSPECV_ATOMIC_CAS ; Represent an atomic CAS. 851 UNSPECV_ATOMIC_SWP ; Represent an atomic SWP. 852 UNSPECV_ATOMIC_OP ; Represent an atomic operation. 853 UNSPECV_ATOMIC_LDOP_OR ; Represent an atomic load-or 854 UNSPECV_ATOMIC_LDOP_BIC ; Represent an atomic load-bic 855 UNSPECV_ATOMIC_LDOP_XOR ; Represent an atomic load-xor 856 UNSPECV_ATOMIC_LDOP_PLUS ; Represent an atomic load-add 857]) 858 859;; ------------------------------------------------------------------- 860;; Mode attributes 861;; ------------------------------------------------------------------- 862 863;; "e" for signaling operations, "" for quiet operations. 864(define_mode_attr e [(CCFP "") (CCFPE "e")]) 865 866;; In GPI templates, a string like "%<w>0" will expand to "%w0" in the 867;; 32-bit version and "%x0" in the 64-bit version. 868(define_mode_attr w [(QI "w") (HI "w") (SI "w") (DI "x") (SF "s") (DF "d")]) 869 870;; The size of access, in bytes. 871(define_mode_attr ldst_sz [(SI "4") (DI "8")]) 872;; Likewise for load/store pair. 873(define_mode_attr ldpstp_sz [(SI "8") (DI "16")]) 874 875;; For inequal width int to float conversion 876(define_mode_attr w1 [(HF "w") (SF "w") (DF "x")]) 877(define_mode_attr w2 [(HF "x") (SF "x") (DF "w")]) 878 879;; For width of fp registers in fcvt instruction 880(define_mode_attr fpw [(DI "s") (SI "d")]) 881 882(define_mode_attr short_mask [(HI "65535") (QI "255")]) 883 884;; For constraints used in scalar immediate vector moves 885(define_mode_attr hq [(HI "h") (QI "q")]) 886 887;; For doubling width of an integer mode 888(define_mode_attr DWI [(QI "HI") (HI "SI") (SI "DI") (DI "TI")]) 889 890(define_mode_attr fcvt_change_mode [(SI "df") (DI "sf")]) 891 892(define_mode_attr FCVT_CHANGE_MODE [(SI "DF") (DI "SF")]) 893 894;; For scalar usage of vector/FP registers 895(define_mode_attr v [(QI "b") (HI "h") (SI "s") (DI "d") 896 (HF "h") (SF "s") (DF "d") 897 (V8QI "") (V16QI "") 898 (V4HI "") (V8HI "") 899 (V2SI "") (V4SI "") 900 (V2DI "") (V2SF "") 901 (V4SF "") (V4HF "") 902 (V8HF "") (V2DF "")]) 903 904;; For scalar usage of vector/FP registers, narrowing 905(define_mode_attr vn2 [(QI "") (HI "b") (SI "h") (DI "s") 906 (V8QI "") (V16QI "") 907 (V4HI "") (V8HI "") 908 (V2SI "") (V4SI "") 909 (V2DI "") (V2SF "") 910 (V4SF "") (V2DF "")]) 911 912;; For scalar usage of vector/FP registers, widening 913(define_mode_attr vw2 [(DI "") (QI "h") (HI "s") (SI "d") 914 (V8QI "") (V16QI "") 915 (V4HI "") (V8HI "") 916 (V2SI "") (V4SI "") 917 (V2DI "") (V2SF "") 918 (V4SF "") (V2DF "")]) 919 920;; Register Type Name and Vector Arrangement Specifier for when 921;; we are doing scalar for DI and SIMD for SI (ignoring all but 922;; lane 0). 923(define_mode_attr rtn [(DI "d") (SI "")]) 924(define_mode_attr vas [(DI "") (SI ".2s")]) 925 926;; Map a vector to the number of units in it, if the size of the mode 927;; is constant. 928(define_mode_attr nunits [(V8QI "8") (V16QI "16") 929 (V4HI "4") (V8HI "8") 930 (V2SI "2") (V4SI "4") 931 (V2DI "2") 932 (V4HF "4") (V8HF "8") 933 (V4BF "4") (V8BF "8") 934 (V2SF "2") (V4SF "4") 935 (V1DF "1") (V2DF "2") 936 (DI "1") (DF "1")]) 937 938;; Map a mode to the number of bits in it, if the size of the mode 939;; is constant. 940(define_mode_attr bitsize [(V8QI "64") (V16QI "128") 941 (V4HI "64") (V8HI "128") 942 (V2SI "64") (V4SI "128") 943 (V2DI "128")]) 944 945;; Map a floating point or integer mode to the appropriate register name prefix 946(define_mode_attr s [(HF "h") (SF "s") (DF "d") (SI "s") (DI "d")]) 947 948;; Give the length suffix letter for a sign- or zero-extension. 949(define_mode_attr size [(QI "b") (HI "h") (SI "w")]) 950 951;; Give the number of bits in the mode 952(define_mode_attr sizen [(QI "8") (HI "16") (SI "32") (DI "64")]) 953 954;; Give the ordinal of the MSB in the mode 955(define_mode_attr sizem1 [(QI "#7") (HI "#15") (SI "#31") (DI "#63") 956 (HF "#15") (SF "#31") (DF "#63")]) 957 958;; The number of bits in a vector element, or controlled by a predicate 959;; element. 960(define_mode_attr elem_bits [(VNx16BI "8") (VNx8BI "16") 961 (VNx4BI "32") (VNx2BI "64") 962 (VNx16QI "8") (VNx8HI "16") 963 (VNx4SI "32") (VNx2DI "64") 964 (VNx8HF "16") (VNx4SF "32") (VNx2DF "64")]) 965 966;; Attribute to describe constants acceptable in logical operations 967(define_mode_attr lconst [(SI "K") (DI "L")]) 968 969;; Attribute to describe constants acceptable in logical and operations 970(define_mode_attr lconst2 [(SI "UsO") (DI "UsP")]) 971 972;; Map a mode to a specific constraint character. 973(define_mode_attr cmode [(QI "q") (HI "h") (SI "s") (DI "d")]) 974 975;; Map modes to Usg and Usj constraints for SISD right shifts 976(define_mode_attr cmode_simd [(SI "g") (DI "j")]) 977 978(define_mode_attr Vtype [(V8QI "8b") (V16QI "16b") 979 (V4HI "4h") (V8HI "8h") 980 (V4BF "4h") (V8BF "8h") 981 (V2SI "2s") (V4SI "4s") 982 (DI "1d") (DF "1d") 983 (V2DI "2d") (V2SF "2s") 984 (V4SF "4s") (V2DF "2d") 985 (V4HF "4h") (V8HF "8h")]) 986 987;; Map mode to type used in widening multiplies. 988(define_mode_attr Vcondtype [(V4HI "4h") (V8HI "4h") (V2SI "2s") (V4SI "2s")]) 989 990;; Map lane mode to name 991(define_mode_attr Qlane [(V4HI "_v4hi") (V8HI "q_v4hi") 992 (V2SI "_v2si") (V4SI "q_v2si")]) 993 994(define_mode_attr Vrevsuff [(V4HI "16") (V8HI "16") (V2SI "32") 995 (V4SI "32") (V2DI "64")]) 996 997(define_mode_attr Vmtype [(V8QI ".8b") (V16QI ".16b") 998 (V4HI ".4h") (V8HI ".8h") 999 (V2SI ".2s") (V4SI ".4s") 1000 (V2DI ".2d") (V4HF ".4h") 1001 (V8HF ".8h") (V4BF ".4h") 1002 (V8BF ".8h") (V2SF ".2s") 1003 (V4SF ".4s") (V2DF ".2d") 1004 (DI "") (SI "") 1005 (HI "") (QI "") 1006 (TI "") (HF "") 1007 (SF "") (DF "")]) 1008 1009;; Register suffix narrowed modes for VQN. 1010(define_mode_attr Vmntype [(V8HI ".8b") (V4SI ".4h") 1011 (V2DI ".2s") 1012 (DI "") (SI "") 1013 (HI "")]) 1014 1015;; Mode-to-individual element type mapping. 1016(define_mode_attr Vetype [(V8QI "b") (V16QI "b") 1017 (V4HI "h") (V8HI "h") 1018 (V2SI "s") (V4SI "s") 1019 (V2DI "d") 1020 (V4HF "h") (V8HF "h") 1021 (V2SF "s") (V4SF "s") 1022 (V2DF "d") 1023 (VNx16BI "b") (VNx8BI "h") (VNx4BI "s") (VNx2BI "d") 1024 (VNx16QI "b") (VNx8QI "b") (VNx4QI "b") (VNx2QI "b") 1025 (VNx8HI "h") (VNx4HI "h") (VNx2HI "h") 1026 (VNx8HF "h") (VNx4HF "h") (VNx2HF "h") 1027 (VNx8BF "h") 1028 (VNx4SI "s") (VNx2SI "s") 1029 (VNx4SF "s") (VNx2SF "s") 1030 (VNx2DI "d") 1031 (VNx2DF "d") 1032 (BF "h") (V4BF "h") (V8BF "h") 1033 (HF "h") 1034 (SF "s") (DF "d") 1035 (QI "b") (HI "h") 1036 (SI "s") (DI "d")]) 1037 1038;; Like Vetype, but map to types that are a quarter of the element size. 1039(define_mode_attr Vetype_fourth [(VNx4SI "b") (VNx2DI "h")]) 1040 1041;; Equivalent of "size" for a vector element. 1042(define_mode_attr Vesize [(VNx16QI "b") (VNx8QI "b") (VNx4QI "b") (VNx2QI "b") 1043 (VNx8HI "h") (VNx4HI "h") (VNx2HI "h") 1044 (VNx8HF "h") (VNx4HF "h") (VNx2HF "h") 1045 (VNx8BF "h") 1046 (VNx4SI "w") (VNx2SI "w") 1047 (VNx4SF "w") (VNx2SF "w") 1048 (VNx2DI "d") 1049 (VNx2DF "d") 1050 (VNx32QI "b") (VNx48QI "b") (VNx64QI "b") 1051 (VNx16HI "h") (VNx24HI "h") (VNx32HI "h") 1052 (VNx16HF "h") (VNx24HF "h") (VNx32HF "h") 1053 (VNx16BF "h") (VNx24BF "h") (VNx32BF "h") 1054 (VNx8SI "w") (VNx12SI "w") (VNx16SI "w") 1055 (VNx8SF "w") (VNx12SF "w") (VNx16SF "w") 1056 (VNx4DI "d") (VNx6DI "d") (VNx8DI "d") 1057 (VNx4DF "d") (VNx6DF "d") (VNx8DF "d")]) 1058 1059;; The Z register suffix for an SVE mode's element container, i.e. the 1060;; Vetype of full SVE modes that have the same number of elements. 1061(define_mode_attr Vctype [(VNx16QI "b") (VNx8QI "h") (VNx4QI "s") (VNx2QI "d") 1062 (VNx8HI "h") (VNx4HI "s") (VNx2HI "d") 1063 (VNx8HF "h") (VNx4HF "s") (VNx2HF "d") 1064 (VNx8BF "h") 1065 (VNx4SI "s") (VNx2SI "d") 1066 (VNx4SF "s") (VNx2SF "d") 1067 (VNx2DI "d") 1068 (VNx2DF "d")]) 1069 1070;; Vetype is used everywhere in scheduling type and assembly output, 1071;; sometimes they are not the same, for example HF modes on some 1072;; instructions. stype is defined to represent scheduling type 1073;; more accurately. 1074(define_mode_attr stype [(V8QI "b") (V16QI "b") (V4HI "s") (V8HI "s") 1075 (V2SI "s") (V4SI "s") (V2DI "d") (V4HF "s") 1076 (V8HF "s") (V2SF "s") (V4SF "s") (V2DF "d") 1077 (HF "s") (SF "s") (DF "d") (QI "b") (HI "s") 1078 (SI "s") (DI "d")]) 1079 1080;; Mode-to-bitwise operation type mapping. 1081(define_mode_attr Vbtype [(V8QI "8b") (V16QI "16b") 1082 (V4HI "8b") (V8HI "16b") 1083 (V2SI "8b") (V4SI "16b") 1084 (V2DI "16b") (V4HF "8b") 1085 (V8HF "16b") (V2SF "8b") 1086 (V4SF "16b") (V2DF "16b") 1087 (DI "8b") (DF "8b") 1088 (SI "8b") (SF "8b") 1089 (V4BF "8b") (V8BF "16b")]) 1090 1091;; Define element mode for each vector mode. 1092(define_mode_attr VEL [(V8QI "QI") (V16QI "QI") 1093 (V4HI "HI") (V8HI "HI") 1094 (V2SI "SI") (V4SI "SI") 1095 (DI "DI") (V2DI "DI") 1096 (V4HF "HF") (V8HF "HF") 1097 (V2SF "SF") (V4SF "SF") 1098 (DF "DF") (V2DF "DF") 1099 (SI "SI") (HI "HI") 1100 (QI "QI") 1101 (V4BF "BF") (V8BF "BF") 1102 (VNx16QI "QI") (VNx8QI "QI") (VNx4QI "QI") (VNx2QI "QI") 1103 (VNx8HI "HI") (VNx4HI "HI") (VNx2HI "HI") 1104 (VNx8HF "HF") (VNx4HF "HF") (VNx2HF "HF") 1105 (VNx8BF "BF") 1106 (VNx4SI "SI") (VNx2SI "SI") 1107 (VNx4SF "SF") (VNx2SF "SF") 1108 (VNx2DI "DI") 1109 (VNx2DF "DF")]) 1110 1111;; Define element mode for each vector mode (lower case). 1112(define_mode_attr Vel [(V8QI "qi") (V16QI "qi") 1113 (V4HI "hi") (V8HI "hi") 1114 (V2SI "si") (V4SI "si") 1115 (DI "di") (V2DI "di") 1116 (V4HF "hf") (V8HF "hf") 1117 (V2SF "sf") (V4SF "sf") 1118 (V2DF "df") (DF "df") 1119 (SI "si") (HI "hi") 1120 (QI "qi") 1121 (V4BF "bf") (V8BF "bf") 1122 (VNx16QI "qi") (VNx8QI "qi") (VNx4QI "qi") (VNx2QI "qi") 1123 (VNx8HI "hi") (VNx4HI "hi") (VNx2HI "hi") 1124 (VNx8HF "hf") (VNx4HF "hf") (VNx2HF "hf") 1125 (VNx8BF "bf") 1126 (VNx4SI "si") (VNx2SI "si") 1127 (VNx4SF "sf") (VNx2SF "sf") 1128 (VNx2DI "di") 1129 (VNx2DF "df")]) 1130 1131;; Element mode with floating-point values replaced by like-sized integers. 1132(define_mode_attr VEL_INT [(VNx16QI "QI") 1133 (VNx8HI "HI") (VNx8HF "HI") (VNx8BF "HI") 1134 (VNx4SI "SI") (VNx4SF "SI") 1135 (VNx2DI "DI") (VNx2DF "DI")]) 1136 1137;; Gives the mode of the 128-bit lowpart of an SVE vector. 1138(define_mode_attr V128 [(VNx16QI "V16QI") 1139 (VNx8HI "V8HI") (VNx8HF "V8HF") (VNx8BF "V8BF") 1140 (VNx4SI "V4SI") (VNx4SF "V4SF") 1141 (VNx2DI "V2DI") (VNx2DF "V2DF")]) 1142 1143;; ...and again in lower case. 1144(define_mode_attr v128 [(VNx16QI "v16qi") 1145 (VNx8HI "v8hi") (VNx8HF "v8hf") (VNx8BF "v8bf") 1146 (VNx4SI "v4si") (VNx4SF "v4sf") 1147 (VNx2DI "v2di") (VNx2DF "v2df")]) 1148 1149;; 64-bit container modes the inner or scalar source mode. 1150(define_mode_attr VCOND [(HI "V4HI") (SI "V2SI") 1151 (V4HI "V4HI") (V8HI "V4HI") 1152 (V2SI "V2SI") (V4SI "V2SI") 1153 (DI "DI") (V2DI "DI") 1154 (V2SF "V2SF") (V4SF "V2SF") 1155 (V2DF "DF")]) 1156 1157;; 128-bit container modes the inner or scalar source mode. 1158(define_mode_attr VCONQ [(V8QI "V16QI") (V16QI "V16QI") 1159 (V4HI "V8HI") (V8HI "V8HI") 1160 (V2SI "V4SI") (V4SI "V4SI") 1161 (DI "V2DI") (V2DI "V2DI") 1162 (V4HF "V8HF") (V8HF "V8HF") 1163 (V2SF "V2SF") (V4SF "V4SF") 1164 (V2DF "V2DF") (SI "V4SI") 1165 (HI "V8HI") (QI "V16QI")]) 1166 1167;; Half modes of all vector modes. 1168(define_mode_attr VHALF [(V8QI "V4QI") (V16QI "V8QI") 1169 (V4HI "V2HI") (V8HI "V4HI") 1170 (V2SI "SI") (V4SI "V2SI") 1171 (V2DI "DI") (V2SF "SF") 1172 (V4SF "V2SF") (V4HF "V2HF") 1173 (V8HF "V4HF") (V2DF "DF") 1174 (V8BF "V4BF")]) 1175 1176;; Half modes of all vector modes, in lower-case. 1177(define_mode_attr Vhalf [(V8QI "v4qi") (V16QI "v8qi") 1178 (V4HI "v2hi") (V8HI "v4hi") 1179 (V8HF "v4hf") (V8BF "v4bf") 1180 (V2SI "si") (V4SI "v2si") 1181 (V2DI "di") (V2SF "sf") 1182 (V4SF "v2sf") (V2DF "df")]) 1183 1184;; Double modes of vector modes. 1185(define_mode_attr VDBL [(V8QI "V16QI") (V4HI "V8HI") 1186 (V4HF "V8HF") (V4BF "V8BF") 1187 (V2SI "V4SI") (V2SF "V4SF") 1188 (SI "V2SI") (DI "V2DI") 1189 (DF "V2DF")]) 1190 1191;; Register suffix for double-length mode. 1192(define_mode_attr Vdtype [(V4HF "8h") (V2SF "4s")]) 1193 1194;; Double modes of vector modes (lower case). 1195(define_mode_attr Vdbl [(V8QI "v16qi") (V4HI "v8hi") 1196 (V4HF "v8hf") (V4BF "v8bf") 1197 (V2SI "v4si") (V2SF "v4sf") 1198 (SI "v2si") (DI "v2di") 1199 (DF "v2df")]) 1200 1201;; Modes with double-width elements. 1202(define_mode_attr VDBLW [(V8QI "V4HI") (V16QI "V8HI") 1203 (V4HI "V2SI") (V8HI "V4SI") 1204 (V2SI "DI") (V4SI "V2DI")]) 1205 1206;; Narrowed modes for VDN. 1207(define_mode_attr VNARROWD [(V4HI "V8QI") (V2SI "V4HI") 1208 (DI "V2SI")]) 1209 1210;; Narrowed double-modes for VQN (Used for XTN). 1211(define_mode_attr VNARROWQ [(V8HI "V8QI") (V4SI "V4HI") 1212 (V2DI "V2SI") 1213 (DI "SI") (SI "HI") 1214 (HI "QI")]) 1215(define_mode_attr Vnarrowq [(V8HI "v8qi") (V4SI "v4hi") 1216 (V2DI "v2si")]) 1217 1218;; Narrowed quad-modes for VQN (Used for XTN2). 1219(define_mode_attr VNARROWQ2 [(V8HI "V16QI") (V4SI "V8HI") 1220 (V2DI "V4SI")]) 1221 1222;; Narrowed modes of vector modes. 1223(define_mode_attr VNARROW [(VNx8HI "VNx16QI") 1224 (VNx4SI "VNx8HI") (VNx4SF "VNx8HF") 1225 (VNx2DI "VNx4SI") (VNx2DF "VNx4SF")]) 1226 1227;; Register suffix narrowed modes for VQN. 1228(define_mode_attr Vntype [(V8HI "8b") (V4SI "4h") 1229 (V2DI "2s")]) 1230 1231;; Register suffix narrowed modes for VQN. 1232(define_mode_attr V2ntype [(V8HI "16b") (V4SI "8h") 1233 (V2DI "4s")]) 1234 1235;; Widened modes of vector modes. 1236(define_mode_attr VWIDE [(V8QI "V8HI") (V4HI "V4SI") 1237 (V2SI "V2DI") (V16QI "V8HI") 1238 (V8HI "V4SI") (V4SI "V2DI") 1239 (HI "SI") (SI "DI") 1240 (V8HF "V4SF") (V4SF "V2DF") 1241 (V4HF "V4SF") (V2SF "V2DF") 1242 (VNx8HF "VNx4SF") (VNx4SF "VNx2DF") 1243 (VNx16QI "VNx8HI") (VNx8HI "VNx4SI") 1244 (VNx4SI "VNx2DI") 1245 (VNx16BI "VNx8BI") (VNx8BI "VNx4BI") 1246 (VNx4BI "VNx2BI")]) 1247 1248;; Predicate mode associated with VWIDE. 1249(define_mode_attr VWIDE_PRED [(VNx8HF "VNx4BI") (VNx4SF "VNx2BI")]) 1250 1251;; Widened modes of vector modes, lowercase 1252(define_mode_attr Vwide [(V2SF "v2df") (V4HF "v4sf") 1253 (VNx16QI "vnx8hi") (VNx8HI "vnx4si") 1254 (VNx4SI "vnx2di") 1255 (VNx8HF "vnx4sf") (VNx4SF "vnx2df") 1256 (VNx16BI "vnx8bi") (VNx8BI "vnx4bi") 1257 (VNx4BI "vnx2bi")]) 1258 1259;; Widened mode register suffixes for VD_BHSI/VQW/VQ_HSF. 1260(define_mode_attr Vwtype [(V8QI "8h") (V4HI "4s") 1261 (V2SI "2d") (V16QI "8h") 1262 (V8HI "4s") (V4SI "2d") 1263 (V8HF "4s") (V4SF "2d")]) 1264 1265;; SVE vector after narrowing. 1266(define_mode_attr Ventype [(VNx8HI "b") 1267 (VNx4SI "h") (VNx4SF "h") 1268 (VNx2DI "s") (VNx2DF "s")]) 1269 1270;; SVE vector after widening. 1271(define_mode_attr Vewtype [(VNx16QI "h") 1272 (VNx8HI "s") (VNx8HF "s") 1273 (VNx4SI "d") (VNx4SF "d") 1274 (VNx2DI "q")]) 1275 1276;; Widened mode register suffixes for VDW/VQW. 1277(define_mode_attr Vmwtype [(V8QI ".8h") (V4HI ".4s") 1278 (V2SI ".2d") (V16QI ".8h") 1279 (V8HI ".4s") (V4SI ".2d") 1280 (V4HF ".4s") (V2SF ".2d") 1281 (SI "") (HI "")]) 1282 1283;; Lower part register suffixes for VQW/VQ_HSF. 1284(define_mode_attr Vhalftype [(V16QI "8b") (V8HI "4h") 1285 (V4SI "2s") (V8HF "4h") 1286 (V4SF "2s")]) 1287 1288;; Define corresponding core/FP element mode for each vector mode. 1289(define_mode_attr vw [(V8QI "w") (V16QI "w") 1290 (V4HI "w") (V8HI "w") 1291 (V2SI "w") (V4SI "w") 1292 (DI "x") (V2DI "x") 1293 (V2SF "s") (V4SF "s") 1294 (V2DF "d")]) 1295 1296;; Corresponding core element mode for each vector mode. This is a 1297;; variation on <vw> mapping FP modes to GP regs. 1298(define_mode_attr vwcore [(V8QI "w") (V16QI "w") 1299 (V4HI "w") (V8HI "w") 1300 (V2SI "w") (V4SI "w") 1301 (DI "x") (V2DI "x") 1302 (V4HF "w") (V8HF "w") 1303 (V2SF "w") (V4SF "w") 1304 (V2DF "x") 1305 (VNx16QI "w") (VNx8QI "w") (VNx4QI "w") (VNx2QI "w") 1306 (VNx8HI "w") (VNx4HI "w") (VNx2HI "w") 1307 (VNx8HF "w") (VNx4HF "w") (VNx2HF "w") 1308 (VNx8BF "w") 1309 (VNx4SI "w") (VNx2SI "w") 1310 (VNx4SF "w") (VNx2SF "w") 1311 (VNx2DI "x") 1312 (VNx2DF "x")]) 1313 1314;; Like vwcore, but for the container mode rather than the element mode. 1315(define_mode_attr vccore [(VNx16QI "w") (VNx8QI "w") (VNx4QI "w") (VNx2QI "x") 1316 (VNx8HI "w") (VNx4HI "w") (VNx2HI "x") 1317 (VNx4SI "w") (VNx2SI "x") 1318 (VNx2DI "x")]) 1319 1320;; Double vector types for ALLX. 1321(define_mode_attr Vallxd [(QI "8b") (HI "4h") (SI "2s")]) 1322 1323;; Mode with floating-point values replaced by like-sized integers. 1324(define_mode_attr V_INT_EQUIV [(V8QI "V8QI") (V16QI "V16QI") 1325 (V4HI "V4HI") (V8HI "V8HI") 1326 (V2SI "V2SI") (V4SI "V4SI") 1327 (DI "DI") (V2DI "V2DI") 1328 (V4HF "V4HI") (V8HF "V8HI") 1329 (V4BF "V4HI") (V8BF "V8HI") 1330 (V2SF "V2SI") (V4SF "V4SI") 1331 (DF "DI") (V2DF "V2DI") 1332 (SF "SI") (SI "SI") 1333 (HF "HI") 1334 (VNx16QI "VNx16QI") 1335 (VNx8HI "VNx8HI") (VNx8HF "VNx8HI") 1336 (VNx8BF "VNx8HI") 1337 (VNx4SI "VNx4SI") (VNx4SF "VNx4SI") 1338 (VNx2DI "VNx2DI") (VNx2DF "VNx2DI") 1339]) 1340 1341;; Lower case mode with floating-point values replaced by like-sized integers. 1342(define_mode_attr v_int_equiv [(V8QI "v8qi") (V16QI "v16qi") 1343 (V4HI "v4hi") (V8HI "v8hi") 1344 (V2SI "v2si") (V4SI "v4si") 1345 (DI "di") (V2DI "v2di") 1346 (V4HF "v4hi") (V8HF "v8hi") 1347 (V4BF "v4hi") (V8BF "v8hi") 1348 (V2SF "v2si") (V4SF "v4si") 1349 (DF "di") (V2DF "v2di") 1350 (SF "si") 1351 (VNx16QI "vnx16qi") 1352 (VNx8HI "vnx8hi") (VNx8HF "vnx8hi") 1353 (VNx8BF "vnx8hi") 1354 (VNx4SI "vnx4si") (VNx4SF "vnx4si") 1355 (VNx2DI "vnx2di") (VNx2DF "vnx2di") 1356]) 1357 1358;; Floating-point equivalent of selected modes. 1359(define_mode_attr V_FP_EQUIV [(VNx8HI "VNx8HF") (VNx8HF "VNx8HF") 1360 (VNx8BF "VNx8HF") 1361 (VNx4SI "VNx4SF") (VNx4SF "VNx4SF") 1362 (VNx2DI "VNx2DF") (VNx2DF "VNx2DF")]) 1363(define_mode_attr v_fp_equiv [(VNx8HI "vnx8hf") (VNx8HF "vnx8hf") 1364 (VNx8BF "vnx8hf") 1365 (VNx4SI "vnx4sf") (VNx4SF "vnx4sf") 1366 (VNx2DI "vnx2df") (VNx2DF "vnx2df")]) 1367 1368;; Maps full and partial vector modes of any element type to a full-vector 1369;; integer mode with the same number of units. 1370(define_mode_attr V_INT_CONTAINER [(VNx16QI "VNx16QI") (VNx8QI "VNx8HI") 1371 (VNx4QI "VNx4SI") (VNx2QI "VNx2DI") 1372 (VNx8HI "VNx8HI") (VNx4HI "VNx4SI") 1373 (VNx2HI "VNx2DI") 1374 (VNx4SI "VNx4SI") (VNx2SI "VNx2DI") 1375 (VNx2DI "VNx2DI") 1376 (VNx8HF "VNx8HI") (VNx4HF "VNx4SI") 1377 (VNx2HF "VNx2DI") 1378 (VNx4SF "VNx4SI") (VNx2SF "VNx2DI") 1379 (VNx2DF "VNx2DI")]) 1380 1381;; Lower-case version of V_INT_CONTAINER. 1382(define_mode_attr v_int_container [(VNx16QI "vnx16qi") (VNx8QI "vnx8hi") 1383 (VNx4QI "vnx4si") (VNx2QI "vnx2di") 1384 (VNx8HI "vnx8hi") (VNx4HI "vnx4si") 1385 (VNx2HI "vnx2di") 1386 (VNx4SI "vnx4si") (VNx2SI "vnx2di") 1387 (VNx2DI "vnx2di") 1388 (VNx8HF "vnx8hi") (VNx4HF "vnx4si") 1389 (VNx2HF "vnx2di") 1390 (VNx4SF "vnx4si") (VNx2SF "vnx2di") 1391 (VNx2DF "vnx2di")]) 1392 1393;; Mode for vector conditional operations where the comparison has 1394;; different type from the lhs. 1395(define_mode_attr V_cmp_mixed [(V2SI "V2SF") (V4SI "V4SF") 1396 (V2DI "V2DF") (V2SF "V2SI") 1397 (V4SF "V4SI") (V2DF "V2DI")]) 1398 1399(define_mode_attr v_cmp_mixed [(V2SI "v2sf") (V4SI "v4sf") 1400 (V2DI "v2df") (V2SF "v2si") 1401 (V4SF "v4si") (V2DF "v2di")]) 1402 1403;; Lower case element modes (as used in shift immediate patterns). 1404(define_mode_attr ve_mode [(V8QI "qi") (V16QI "qi") 1405 (V4HI "hi") (V8HI "hi") 1406 (V2SI "si") (V4SI "si") 1407 (DI "di") (V2DI "di") 1408 (QI "qi") (HI "hi") 1409 (SI "si")]) 1410 1411;; Vm for lane instructions is restricted to FP_LO_REGS. 1412(define_mode_attr vwx [(V4HI "x") (V8HI "x") (HI "x") 1413 (V2SI "w") (V4SI "w") (SI "w")]) 1414 1415(define_mode_attr Vendreg [(OI "T") (CI "U") (XI "V")]) 1416 1417;; This is both the number of Q-Registers needed to hold the corresponding 1418;; opaque large integer mode, and the number of elements touched by the 1419;; ld..._lane and st..._lane operations. 1420(define_mode_attr nregs [(OI "2") (CI "3") (XI "4")]) 1421 1422;; Mode for atomic operation suffixes 1423(define_mode_attr atomic_sfx 1424 [(QI "b") (HI "h") (SI "") (DI "")]) 1425 1426(define_mode_attr fcvt_target [(V2DF "v2di") (V4SF "v4si") (V2SF "v2si") 1427 (V2DI "v2df") (V4SI "v4sf") (V2SI "v2sf") 1428 (SF "si") (DF "di") (SI "sf") (DI "df") 1429 (V4HF "v4hi") (V8HF "v8hi") (V4HI "v4hf") 1430 (V8HI "v8hf") (HF "hi") (HI "hf")]) 1431(define_mode_attr FCVT_TARGET [(V2DF "V2DI") (V4SF "V4SI") (V2SF "V2SI") 1432 (V2DI "V2DF") (V4SI "V4SF") (V2SI "V2SF") 1433 (SF "SI") (DF "DI") (SI "SF") (DI "DF") 1434 (V4HF "V4HI") (V8HF "V8HI") (V4HI "V4HF") 1435 (V8HI "V8HF") (HF "HI") (HI "HF")]) 1436 1437 1438;; for the inequal width integer to fp conversions 1439(define_mode_attr fcvt_iesize [(HF "di") (SF "di") (DF "si")]) 1440(define_mode_attr FCVT_IESIZE [(HF "DI") (SF "DI") (DF "SI")]) 1441 1442(define_mode_attr VSWAP_WIDTH [(V8QI "V16QI") (V16QI "V8QI") 1443 (V4HI "V8HI") (V8HI "V4HI") 1444 (V8BF "V4BF") (V4BF "V8BF") 1445 (V2SI "V4SI") (V4SI "V2SI") 1446 (DI "V2DI") (V2DI "DI") 1447 (V2SF "V4SF") (V4SF "V2SF") 1448 (V4HF "V8HF") (V8HF "V4HF") 1449 (DF "V2DF") (V2DF "DF")]) 1450 1451(define_mode_attr vswap_width_name [(V8QI "to_128") (V16QI "to_64") 1452 (V4HI "to_128") (V8HI "to_64") 1453 (V2SI "to_128") (V4SI "to_64") 1454 (DI "to_128") (V2DI "to_64") 1455 (V4HF "to_128") (V8HF "to_64") 1456 (V2SF "to_128") (V4SF "to_64") 1457 (V4BF "to_128") (V8BF "to_64") 1458 (DF "to_128") (V2DF "to_64")]) 1459 1460;; For certain vector-by-element multiplication instructions we must 1461;; constrain the 16-bit cases to use only V0-V15. This is covered by 1462;; the 'x' constraint. All other modes may use the 'w' constraint. 1463(define_mode_attr h_con [(V2SI "w") (V4SI "w") 1464 (V4HI "x") (V8HI "x") 1465 (V4HF "x") (V8HF "x") 1466 (V2SF "w") (V4SF "w") 1467 (V2DF "w") (DF "w")]) 1468 1469;; Defined to 'f' for types whose element type is a float type. 1470(define_mode_attr f [(V8QI "") (V16QI "") 1471 (V4HI "") (V8HI "") 1472 (V2SI "") (V4SI "") 1473 (DI "") (V2DI "") 1474 (V4HF "f") (V8HF "f") 1475 (V2SF "f") (V4SF "f") 1476 (V2DF "f") (DF "f")]) 1477 1478;; Defined to '_fp' for types whose element type is a float type. 1479(define_mode_attr fp [(V8QI "") (V16QI "") 1480 (V4HI "") (V8HI "") 1481 (V2SI "") (V4SI "") 1482 (DI "") (V2DI "") 1483 (V4HF "_fp") (V8HF "_fp") 1484 (V2SF "_fp") (V4SF "_fp") 1485 (V2DF "_fp") (DF "_fp") 1486 (SF "_fp")]) 1487 1488;; Defined to '_q' for 128-bit types. 1489(define_mode_attr q [(V8QI "") (V16QI "_q") 1490 (V4HI "") (V8HI "_q") 1491 (V4BF "") (V8BF "_q") 1492 (V2SI "") (V4SI "_q") 1493 (DI "") (V2DI "_q") 1494 (V4HF "") (V8HF "_q") 1495 (V4BF "") (V8BF "_q") 1496 (V2SF "") (V4SF "_q") 1497 (V2DF "_q") 1498 (QI "") (HI "") (SI "") (DI "") (HF "") (SF "") (DF "")]) 1499 1500(define_mode_attr vp [(V8QI "v") (V16QI "v") 1501 (V4HI "v") (V8HI "v") 1502 (V2SI "p") (V4SI "v") 1503 (V2DI "p") (V2DF "p") 1504 (V2SF "p") (V4SF "v") 1505 (V4HF "v") (V8HF "v")]) 1506 1507(define_mode_attr vsi2qi [(V2SI "v8qi") (V4SI "v16qi") 1508 (VNx4SI "vnx16qi") (VNx2DI "vnx8hi")]) 1509(define_mode_attr VSI2QI [(V2SI "V8QI") (V4SI "V16QI") 1510 (VNx4SI "VNx16QI") (VNx2DI "VNx8HI")]) 1511 1512 1513;; Register suffix for DOTPROD input types from the return type. 1514(define_mode_attr Vdottype [(V2SI "8b") (V4SI "16b")]) 1515 1516;; Register suffix for BFDOT input types from the return type. 1517(define_mode_attr Vbfdottype [(V2SF "4h") (V4SF "8h")]) 1518 1519;; Sum of lengths of instructions needed to move vector registers of a mode. 1520(define_mode_attr insn_count [(OI "8") (CI "12") (XI "16")]) 1521 1522;; -fpic small model GOT reloc modifers: gotpage_lo15/lo14 for ILP64/32. 1523;; No need of iterator for -fPIC as it use got_lo12 for both modes. 1524(define_mode_attr got_modifier [(SI "gotpage_lo14") (DI "gotpage_lo15")]) 1525 1526;; Width of 2nd and 3rd arguments to fp16 vector multiply add/sub 1527(define_mode_attr VFMLA_W [(V2SF "V4HF") (V4SF "V8HF")]) 1528 1529;; Width of 2nd and 3rd arguments to bf16 vector multiply add/sub 1530(define_mode_attr VBFMLA_W [(V2SF "V4BF") (V4SF "V8BF")]) 1531 1532(define_mode_attr VFMLA_SEL_W [(V2SF "V2HF") (V4SF "V4HF")]) 1533 1534(define_mode_attr f16quad [(V2SF "") (V4SF "q")]) 1535 1536(define_mode_attr isquadop [(V8QI "") (V16QI "q") (V4BF "") (V8BF "q")]) 1537 1538(define_code_attr f16mac [(plus "a") (minus "s")]) 1539 1540;; Map smax to smin and umax to umin. 1541(define_code_attr max_opp [(smax "smin") (umax "umin")]) 1542 1543;; Same as above, but louder. 1544(define_code_attr MAX_OPP [(smax "SMIN") (umax "UMIN")]) 1545 1546;; The number of subvectors in an SVE_STRUCT. 1547(define_mode_attr vector_count [(VNx32QI "2") (VNx16HI "2") 1548 (VNx8SI "2") (VNx4DI "2") 1549 (VNx16BF "2") 1550 (VNx16HF "2") (VNx8SF "2") (VNx4DF "2") 1551 (VNx48QI "3") (VNx24HI "3") 1552 (VNx12SI "3") (VNx6DI "3") 1553 (VNx24BF "3") 1554 (VNx24HF "3") (VNx12SF "3") (VNx6DF "3") 1555 (VNx64QI "4") (VNx32HI "4") 1556 (VNx16SI "4") (VNx8DI "4") 1557 (VNx32BF "4") 1558 (VNx32HF "4") (VNx16SF "4") (VNx8DF "4")]) 1559 1560;; The number of instruction bytes needed for an SVE_STRUCT move. This is 1561;; equal to vector_count * 4. 1562(define_mode_attr insn_length [(VNx32QI "8") (VNx16HI "8") 1563 (VNx8SI "8") (VNx4DI "8") 1564 (VNx16BF "8") 1565 (VNx16HF "8") (VNx8SF "8") (VNx4DF "8") 1566 (VNx48QI "12") (VNx24HI "12") 1567 (VNx12SI "12") (VNx6DI "12") 1568 (VNx24BF "12") 1569 (VNx24HF "12") (VNx12SF "12") (VNx6DF "12") 1570 (VNx64QI "16") (VNx32HI "16") 1571 (VNx16SI "16") (VNx8DI "16") 1572 (VNx32BF "16") 1573 (VNx32HF "16") (VNx16SF "16") (VNx8DF "16")]) 1574 1575;; The type of a subvector in an SVE_STRUCT. 1576(define_mode_attr VSINGLE [(VNx32QI "VNx16QI") 1577 (VNx16HI "VNx8HI") (VNx16HF "VNx8HF") 1578 (VNx16BF "VNx8BF") 1579 (VNx8SI "VNx4SI") (VNx8SF "VNx4SF") 1580 (VNx4DI "VNx2DI") (VNx4DF "VNx2DF") 1581 (VNx48QI "VNx16QI") 1582 (VNx24HI "VNx8HI") (VNx24HF "VNx8HF") 1583 (VNx24BF "VNx8BF") 1584 (VNx12SI "VNx4SI") (VNx12SF "VNx4SF") 1585 (VNx6DI "VNx2DI") (VNx6DF "VNx2DF") 1586 (VNx64QI "VNx16QI") 1587 (VNx32HI "VNx8HI") (VNx32HF "VNx8HF") 1588 (VNx32BF "VNx8BF") 1589 (VNx16SI "VNx4SI") (VNx16SF "VNx4SF") 1590 (VNx8DI "VNx2DI") (VNx8DF "VNx2DF")]) 1591 1592;; ...and again in lower case. 1593(define_mode_attr vsingle [(VNx32QI "vnx16qi") 1594 (VNx16HI "vnx8hi") (VNx16HF "vnx8hf") 1595 (VNx16BF "vnx8bf") 1596 (VNx8SI "vnx4si") (VNx8SF "vnx4sf") 1597 (VNx4DI "vnx2di") (VNx4DF "vnx2df") 1598 (VNx48QI "vnx16qi") 1599 (VNx24HI "vnx8hi") (VNx24HF "vnx8hf") 1600 (VNx24BF "vnx8bf") 1601 (VNx12SI "vnx4si") (VNx12SF "vnx4sf") 1602 (VNx6DI "vnx2di") (VNx6DF "vnx2df") 1603 (VNx64QI "vnx16qi") 1604 (VNx32HI "vnx8hi") (VNx32HF "vnx8hf") 1605 (VNx32BF "vnx8bf") 1606 (VNx16SI "vnx4si") (VNx16SF "vnx4sf") 1607 (VNx8DI "vnx2di") (VNx8DF "vnx2df")]) 1608 1609;; The predicate mode associated with an SVE data mode. For structure modes 1610;; this is equivalent to the <VPRED> of the subvector mode. 1611(define_mode_attr VPRED [(VNx16QI "VNx16BI") (VNx8QI "VNx8BI") 1612 (VNx4QI "VNx4BI") (VNx2QI "VNx2BI") 1613 (VNx8HI "VNx8BI") (VNx4HI "VNx4BI") (VNx2HI "VNx2BI") 1614 (VNx8HF "VNx8BI") (VNx4HF "VNx4BI") (VNx2HF "VNx2BI") 1615 (VNx8BF "VNx8BI") 1616 (VNx4SI "VNx4BI") (VNx2SI "VNx2BI") 1617 (VNx4SF "VNx4BI") (VNx2SF "VNx2BI") 1618 (VNx2DI "VNx2BI") 1619 (VNx2DF "VNx2BI") 1620 (VNx32QI "VNx16BI") 1621 (VNx16HI "VNx8BI") (VNx16HF "VNx8BI") 1622 (VNx16BF "VNx8BI") 1623 (VNx8SI "VNx4BI") (VNx8SF "VNx4BI") 1624 (VNx4DI "VNx2BI") (VNx4DF "VNx2BI") 1625 (VNx48QI "VNx16BI") 1626 (VNx24HI "VNx8BI") (VNx24HF "VNx8BI") 1627 (VNx24BF "VNx8BI") 1628 (VNx12SI "VNx4BI") (VNx12SF "VNx4BI") 1629 (VNx6DI "VNx2BI") (VNx6DF "VNx2BI") 1630 (VNx64QI "VNx16BI") 1631 (VNx32HI "VNx8BI") (VNx32HF "VNx8BI") 1632 (VNx32BF "VNx8BI") 1633 (VNx16SI "VNx4BI") (VNx16SF "VNx4BI") 1634 (VNx8DI "VNx2BI") (VNx8DF "VNx2BI")]) 1635 1636;; ...and again in lower case. 1637(define_mode_attr vpred [(VNx16QI "vnx16bi") (VNx8QI "vnx8bi") 1638 (VNx4QI "vnx4bi") (VNx2QI "vnx2bi") 1639 (VNx8HI "vnx8bi") (VNx4HI "vnx4bi") (VNx2HI "vnx2bi") 1640 (VNx8HF "vnx8bi") (VNx4HF "vnx4bi") (VNx2HF "vnx2bi") 1641 (VNx8BF "vnx8bi") 1642 (VNx4SI "vnx4bi") (VNx2SI "vnx2bi") 1643 (VNx4SF "vnx4bi") (VNx2SF "vnx2bi") 1644 (VNx2DI "vnx2bi") 1645 (VNx2DF "vnx2bi") 1646 (VNx32QI "vnx16bi") 1647 (VNx16HI "vnx8bi") (VNx16HF "vnx8bi") 1648 (VNx16BF "vnx8bi") 1649 (VNx8SI "vnx4bi") (VNx8SF "vnx4bi") 1650 (VNx4DI "vnx2bi") (VNx4DF "vnx2bi") 1651 (VNx48QI "vnx16bi") 1652 (VNx24HI "vnx8bi") (VNx24HF "vnx8bi") 1653 (VNx24BF "vnx8bi") 1654 (VNx12SI "vnx4bi") (VNx12SF "vnx4bi") 1655 (VNx6DI "vnx2bi") (VNx6DF "vnx2bi") 1656 (VNx64QI "vnx16bi") 1657 (VNx32HI "vnx8bi") (VNx32HF "vnx4bi") 1658 (VNx32BF "vnx8bi") 1659 (VNx16SI "vnx4bi") (VNx16SF "vnx4bi") 1660 (VNx8DI "vnx2bi") (VNx8DF "vnx2bi")]) 1661 1662(define_mode_attr VDOUBLE [(VNx16QI "VNx32QI") 1663 (VNx8HI "VNx16HI") (VNx8HF "VNx16HF") 1664 (VNx8BF "VNx16BF") 1665 (VNx4SI "VNx8SI") (VNx4SF "VNx8SF") 1666 (VNx2DI "VNx4DI") (VNx2DF "VNx4DF")]) 1667 1668;; On AArch64 the By element instruction doesn't have a 2S variant. 1669;; However because the instruction always selects a pair of values 1670;; The normal 3SAME instruction can be used here instead. 1671(define_mode_attr FCMLA_maybe_lane [(V2SF "<Vtype>") (V4SF "<Vetype>[%4]") 1672 (V4HF "<Vetype>[%4]") (V8HF "<Vetype>[%4]") 1673 ]) 1674 1675;; The number of bytes controlled by a predicate 1676(define_mode_attr data_bytes [(VNx16BI "1") (VNx8BI "2") 1677 (VNx4BI "4") (VNx2BI "8")]) 1678 1679;; Two-nybble mask for partial vector modes: nunits, byte size. 1680(define_mode_attr self_mask [(VNx8QI "0x81") 1681 (VNx4QI "0x41") 1682 (VNx2QI "0x21") 1683 (VNx4HI "0x42") 1684 (VNx2HI "0x22") 1685 (VNx2SI "0x24")]) 1686 1687;; For SVE_HSDI vector modes, the mask of narrower modes, encoded as above. 1688(define_mode_attr narrower_mask [(VNx8HI "0x81") (VNx4HI "0x41") 1689 (VNx2HI "0x21") 1690 (VNx4SI "0x43") (VNx2SI "0x23") 1691 (VNx2DI "0x27")]) 1692 1693;; The constraint to use for an SVE [SU]DOT, FMUL, FMLA or FMLS lane index. 1694(define_mode_attr sve_lane_con [(VNx8HI "y") (VNx4SI "y") (VNx2DI "x") 1695 (VNx8HF "y") (VNx4SF "y") (VNx2DF "x")]) 1696 1697;; The constraint to use for an SVE FCMLA lane index. 1698(define_mode_attr sve_lane_pair_con [(VNx8HF "y") (VNx4SF "x")]) 1699 1700;; ------------------------------------------------------------------- 1701;; Code Iterators 1702;; ------------------------------------------------------------------- 1703 1704;; This code iterator allows the various shifts supported on the core 1705(define_code_iterator SHIFT [ashift ashiftrt lshiftrt rotatert]) 1706 1707;; This code iterator allows the shifts supported in arithmetic instructions 1708(define_code_iterator ASHIFT [ashift ashiftrt lshiftrt]) 1709 1710(define_code_iterator SHIFTRT [ashiftrt lshiftrt]) 1711 1712;; Code iterator for logical operations 1713(define_code_iterator LOGICAL [and ior xor]) 1714 1715;; LOGICAL without AND. 1716(define_code_iterator LOGICAL_OR [ior xor]) 1717 1718;; Code iterator for logical operations whose :nlogical works on SIMD registers. 1719(define_code_iterator NLOGICAL [and ior]) 1720 1721;; Code iterator for unary negate and bitwise complement. 1722(define_code_iterator NEG_NOT [neg not]) 1723 1724;; Code iterator for sign/zero extension 1725(define_code_iterator ANY_EXTEND [sign_extend zero_extend]) 1726(define_code_iterator ANY_EXTEND2 [sign_extend zero_extend]) 1727 1728;; All division operations (signed/unsigned) 1729(define_code_iterator ANY_DIV [div udiv]) 1730 1731;; Code iterator for sign/zero extraction 1732(define_code_iterator ANY_EXTRACT [sign_extract zero_extract]) 1733 1734;; Code iterator for equality comparisons 1735(define_code_iterator EQL [eq ne]) 1736 1737;; Code iterator for less-than and greater/equal-to 1738(define_code_iterator LTGE [lt ge]) 1739 1740;; Iterator for __sync_<op> operations that where the operation can be 1741;; represented directly RTL. This is all of the sync operations bar 1742;; nand. 1743(define_code_iterator atomic_op [plus minus ior xor and]) 1744 1745;; Iterator for integer conversions 1746(define_code_iterator FIXUORS [fix unsigned_fix]) 1747 1748;; Iterator for float conversions 1749(define_code_iterator FLOATUORS [float unsigned_float]) 1750 1751;; Code iterator for variants of vector max and min. 1752(define_code_iterator MAXMIN [smax smin umax umin]) 1753 1754(define_code_iterator FMAXMIN [smax smin]) 1755 1756;; Signed and unsigned max operations. 1757(define_code_iterator USMAX [smax umax]) 1758 1759;; Code iterator for plus and minus. 1760(define_code_iterator ADDSUB [plus minus]) 1761 1762;; Code iterator for variants of vector saturating binary ops. 1763(define_code_iterator BINQOPS [ss_plus us_plus ss_minus us_minus]) 1764 1765;; Code iterator for variants of vector saturating unary ops. 1766(define_code_iterator UNQOPS [ss_neg ss_abs]) 1767 1768;; Code iterator for signed variants of vector saturating binary ops. 1769(define_code_iterator SBINQOPS [ss_plus ss_minus]) 1770 1771;; Code iterator for unsigned variants of vector saturating binary ops. 1772(define_code_iterator UBINQOPS [us_plus us_minus]) 1773 1774;; Modular and saturating addition. 1775(define_code_iterator ANY_PLUS [plus ss_plus us_plus]) 1776 1777;; Saturating addition. 1778(define_code_iterator SAT_PLUS [ss_plus us_plus]) 1779 1780;; Modular and saturating subtraction. 1781(define_code_iterator ANY_MINUS [minus ss_minus us_minus]) 1782 1783;; Saturating subtraction. 1784(define_code_iterator SAT_MINUS [ss_minus us_minus]) 1785 1786;; Comparison operators for <F>CM. 1787(define_code_iterator COMPARISONS [lt le eq ge gt]) 1788 1789;; Unsigned comparison operators. 1790(define_code_iterator UCOMPARISONS [ltu leu geu gtu]) 1791 1792;; Unsigned comparison operators. 1793(define_code_iterator FAC_COMPARISONS [lt le ge gt]) 1794 1795;; SVE integer unary operations. 1796(define_code_iterator SVE_INT_UNARY [abs neg not clrsb clz popcount 1797 (ss_abs "TARGET_SVE2") 1798 (ss_neg "TARGET_SVE2")]) 1799 1800;; SVE integer binary operations. 1801(define_code_iterator SVE_INT_BINARY [plus minus mult smax umax smin umin 1802 ashift ashiftrt lshiftrt 1803 and ior xor 1804 (ss_plus "TARGET_SVE2") 1805 (us_plus "TARGET_SVE2") 1806 (ss_minus "TARGET_SVE2") 1807 (us_minus "TARGET_SVE2")]) 1808 1809;; SVE integer binary division operations. 1810(define_code_iterator SVE_INT_BINARY_SD [div udiv]) 1811 1812;; SVE integer binary operations that have an immediate form. 1813(define_code_iterator SVE_INT_BINARY_IMM [mult smax smin umax umin]) 1814 1815;; SVE floating-point operations with an unpredicated all-register form. 1816(define_code_iterator SVE_UNPRED_FP_BINARY [plus minus mult]) 1817 1818;; SVE integer comparisons. 1819(define_code_iterator SVE_INT_CMP [lt le eq ne ge gt ltu leu geu gtu]) 1820 1821;; ------------------------------------------------------------------- 1822;; Code Attributes 1823;; ------------------------------------------------------------------- 1824;; Map rtl objects to optab names 1825(define_code_attr optab [(ashift "ashl") 1826 (ashiftrt "ashr") 1827 (lshiftrt "lshr") 1828 (rotatert "rotr") 1829 (sign_extend "extend") 1830 (zero_extend "zero_extend") 1831 (sign_extract "extv") 1832 (zero_extract "extzv") 1833 (fix "fix") 1834 (unsigned_fix "fixuns") 1835 (float "float") 1836 (unsigned_float "floatuns") 1837 (clrsb "clrsb") 1838 (clz "clz") 1839 (popcount "popcount") 1840 (and "and") 1841 (ior "ior") 1842 (xor "xor") 1843 (not "one_cmpl") 1844 (neg "neg") 1845 (plus "add") 1846 (minus "sub") 1847 (mult "mul") 1848 (div "div") 1849 (udiv "udiv") 1850 (ss_plus "ssadd") 1851 (us_plus "usadd") 1852 (ss_minus "sssub") 1853 (us_minus "ussub") 1854 (ss_neg "qneg") 1855 (ss_abs "qabs") 1856 (smin "smin") 1857 (smax "smax") 1858 (umin "umin") 1859 (umax "umax") 1860 (eq "eq") 1861 (ne "ne") 1862 (lt "lt") 1863 (ge "ge") 1864 (le "le") 1865 (gt "gt") 1866 (ltu "ltu") 1867 (leu "leu") 1868 (geu "geu") 1869 (gtu "gtu") 1870 (abs "abs")]) 1871 1872(define_code_attr addsub [(ss_plus "add") 1873 (us_plus "add") 1874 (ss_minus "sub") 1875 (us_minus "sub")]) 1876 1877;; For comparison operators we use the FCM* and CM* instructions. 1878;; As there are no CMLE or CMLT instructions which act on 3 vector 1879;; operands, we must use CMGE or CMGT and swap the order of the 1880;; source operands. 1881 1882(define_code_attr n_optab [(lt "gt") (le "ge") (eq "eq") (ge "ge") (gt "gt") 1883 (ltu "hi") (leu "hs") (geu "hs") (gtu "hi")]) 1884(define_code_attr cmp_1 [(lt "2") (le "2") (eq "1") (ge "1") (gt "1") 1885 (ltu "2") (leu "2") (geu "1") (gtu "1")]) 1886(define_code_attr cmp_2 [(lt "1") (le "1") (eq "2") (ge "2") (gt "2") 1887 (ltu "1") (leu "1") (geu "2") (gtu "2")]) 1888 1889(define_code_attr CMP [(lt "LT") (le "LE") (eq "EQ") (ge "GE") (gt "GT") 1890 (ltu "LTU") (leu "LEU") (ne "NE") (geu "GEU") 1891 (gtu "GTU")]) 1892 1893;; The AArch64 condition associated with an rtl comparison code. 1894(define_code_attr cmp_op [(lt "lt") 1895 (le "le") 1896 (eq "eq") 1897 (ne "ne") 1898 (ge "ge") 1899 (gt "gt") 1900 (ltu "lo") 1901 (leu "ls") 1902 (geu "hs") 1903 (gtu "hi")]) 1904 1905(define_code_attr fix_trunc_optab [(fix "fix_trunc") 1906 (unsigned_fix "fixuns_trunc")]) 1907 1908;; Optab prefix for sign/zero-extending operations 1909(define_code_attr su_optab [(sign_extend "") (zero_extend "u") 1910 (div "") (udiv "u") 1911 (fix "") (unsigned_fix "u") 1912 (float "s") (unsigned_float "u") 1913 (ss_plus "s") (us_plus "u") 1914 (ss_minus "s") (us_minus "u")]) 1915 1916;; Similar for the instruction mnemonics 1917(define_code_attr shift [(ashift "lsl") (ashiftrt "asr") 1918 (lshiftrt "lsr") (rotatert "ror")]) 1919 1920;; Op prefix for shift right and accumulate. 1921(define_code_attr sra_op [(ashiftrt "s") (lshiftrt "u")]) 1922 1923;; Map shift operators onto underlying bit-field instructions 1924(define_code_attr bfshift [(ashift "ubfiz") (ashiftrt "sbfx") 1925 (lshiftrt "ubfx") (rotatert "extr")]) 1926 1927;; Logical operator instruction mnemonics 1928(define_code_attr logical [(and "and") (ior "orr") (xor "eor")]) 1929 1930;; Operation names for negate and bitwise complement. 1931(define_code_attr neg_not_op [(neg "neg") (not "not")]) 1932 1933;; Similar, but when the second operand is inverted. 1934(define_code_attr nlogical [(and "bic") (ior "orn") (xor "eon")]) 1935 1936;; Similar, but when both operands are inverted. 1937(define_code_attr logical_nn [(and "nor") (ior "nand")]) 1938 1939;; Sign- or zero-extending data-op 1940(define_code_attr su [(sign_extend "s") (zero_extend "u") 1941 (sign_extract "s") (zero_extract "u") 1942 (fix "s") (unsigned_fix "u") 1943 (div "s") (udiv "u") 1944 (smax "s") (umax "u") 1945 (smin "s") (umin "u")]) 1946 1947;; "s" for signed ops, empty for unsigned ones. 1948(define_code_attr s [(sign_extend "s") (zero_extend "")]) 1949 1950;; Map signed/unsigned ops to the corresponding extension. 1951(define_code_attr paired_extend [(ss_plus "sign_extend") 1952 (us_plus "zero_extend") 1953 (ss_minus "sign_extend") 1954 (us_minus "zero_extend")]) 1955 1956;; Whether a shift is left or right. 1957(define_code_attr lr [(ashift "l") (ashiftrt "r") (lshiftrt "r")]) 1958 1959;; Emit conditional branch instructions. 1960(define_code_attr bcond [(eq "beq") (ne "bne") (lt "bne") (ge "beq")]) 1961 1962;; Emit cbz/cbnz depending on comparison type. 1963(define_code_attr cbz [(eq "cbz") (ne "cbnz") (lt "cbnz") (ge "cbz")]) 1964 1965;; Emit inverted cbz/cbnz depending on comparison type. 1966(define_code_attr inv_cb [(eq "cbnz") (ne "cbz") (lt "cbz") (ge "cbnz")]) 1967 1968;; Emit tbz/tbnz depending on comparison type. 1969(define_code_attr tbz [(eq "tbz") (ne "tbnz") (lt "tbnz") (ge "tbz")]) 1970 1971;; Emit inverted tbz/tbnz depending on comparison type. 1972(define_code_attr inv_tb [(eq "tbnz") (ne "tbz") (lt "tbz") (ge "tbnz")]) 1973 1974;; Max/min attributes. 1975(define_code_attr maxmin [(smax "max") 1976 (smin "min") 1977 (umax "max") 1978 (umin "min")]) 1979 1980;; MLA/MLS attributes. 1981(define_code_attr as [(ss_plus "a") (ss_minus "s")]) 1982 1983;; Atomic operations 1984(define_code_attr atomic_optab 1985 [(ior "or") (xor "xor") (and "and") (plus "add") (minus "sub")]) 1986 1987(define_code_attr atomic_op_operand 1988 [(ior "aarch64_logical_operand") 1989 (xor "aarch64_logical_operand") 1990 (and "aarch64_logical_operand") 1991 (plus "aarch64_plus_operand") 1992 (minus "aarch64_plus_operand")]) 1993 1994;; Constants acceptable for atomic operations. 1995;; This definition must appear in this file before the iterators it refers to. 1996(define_code_attr const_atomic 1997 [(plus "IJ") (minus "IJ") 1998 (xor "<lconst_atomic>") (ior "<lconst_atomic>") 1999 (and "<lconst_atomic>")]) 2000 2001;; Attribute to describe constants acceptable in atomic logical operations 2002(define_mode_attr lconst_atomic [(QI "K") (HI "K") (SI "K") (DI "L")]) 2003 2004;; The integer SVE instruction that implements an rtx code. 2005(define_code_attr sve_int_op [(plus "add") 2006 (minus "sub") 2007 (mult "mul") 2008 (div "sdiv") 2009 (udiv "udiv") 2010 (abs "abs") 2011 (neg "neg") 2012 (smin "smin") 2013 (smax "smax") 2014 (umin "umin") 2015 (umax "umax") 2016 (ashift "lsl") 2017 (ashiftrt "asr") 2018 (lshiftrt "lsr") 2019 (and "and") 2020 (ior "orr") 2021 (xor "eor") 2022 (not "not") 2023 (clrsb "cls") 2024 (clz "clz") 2025 (popcount "cnt") 2026 (ss_plus "sqadd") 2027 (us_plus "uqadd") 2028 (ss_minus "sqsub") 2029 (us_minus "uqsub") 2030 (ss_neg "sqneg") 2031 (ss_abs "sqabs")]) 2032 2033(define_code_attr sve_int_op_rev [(plus "add") 2034 (minus "subr") 2035 (mult "mul") 2036 (div "sdivr") 2037 (udiv "udivr") 2038 (smin "smin") 2039 (smax "smax") 2040 (umin "umin") 2041 (umax "umax") 2042 (ashift "lslr") 2043 (ashiftrt "asrr") 2044 (lshiftrt "lsrr") 2045 (and "and") 2046 (ior "orr") 2047 (xor "eor") 2048 (ss_plus "sqadd") 2049 (us_plus "uqadd") 2050 (ss_minus "sqsubr") 2051 (us_minus "uqsubr")]) 2052 2053;; The floating-point SVE instruction that implements an rtx code. 2054(define_code_attr sve_fp_op [(plus "fadd") 2055 (minus "fsub") 2056 (mult "fmul")]) 2057 2058;; The SVE immediate constraint to use for an rtl code. 2059(define_code_attr sve_imm_con [(mult "vsm") 2060 (smax "vsm") 2061 (smin "vsm") 2062 (umax "vsb") 2063 (umin "vsb") 2064 (eq "vsc") 2065 (ne "vsc") 2066 (lt "vsc") 2067 (ge "vsc") 2068 (le "vsc") 2069 (gt "vsc") 2070 (ltu "vsd") 2071 (leu "vsd") 2072 (geu "vsd") 2073 (gtu "vsd")]) 2074 2075;; The prefix letter to use when printing an immediate operand. 2076(define_code_attr sve_imm_prefix [(mult "") 2077 (smax "") 2078 (smin "") 2079 (umax "D") 2080 (umin "D")]) 2081 2082;; The predicate to use for the second input operand in a cond_<optab><mode> 2083;; pattern. 2084(define_code_attr sve_pred_int_rhs2_operand 2085 [(plus "register_operand") 2086 (minus "register_operand") 2087 (mult "register_operand") 2088 (smax "register_operand") 2089 (umax "register_operand") 2090 (smin "register_operand") 2091 (umin "register_operand") 2092 (ashift "aarch64_sve_lshift_operand") 2093 (ashiftrt "aarch64_sve_rshift_operand") 2094 (lshiftrt "aarch64_sve_rshift_operand") 2095 (and "aarch64_sve_pred_and_operand") 2096 (ior "register_operand") 2097 (xor "register_operand") 2098 (ss_plus "register_operand") 2099 (us_plus "register_operand") 2100 (ss_minus "register_operand") 2101 (us_minus "register_operand")]) 2102 2103(define_code_attr inc_dec [(minus "dec") (ss_minus "sqdec") (us_minus "uqdec") 2104 (plus "inc") (ss_plus "sqinc") (us_plus "uqinc")]) 2105 2106;; ------------------------------------------------------------------- 2107;; Int Iterators. 2108;; ------------------------------------------------------------------- 2109 2110;; The unspec codes for the SABAL, UABAL AdvancedSIMD instructions. 2111(define_int_iterator ABAL [UNSPEC_SABAL UNSPEC_UABAL]) 2112 2113;; The unspec codes for the SABDL2, UABDL2 AdvancedSIMD instructions. 2114(define_int_iterator ABDL2 [UNSPEC_SABDL2 UNSPEC_UABDL2]) 2115 2116;; The unspec codes for the SADALP, UADALP AdvancedSIMD instructions. 2117(define_int_iterator ADALP [UNSPEC_SADALP UNSPEC_UADALP]) 2118 2119(define_int_iterator MAXMINV [UNSPEC_UMAXV UNSPEC_UMINV 2120 UNSPEC_SMAXV UNSPEC_SMINV]) 2121 2122(define_int_iterator FMAXMINV [UNSPEC_FMAXV UNSPEC_FMINV 2123 UNSPEC_FMAXNMV UNSPEC_FMINNMV]) 2124 2125(define_int_iterator SVE_INT_ADDV [UNSPEC_SADDV UNSPEC_UADDV]) 2126 2127(define_int_iterator LOGICALF [UNSPEC_ANDF UNSPEC_IORF UNSPEC_XORF]) 2128 2129(define_int_iterator HADDSUB [UNSPEC_SHADD UNSPEC_UHADD 2130 UNSPEC_SRHADD UNSPEC_URHADD 2131 UNSPEC_SHSUB UNSPEC_UHSUB]) 2132 2133(define_int_iterator HADD [UNSPEC_SHADD UNSPEC_UHADD]) 2134 2135(define_int_iterator RHADD [UNSPEC_SRHADD UNSPEC_URHADD]) 2136 2137(define_int_iterator BSL_DUP [1 2]) 2138 2139(define_int_iterator DOTPROD [UNSPEC_SDOT UNSPEC_UDOT]) 2140 2141(define_int_iterator DOTPROD_I8MM [UNSPEC_USDOT UNSPEC_SUDOT]) 2142(define_int_iterator DOTPROD_US_ONLY [UNSPEC_USDOT]) 2143 2144(define_int_iterator ADDSUBHN [UNSPEC_ADDHN UNSPEC_RADDHN 2145 UNSPEC_SUBHN UNSPEC_RSUBHN]) 2146 2147(define_int_iterator ADDSUBHN2 [UNSPEC_ADDHN2 UNSPEC_RADDHN2 2148 UNSPEC_SUBHN2 UNSPEC_RSUBHN2]) 2149 2150(define_int_iterator FMAXMIN_UNS [UNSPEC_FMAX UNSPEC_FMIN 2151 UNSPEC_FMAXNM UNSPEC_FMINNM]) 2152 2153(define_int_iterator PAUTH_LR_SP [UNSPEC_PACIASP UNSPEC_AUTIASP 2154 UNSPEC_PACIBSP UNSPEC_AUTIBSP]) 2155 2156(define_int_iterator PAUTH_17_16 [UNSPEC_PACIA1716 UNSPEC_AUTIA1716 2157 UNSPEC_PACIB1716 UNSPEC_AUTIB1716]) 2158 2159(define_int_iterator VQDMULH [UNSPEC_SQDMULH UNSPEC_SQRDMULH]) 2160 2161(define_int_iterator MULHRS [UNSPEC_SMULHS UNSPEC_UMULHS 2162 UNSPEC_SMULHRS UNSPEC_UMULHRS]) 2163 2164(define_int_iterator USSUQADD [UNSPEC_SUQADD UNSPEC_USQADD]) 2165 2166(define_int_iterator SUQMOVN [UNSPEC_SQXTN UNSPEC_UQXTN]) 2167 2168(define_int_iterator VSHL [UNSPEC_SSHL UNSPEC_USHL 2169 UNSPEC_SRSHL UNSPEC_URSHL]) 2170 2171(define_int_iterator VSHLL [UNSPEC_SSHLL UNSPEC_USHLL]) 2172 2173(define_int_iterator VQSHL [UNSPEC_SQSHL UNSPEC_UQSHL 2174 UNSPEC_SQRSHL UNSPEC_UQRSHL]) 2175 2176(define_int_iterator VSRA [UNSPEC_SSRA UNSPEC_USRA 2177 UNSPEC_SRSRA UNSPEC_URSRA]) 2178 2179(define_int_iterator VSLRI [UNSPEC_SSLI UNSPEC_USLI 2180 UNSPEC_SSRI UNSPEC_USRI]) 2181 2182 2183(define_int_iterator VRSHR_N [UNSPEC_SRSHR UNSPEC_URSHR]) 2184 2185(define_int_iterator VQSHL_N [UNSPEC_SQSHLU UNSPEC_SQSHL UNSPEC_UQSHL]) 2186 2187(define_int_iterator VQSHRN_N [UNSPEC_SQSHRUN UNSPEC_SQRSHRUN 2188 UNSPEC_SQSHRN UNSPEC_UQSHRN 2189 UNSPEC_SQRSHRN UNSPEC_UQRSHRN]) 2190 2191(define_int_iterator SQRDMLH_AS [UNSPEC_SQRDMLAH UNSPEC_SQRDMLSH]) 2192 2193(define_int_iterator PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2 2194 UNSPEC_TRN1 UNSPEC_TRN2 2195 UNSPEC_UZP1 UNSPEC_UZP2]) 2196 2197(define_int_iterator PERMUTEQ [UNSPEC_ZIP1Q UNSPEC_ZIP2Q 2198 UNSPEC_TRN1Q UNSPEC_TRN2Q 2199 UNSPEC_UZP1Q UNSPEC_UZP2Q]) 2200 2201(define_int_iterator OPTAB_PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2 2202 UNSPEC_UZP1 UNSPEC_UZP2]) 2203 2204(define_int_iterator REVERSE [UNSPEC_REV64 UNSPEC_REV32 UNSPEC_REV16]) 2205 2206(define_int_iterator FRINT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM 2207 UNSPEC_FRINTN UNSPEC_FRINTI UNSPEC_FRINTX 2208 UNSPEC_FRINTA]) 2209 2210(define_int_iterator FCVT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM 2211 UNSPEC_FRINTA UNSPEC_FRINTN]) 2212 2213(define_int_iterator FCVT_F2FIXED [UNSPEC_FCVTZS UNSPEC_FCVTZU]) 2214(define_int_iterator FCVT_FIXED2F [UNSPEC_SCVTF UNSPEC_UCVTF]) 2215 2216(define_int_iterator CRC [UNSPEC_CRC32B UNSPEC_CRC32H UNSPEC_CRC32W 2217 UNSPEC_CRC32X UNSPEC_CRC32CB UNSPEC_CRC32CH 2218 UNSPEC_CRC32CW UNSPEC_CRC32CX]) 2219 2220(define_int_iterator CRYPTO_AES [UNSPEC_AESE UNSPEC_AESD]) 2221(define_int_iterator CRYPTO_AESMC [UNSPEC_AESMC UNSPEC_AESIMC]) 2222 2223(define_int_iterator CRYPTO_SHA1 [UNSPEC_SHA1C UNSPEC_SHA1M UNSPEC_SHA1P]) 2224 2225(define_int_iterator CRYPTO_SHA256 [UNSPEC_SHA256H UNSPEC_SHA256H2]) 2226 2227(define_int_iterator CRYPTO_SHA512 [UNSPEC_SHA512H UNSPEC_SHA512H2]) 2228 2229(define_int_iterator CRYPTO_SM3TT [UNSPEC_SM3TT1A UNSPEC_SM3TT1B 2230 UNSPEC_SM3TT2A UNSPEC_SM3TT2B]) 2231 2232(define_int_iterator CRYPTO_SM3PART [UNSPEC_SM3PARTW1 UNSPEC_SM3PARTW2]) 2233 2234;; Iterators for fp16 operations 2235 2236(define_int_iterator VFMLA16_LOW [UNSPEC_FMLAL UNSPEC_FMLSL]) 2237 2238(define_int_iterator VFMLA16_HIGH [UNSPEC_FMLAL2 UNSPEC_FMLSL2]) 2239 2240(define_int_iterator UNPACK [UNSPEC_UNPACKSHI UNSPEC_UNPACKUHI 2241 UNSPEC_UNPACKSLO UNSPEC_UNPACKULO]) 2242 2243(define_int_iterator UNPACK_UNSIGNED [UNSPEC_UNPACKULO UNSPEC_UNPACKUHI]) 2244 2245(define_int_iterator MUL_HIGHPART [UNSPEC_SMUL_HIGHPART UNSPEC_UMUL_HIGHPART]) 2246 2247(define_int_iterator CLAST [UNSPEC_CLASTA UNSPEC_CLASTB]) 2248 2249(define_int_iterator LAST [UNSPEC_LASTA UNSPEC_LASTB]) 2250 2251(define_int_iterator SVE_INT_UNARY [UNSPEC_RBIT UNSPEC_REVB 2252 UNSPEC_REVH UNSPEC_REVW]) 2253 2254(define_int_iterator SVE_FP_UNARY [UNSPEC_FRECPE UNSPEC_RSQRTE]) 2255 2256(define_int_iterator SVE_FP_UNARY_INT [UNSPEC_FEXPA]) 2257 2258(define_int_iterator SVE_INT_SHIFT_IMM [UNSPEC_ASRD 2259 (UNSPEC_SQSHLU "TARGET_SVE2") 2260 (UNSPEC_SRSHR "TARGET_SVE2") 2261 (UNSPEC_URSHR "TARGET_SVE2")]) 2262 2263(define_int_iterator SVE_FP_BINARY [UNSPEC_FRECPS UNSPEC_RSQRTS]) 2264 2265(define_int_iterator SVE_FP_BINARY_INT [UNSPEC_FTSMUL UNSPEC_FTSSEL]) 2266 2267(define_int_iterator SVE_BFLOAT_TERNARY_LONG [UNSPEC_BFDOT 2268 UNSPEC_BFMLALB 2269 UNSPEC_BFMLALT 2270 UNSPEC_BFMMLA]) 2271 2272(define_int_iterator SVE_BFLOAT_TERNARY_LONG_LANE [UNSPEC_BFDOT 2273 UNSPEC_BFMLALB 2274 UNSPEC_BFMLALT]) 2275 2276(define_int_iterator SVE_INT_REDUCTION [UNSPEC_ANDV 2277 UNSPEC_IORV 2278 UNSPEC_SMAXV 2279 UNSPEC_SMINV 2280 UNSPEC_UMAXV 2281 UNSPEC_UMINV 2282 UNSPEC_XORV]) 2283 2284(define_int_iterator SVE_FP_REDUCTION [UNSPEC_FADDV 2285 UNSPEC_FMAXV 2286 UNSPEC_FMAXNMV 2287 UNSPEC_FMINV 2288 UNSPEC_FMINNMV]) 2289 2290(define_int_iterator SVE_COND_FP_UNARY [UNSPEC_COND_FABS 2291 UNSPEC_COND_FNEG 2292 UNSPEC_COND_FRECPX 2293 UNSPEC_COND_FRINTA 2294 UNSPEC_COND_FRINTI 2295 UNSPEC_COND_FRINTM 2296 UNSPEC_COND_FRINTN 2297 UNSPEC_COND_FRINTP 2298 UNSPEC_COND_FRINTX 2299 UNSPEC_COND_FRINTZ 2300 UNSPEC_COND_FSQRT]) 2301 2302;; Same as SVE_COND_FP_UNARY, but without codes that have a dedicated 2303;; <optab><mode>2 expander. 2304(define_int_iterator SVE_COND_FP_UNARY_OPTAB [UNSPEC_COND_FABS 2305 UNSPEC_COND_FNEG 2306 UNSPEC_COND_FRECPX 2307 UNSPEC_COND_FRINTA 2308 UNSPEC_COND_FRINTI 2309 UNSPEC_COND_FRINTM 2310 UNSPEC_COND_FRINTN 2311 UNSPEC_COND_FRINTP 2312 UNSPEC_COND_FRINTX 2313 UNSPEC_COND_FRINTZ]) 2314 2315(define_int_iterator SVE_COND_FCVT [UNSPEC_COND_FCVT]) 2316(define_int_iterator SVE_COND_FCVTI [UNSPEC_COND_FCVTZS UNSPEC_COND_FCVTZU]) 2317(define_int_iterator SVE_COND_ICVTF [UNSPEC_COND_SCVTF UNSPEC_COND_UCVTF]) 2318 2319(define_int_iterator SVE_COND_FP_BINARY [UNSPEC_COND_FADD 2320 UNSPEC_COND_FDIV 2321 UNSPEC_COND_FMAX 2322 UNSPEC_COND_FMAXNM 2323 UNSPEC_COND_FMIN 2324 UNSPEC_COND_FMINNM 2325 UNSPEC_COND_FMUL 2326 UNSPEC_COND_FMULX 2327 UNSPEC_COND_FSUB]) 2328 2329;; Same as SVE_COND_FP_BINARY, but without codes that have a dedicated 2330;; <optab><mode>3 expander. 2331(define_int_iterator SVE_COND_FP_BINARY_OPTAB [UNSPEC_COND_FADD 2332 UNSPEC_COND_FMAX 2333 UNSPEC_COND_FMAXNM 2334 UNSPEC_COND_FMIN 2335 UNSPEC_COND_FMINNM 2336 UNSPEC_COND_FMUL 2337 UNSPEC_COND_FMULX 2338 UNSPEC_COND_FSUB]) 2339 2340(define_int_iterator SVE_COND_FP_BINARY_INT [UNSPEC_COND_FSCALE]) 2341 2342(define_int_iterator SVE_COND_FP_ADD [UNSPEC_COND_FADD]) 2343(define_int_iterator SVE_COND_FP_SUB [UNSPEC_COND_FSUB]) 2344(define_int_iterator SVE_COND_FP_MUL [UNSPEC_COND_FMUL]) 2345 2346(define_int_iterator SVE_COND_FP_BINARY_I1 [UNSPEC_COND_FMAX 2347 UNSPEC_COND_FMAXNM 2348 UNSPEC_COND_FMIN 2349 UNSPEC_COND_FMINNM 2350 UNSPEC_COND_FMUL]) 2351 2352(define_int_iterator SVE_COND_FP_BINARY_REG [UNSPEC_COND_FDIV 2353 UNSPEC_COND_FMULX]) 2354 2355(define_int_iterator SVE_COND_FCADD [UNSPEC_COND_FCADD90 2356 UNSPEC_COND_FCADD270]) 2357 2358(define_int_iterator SVE_COND_FP_MAXMIN [UNSPEC_COND_FMAX 2359 UNSPEC_COND_FMAXNM 2360 UNSPEC_COND_FMIN 2361 UNSPEC_COND_FMINNM]) 2362 2363;; Floating-point max/min operations that correspond to optabs, 2364;; as opposed to those that are internal to the port. 2365(define_int_iterator SVE_COND_FP_MAXMIN_PUBLIC [UNSPEC_COND_FMAXNM 2366 UNSPEC_COND_FMINNM]) 2367 2368(define_int_iterator SVE_COND_FP_TERNARY [UNSPEC_COND_FMLA 2369 UNSPEC_COND_FMLS 2370 UNSPEC_COND_FNMLA 2371 UNSPEC_COND_FNMLS]) 2372 2373(define_int_iterator SVE_COND_FCMLA [UNSPEC_COND_FCMLA 2374 UNSPEC_COND_FCMLA90 2375 UNSPEC_COND_FCMLA180 2376 UNSPEC_COND_FCMLA270]) 2377 2378(define_int_iterator SVE_COND_INT_CMP_WIDE [UNSPEC_COND_CMPEQ_WIDE 2379 UNSPEC_COND_CMPGE_WIDE 2380 UNSPEC_COND_CMPGT_WIDE 2381 UNSPEC_COND_CMPHI_WIDE 2382 UNSPEC_COND_CMPHS_WIDE 2383 UNSPEC_COND_CMPLE_WIDE 2384 UNSPEC_COND_CMPLO_WIDE 2385 UNSPEC_COND_CMPLS_WIDE 2386 UNSPEC_COND_CMPLT_WIDE 2387 UNSPEC_COND_CMPNE_WIDE]) 2388 2389;; SVE FP comparisons that accept #0.0. 2390(define_int_iterator SVE_COND_FP_CMP_I0 [UNSPEC_COND_FCMEQ 2391 UNSPEC_COND_FCMGE 2392 UNSPEC_COND_FCMGT 2393 UNSPEC_COND_FCMLE 2394 UNSPEC_COND_FCMLT 2395 UNSPEC_COND_FCMNE]) 2396 2397(define_int_iterator SVE_COND_FP_ABS_CMP [UNSPEC_COND_FCMGE 2398 UNSPEC_COND_FCMGT 2399 UNSPEC_COND_FCMLE 2400 UNSPEC_COND_FCMLT]) 2401 2402(define_int_iterator SVE_FP_TERNARY_LANE [UNSPEC_FMLA UNSPEC_FMLS]) 2403 2404(define_int_iterator SVE_CFP_TERNARY_LANE [UNSPEC_FCMLA UNSPEC_FCMLA90 2405 UNSPEC_FCMLA180 UNSPEC_FCMLA270]) 2406 2407(define_int_iterator SVE_WHILE [UNSPEC_WHILELE UNSPEC_WHILELO 2408 UNSPEC_WHILELS UNSPEC_WHILELT 2409 (UNSPEC_WHILEGE "TARGET_SVE2") 2410 (UNSPEC_WHILEGT "TARGET_SVE2") 2411 (UNSPEC_WHILEHI "TARGET_SVE2") 2412 (UNSPEC_WHILEHS "TARGET_SVE2") 2413 (UNSPEC_WHILERW "TARGET_SVE2") 2414 (UNSPEC_WHILEWR "TARGET_SVE2")]) 2415 2416(define_int_iterator SVE2_WHILE_PTR [UNSPEC_WHILERW UNSPEC_WHILEWR]) 2417 2418(define_int_iterator SVE_SHIFT_WIDE [UNSPEC_ASHIFT_WIDE 2419 UNSPEC_ASHIFTRT_WIDE 2420 UNSPEC_LSHIFTRT_WIDE]) 2421 2422(define_int_iterator SVE_LDFF1_LDNF1 [UNSPEC_LDFF1 UNSPEC_LDNF1]) 2423 2424(define_int_iterator SVE2_U32_UNARY [UNSPEC_URECPE UNSPEC_RSQRTE]) 2425 2426(define_int_iterator SVE2_INT_UNARY_NARROWB [UNSPEC_SQXTNB 2427 UNSPEC_SQXTUNB 2428 UNSPEC_UQXTNB]) 2429 2430(define_int_iterator SVE2_INT_UNARY_NARROWT [UNSPEC_SQXTNT 2431 UNSPEC_SQXTUNT 2432 UNSPEC_UQXTNT]) 2433 2434(define_int_iterator SVE2_INT_BINARY [UNSPEC_SQDMULH 2435 UNSPEC_SQRDMULH]) 2436 2437(define_int_iterator SVE2_INT_BINARY_LANE [UNSPEC_SQDMULH 2438 UNSPEC_SQRDMULH]) 2439 2440(define_int_iterator SVE2_INT_BINARY_LONG [UNSPEC_SABDLB 2441 UNSPEC_SABDLT 2442 UNSPEC_SADDLB 2443 UNSPEC_SADDLBT 2444 UNSPEC_SADDLT 2445 UNSPEC_SMULLB 2446 UNSPEC_SMULLT 2447 UNSPEC_SQDMULLB 2448 UNSPEC_SQDMULLT 2449 UNSPEC_SSUBLB 2450 UNSPEC_SSUBLBT 2451 UNSPEC_SSUBLT 2452 UNSPEC_SSUBLTB 2453 UNSPEC_UABDLB 2454 UNSPEC_UABDLT 2455 UNSPEC_UADDLB 2456 UNSPEC_UADDLT 2457 UNSPEC_UMULLB 2458 UNSPEC_UMULLT 2459 UNSPEC_USUBLB 2460 UNSPEC_USUBLT]) 2461 2462(define_int_iterator SVE2_INT_BINARY_LONG_LANE [UNSPEC_SMULLB 2463 UNSPEC_SMULLT 2464 UNSPEC_SQDMULLB 2465 UNSPEC_SQDMULLT 2466 UNSPEC_UMULLB 2467 UNSPEC_UMULLT]) 2468 2469(define_int_iterator SVE2_INT_BINARY_NARROWB [UNSPEC_ADDHNB 2470 UNSPEC_RADDHNB 2471 UNSPEC_RSUBHNB 2472 UNSPEC_SUBHNB]) 2473 2474(define_int_iterator SVE2_INT_BINARY_NARROWT [UNSPEC_ADDHNT 2475 UNSPEC_RADDHNT 2476 UNSPEC_RSUBHNT 2477 UNSPEC_SUBHNT]) 2478 2479(define_int_iterator SVE2_INT_BINARY_PAIR [UNSPEC_ADDP 2480 UNSPEC_SMAXP 2481 UNSPEC_SMINP 2482 UNSPEC_UMAXP 2483 UNSPEC_UMINP]) 2484 2485(define_int_iterator SVE2_FP_BINARY_PAIR [UNSPEC_FADDP 2486 UNSPEC_FMAXP 2487 UNSPEC_FMAXNMP 2488 UNSPEC_FMINP 2489 UNSPEC_FMINNMP]) 2490 2491(define_int_iterator SVE2_INT_BINARY_PAIR_LONG [UNSPEC_SADALP UNSPEC_UADALP]) 2492 2493(define_int_iterator SVE2_INT_BINARY_WIDE [UNSPEC_SADDWB 2494 UNSPEC_SADDWT 2495 UNSPEC_SSUBWB 2496 UNSPEC_SSUBWT 2497 UNSPEC_UADDWB 2498 UNSPEC_UADDWT 2499 UNSPEC_USUBWB 2500 UNSPEC_USUBWT]) 2501 2502(define_int_iterator SVE2_INT_SHIFT_IMM_LONG [UNSPEC_SSHLLB 2503 UNSPEC_SSHLLT 2504 UNSPEC_USHLLB 2505 UNSPEC_USHLLT]) 2506 2507(define_int_iterator SVE2_INT_SHIFT_IMM_NARROWB [UNSPEC_RSHRNB 2508 UNSPEC_SHRNB 2509 UNSPEC_SQRSHRNB 2510 UNSPEC_SQRSHRUNB 2511 UNSPEC_SQSHRNB 2512 UNSPEC_SQSHRUNB 2513 UNSPEC_UQRSHRNB 2514 UNSPEC_UQSHRNB]) 2515 2516(define_int_iterator SVE2_INT_SHIFT_IMM_NARROWT [UNSPEC_RSHRNT 2517 UNSPEC_SHRNT 2518 UNSPEC_SQRSHRNT 2519 UNSPEC_SQRSHRUNT 2520 UNSPEC_SQSHRNT 2521 UNSPEC_SQSHRUNT 2522 UNSPEC_UQRSHRNT 2523 UNSPEC_UQSHRNT]) 2524 2525(define_int_iterator SVE2_INT_SHIFT_INSERT [UNSPEC_SLI UNSPEC_SRI]) 2526 2527(define_int_iterator SVE2_INT_CADD [UNSPEC_CADD90 2528 UNSPEC_CADD270 2529 UNSPEC_SQCADD90 2530 UNSPEC_SQCADD270]) 2531 2532(define_int_iterator SVE2_INT_BITPERM [UNSPEC_BDEP UNSPEC_BEXT UNSPEC_BGRP]) 2533 2534(define_int_iterator SVE2_INT_TERNARY [UNSPEC_ADCLB 2535 UNSPEC_ADCLT 2536 UNSPEC_EORBT 2537 UNSPEC_EORTB 2538 UNSPEC_SBCLB 2539 UNSPEC_SBCLT 2540 UNSPEC_SQRDMLAH 2541 UNSPEC_SQRDMLSH]) 2542 2543(define_int_iterator SVE2_INT_TERNARY_LANE [UNSPEC_SQRDMLAH 2544 UNSPEC_SQRDMLSH]) 2545 2546(define_int_iterator SVE2_FP_TERNARY_LONG [UNSPEC_FMLALB 2547 UNSPEC_FMLALT 2548 UNSPEC_FMLSLB 2549 UNSPEC_FMLSLT]) 2550 2551(define_int_iterator SVE2_FP_TERNARY_LONG_LANE [UNSPEC_FMLALB 2552 UNSPEC_FMLALT 2553 UNSPEC_FMLSLB 2554 UNSPEC_FMLSLT]) 2555 2556(define_int_iterator SVE2_INT_CMLA [UNSPEC_CMLA 2557 UNSPEC_CMLA90 2558 UNSPEC_CMLA180 2559 UNSPEC_CMLA270 2560 UNSPEC_SQRDCMLAH 2561 UNSPEC_SQRDCMLAH90 2562 UNSPEC_SQRDCMLAH180 2563 UNSPEC_SQRDCMLAH270]) 2564 2565(define_int_iterator SVE2_INT_CDOT [UNSPEC_CDOT 2566 UNSPEC_CDOT90 2567 UNSPEC_CDOT180 2568 UNSPEC_CDOT270]) 2569 2570(define_int_iterator SVE2_INT_ADD_BINARY_LONG [UNSPEC_SABDLB 2571 UNSPEC_SABDLT 2572 UNSPEC_SMULLB 2573 UNSPEC_SMULLT 2574 UNSPEC_UABDLB 2575 UNSPEC_UABDLT 2576 UNSPEC_UMULLB 2577 UNSPEC_UMULLT]) 2578 2579(define_int_iterator SVE2_INT_QADD_BINARY_LONG [UNSPEC_SQDMULLB 2580 UNSPEC_SQDMULLBT 2581 UNSPEC_SQDMULLT]) 2582 2583(define_int_iterator SVE2_INT_SUB_BINARY_LONG [UNSPEC_SMULLB 2584 UNSPEC_SMULLT 2585 UNSPEC_UMULLB 2586 UNSPEC_UMULLT]) 2587 2588(define_int_iterator SVE2_INT_QSUB_BINARY_LONG [UNSPEC_SQDMULLB 2589 UNSPEC_SQDMULLBT 2590 UNSPEC_SQDMULLT]) 2591 2592(define_int_iterator SVE2_INT_ADD_BINARY_LONG_LANE [UNSPEC_SMULLB 2593 UNSPEC_SMULLT 2594 UNSPEC_UMULLB 2595 UNSPEC_UMULLT]) 2596 2597(define_int_iterator SVE2_INT_QADD_BINARY_LONG_LANE [UNSPEC_SQDMULLB 2598 UNSPEC_SQDMULLT]) 2599 2600(define_int_iterator SVE2_INT_SUB_BINARY_LONG_LANE [UNSPEC_SMULLB 2601 UNSPEC_SMULLT 2602 UNSPEC_UMULLB 2603 UNSPEC_UMULLT]) 2604 2605(define_int_iterator SVE2_INT_QSUB_BINARY_LONG_LANE [UNSPEC_SQDMULLB 2606 UNSPEC_SQDMULLT]) 2607 2608(define_int_iterator SVE2_COND_INT_UNARY_FP [UNSPEC_COND_FLOGB]) 2609 2610(define_int_iterator SVE2_COND_FP_UNARY_LONG [UNSPEC_COND_FCVTLT]) 2611 2612(define_int_iterator SVE2_COND_FP_UNARY_NARROWB [UNSPEC_COND_FCVTX]) 2613 2614(define_int_iterator SVE2_COND_INT_BINARY [UNSPEC_SHADD 2615 UNSPEC_SHSUB 2616 UNSPEC_SQRSHL 2617 UNSPEC_SRHADD 2618 UNSPEC_SRSHL 2619 UNSPEC_SUQADD 2620 UNSPEC_UHADD 2621 UNSPEC_UHSUB 2622 UNSPEC_UQRSHL 2623 UNSPEC_URHADD 2624 UNSPEC_URSHL 2625 UNSPEC_USQADD]) 2626 2627(define_int_iterator SVE2_COND_INT_BINARY_NOREV [UNSPEC_SUQADD 2628 UNSPEC_USQADD]) 2629 2630(define_int_iterator SVE2_COND_INT_BINARY_REV [UNSPEC_SHADD 2631 UNSPEC_SHSUB 2632 UNSPEC_SQRSHL 2633 UNSPEC_SRHADD 2634 UNSPEC_SRSHL 2635 UNSPEC_UHADD 2636 UNSPEC_UHSUB 2637 UNSPEC_UQRSHL 2638 UNSPEC_URHADD 2639 UNSPEC_URSHL]) 2640 2641(define_int_iterator SVE2_COND_INT_SHIFT [UNSPEC_SQSHL 2642 UNSPEC_UQSHL]) 2643 2644(define_int_iterator SVE2_MATCH [UNSPEC_MATCH UNSPEC_NMATCH]) 2645 2646(define_int_iterator SVE2_PMULL [UNSPEC_PMULLB UNSPEC_PMULLT]) 2647 2648(define_int_iterator SVE2_PMULL_PAIR [UNSPEC_PMULLB_PAIR UNSPEC_PMULLT_PAIR]) 2649 2650(define_int_iterator FCADD [UNSPEC_FCADD90 2651 UNSPEC_FCADD270]) 2652 2653(define_int_iterator FCMLA [UNSPEC_FCMLA 2654 UNSPEC_FCMLA90 2655 UNSPEC_FCMLA180 2656 UNSPEC_FCMLA270]) 2657 2658(define_int_iterator FRINTNZX [UNSPEC_FRINT32Z UNSPEC_FRINT32X 2659 UNSPEC_FRINT64Z UNSPEC_FRINT64X]) 2660 2661(define_int_iterator SVE_BRK_UNARY [UNSPEC_BRKA UNSPEC_BRKB]) 2662 2663(define_int_iterator SVE_BRKP [UNSPEC_BRKPA UNSPEC_BRKPB]) 2664 2665(define_int_iterator SVE_BRK_BINARY [UNSPEC_BRKN UNSPEC_BRKPA UNSPEC_BRKPB]) 2666 2667(define_int_iterator SVE_PITER [UNSPEC_PFIRST UNSPEC_PNEXT]) 2668 2669(define_int_iterator MATMUL [UNSPEC_SMATMUL UNSPEC_UMATMUL 2670 UNSPEC_USMATMUL]) 2671 2672(define_int_iterator FMMLA [UNSPEC_FMMLA]) 2673 2674(define_int_iterator BF_MLA [UNSPEC_BFMLALB 2675 UNSPEC_BFMLALT]) 2676 2677;; Iterators for atomic operations. 2678 2679(define_int_iterator ATOMIC_LDOP 2680 [UNSPECV_ATOMIC_LDOP_OR UNSPECV_ATOMIC_LDOP_BIC 2681 UNSPECV_ATOMIC_LDOP_XOR UNSPECV_ATOMIC_LDOP_PLUS]) 2682 2683(define_int_attr atomic_ldop 2684 [(UNSPECV_ATOMIC_LDOP_OR "set") (UNSPECV_ATOMIC_LDOP_BIC "clr") 2685 (UNSPECV_ATOMIC_LDOP_XOR "eor") (UNSPECV_ATOMIC_LDOP_PLUS "add")]) 2686 2687(define_int_attr atomic_ldoptab 2688 [(UNSPECV_ATOMIC_LDOP_OR "ior") (UNSPECV_ATOMIC_LDOP_BIC "bic") 2689 (UNSPECV_ATOMIC_LDOP_XOR "xor") (UNSPECV_ATOMIC_LDOP_PLUS "add")]) 2690 2691;; ------------------------------------------------------------------- 2692;; Int Iterators Attributes. 2693;; ------------------------------------------------------------------- 2694 2695;; The optab associated with an operation. Note that for ANDF, IORF 2696;; and XORF, the optab pattern is not actually defined; we just use this 2697;; name for consistency with the integer patterns. 2698(define_int_attr optab [(UNSPEC_ANDF "and") 2699 (UNSPEC_IORF "ior") 2700 (UNSPEC_XORF "xor") 2701 (UNSPEC_SADDV "sadd") 2702 (UNSPEC_UADDV "uadd") 2703 (UNSPEC_ANDV "and") 2704 (UNSPEC_IORV "ior") 2705 (UNSPEC_XORV "xor") 2706 (UNSPEC_FRECPE "frecpe") 2707 (UNSPEC_FRECPS "frecps") 2708 (UNSPEC_RSQRTE "frsqrte") 2709 (UNSPEC_RSQRTS "frsqrts") 2710 (UNSPEC_RBIT "rbit") 2711 (UNSPEC_REVB "revb") 2712 (UNSPEC_REVH "revh") 2713 (UNSPEC_REVW "revw") 2714 (UNSPEC_UMAXV "umax") 2715 (UNSPEC_UMINV "umin") 2716 (UNSPEC_SMAXV "smax") 2717 (UNSPEC_SMINV "smin") 2718 (UNSPEC_CADD90 "cadd90") 2719 (UNSPEC_CADD270 "cadd270") 2720 (UNSPEC_CDOT "cdot") 2721 (UNSPEC_CDOT90 "cdot90") 2722 (UNSPEC_CDOT180 "cdot180") 2723 (UNSPEC_CDOT270 "cdot270") 2724 (UNSPEC_CMLA "cmla") 2725 (UNSPEC_CMLA90 "cmla90") 2726 (UNSPEC_CMLA180 "cmla180") 2727 (UNSPEC_CMLA270 "cmla270") 2728 (UNSPEC_FADDV "plus") 2729 (UNSPEC_FMAXNMV "smax") 2730 (UNSPEC_FMAXV "smax_nan") 2731 (UNSPEC_FMINNMV "smin") 2732 (UNSPEC_FMINV "smin_nan") 2733 (UNSPEC_SMUL_HIGHPART "smulh") 2734 (UNSPEC_UMUL_HIGHPART "umulh") 2735 (UNSPEC_FMLA "fma") 2736 (UNSPEC_FMLS "fnma") 2737 (UNSPEC_FCMLA "fcmla") 2738 (UNSPEC_FCMLA90 "fcmla90") 2739 (UNSPEC_FCMLA180 "fcmla180") 2740 (UNSPEC_FCMLA270 "fcmla270") 2741 (UNSPEC_FEXPA "fexpa") 2742 (UNSPEC_FTSMUL "ftsmul") 2743 (UNSPEC_FTSSEL "ftssel") 2744 (UNSPEC_PMULLB "pmullb") 2745 (UNSPEC_PMULLB_PAIR "pmullb_pair") 2746 (UNSPEC_PMULLT "pmullt") 2747 (UNSPEC_PMULLT_PAIR "pmullt_pair") 2748 (UNSPEC_SMATMUL "smatmul") 2749 (UNSPEC_SQCADD90 "sqcadd90") 2750 (UNSPEC_SQCADD270 "sqcadd270") 2751 (UNSPEC_SQRDCMLAH "sqrdcmlah") 2752 (UNSPEC_SQRDCMLAH90 "sqrdcmlah90") 2753 (UNSPEC_SQRDCMLAH180 "sqrdcmlah180") 2754 (UNSPEC_SQRDCMLAH270 "sqrdcmlah270") 2755 (UNSPEC_TRN1Q "trn1q") 2756 (UNSPEC_TRN2Q "trn2q") 2757 (UNSPEC_UMATMUL "umatmul") 2758 (UNSPEC_USMATMUL "usmatmul") 2759 (UNSPEC_UZP1Q "uzp1q") 2760 (UNSPEC_UZP2Q "uzp2q") 2761 (UNSPEC_WHILERW "vec_check_raw_alias") 2762 (UNSPEC_WHILEWR "vec_check_war_alias") 2763 (UNSPEC_ZIP1Q "zip1q") 2764 (UNSPEC_ZIP2Q "zip2q") 2765 (UNSPEC_COND_FABS "abs") 2766 (UNSPEC_COND_FADD "add") 2767 (UNSPEC_COND_FCADD90 "cadd90") 2768 (UNSPEC_COND_FCADD270 "cadd270") 2769 (UNSPEC_COND_FCMLA "fcmla") 2770 (UNSPEC_COND_FCMLA90 "fcmla90") 2771 (UNSPEC_COND_FCMLA180 "fcmla180") 2772 (UNSPEC_COND_FCMLA270 "fcmla270") 2773 (UNSPEC_COND_FCVT "fcvt") 2774 (UNSPEC_COND_FCVTZS "fix_trunc") 2775 (UNSPEC_COND_FCVTZU "fixuns_trunc") 2776 (UNSPEC_COND_FDIV "div") 2777 (UNSPEC_COND_FMAX "smax_nan") 2778 (UNSPEC_COND_FMAXNM "smax") 2779 (UNSPEC_COND_FMIN "smin_nan") 2780 (UNSPEC_COND_FMINNM "smin") 2781 (UNSPEC_COND_FMLA "fma") 2782 (UNSPEC_COND_FMLS "fnma") 2783 (UNSPEC_COND_FMUL "mul") 2784 (UNSPEC_COND_FMULX "mulx") 2785 (UNSPEC_COND_FNEG "neg") 2786 (UNSPEC_COND_FNMLA "fnms") 2787 (UNSPEC_COND_FNMLS "fms") 2788 (UNSPEC_COND_FRECPX "frecpx") 2789 (UNSPEC_COND_FRINTA "round") 2790 (UNSPEC_COND_FRINTI "nearbyint") 2791 (UNSPEC_COND_FRINTM "floor") 2792 (UNSPEC_COND_FRINTN "frintn") 2793 (UNSPEC_COND_FRINTP "ceil") 2794 (UNSPEC_COND_FRINTX "rint") 2795 (UNSPEC_COND_FRINTZ "btrunc") 2796 (UNSPEC_COND_FSCALE "fscale") 2797 (UNSPEC_COND_FSQRT "sqrt") 2798 (UNSPEC_COND_FSUB "sub") 2799 (UNSPEC_COND_SCVTF "float") 2800 (UNSPEC_COND_UCVTF "floatuns")]) 2801 2802(define_int_attr maxmin_uns [(UNSPEC_UMAXV "umax") 2803 (UNSPEC_UMINV "umin") 2804 (UNSPEC_SMAXV "smax") 2805 (UNSPEC_SMINV "smin") 2806 (UNSPEC_FMAX "smax_nan") 2807 (UNSPEC_FMAXNMV "smax") 2808 (UNSPEC_FMAXV "smax_nan") 2809 (UNSPEC_FMIN "smin_nan") 2810 (UNSPEC_FMINNMV "smin") 2811 (UNSPEC_FMINV "smin_nan") 2812 (UNSPEC_FMAXNM "fmax") 2813 (UNSPEC_FMINNM "fmin") 2814 (UNSPEC_COND_FMAX "fmax_nan") 2815 (UNSPEC_COND_FMAXNM "fmax") 2816 (UNSPEC_COND_FMIN "fmin_nan") 2817 (UNSPEC_COND_FMINNM "fmin")]) 2818 2819(define_int_attr maxmin_uns_op [(UNSPEC_UMAXV "umax") 2820 (UNSPEC_UMINV "umin") 2821 (UNSPEC_SMAXV "smax") 2822 (UNSPEC_SMINV "smin") 2823 (UNSPEC_FMAX "fmax") 2824 (UNSPEC_FMAXNMV "fmaxnm") 2825 (UNSPEC_FMAXV "fmax") 2826 (UNSPEC_FMIN "fmin") 2827 (UNSPEC_FMINNMV "fminnm") 2828 (UNSPEC_FMINV "fmin") 2829 (UNSPEC_FMAXNM "fmaxnm") 2830 (UNSPEC_FMINNM "fminnm")]) 2831 2832(define_code_attr binqops_op [(ss_plus "sqadd") 2833 (us_plus "uqadd") 2834 (ss_minus "sqsub") 2835 (us_minus "uqsub")]) 2836 2837(define_code_attr binqops_op_rev [(ss_plus "sqsub") 2838 (ss_minus "sqadd")]) 2839 2840;; The SVE logical instruction that implements an unspec. 2841(define_int_attr logicalf_op [(UNSPEC_ANDF "and") 2842 (UNSPEC_IORF "orr") 2843 (UNSPEC_XORF "eor")]) 2844 2845(define_int_attr last_op [(UNSPEC_CLASTA "after_last") 2846 (UNSPEC_CLASTB "last") 2847 (UNSPEC_LASTA "after_last") 2848 (UNSPEC_LASTB "last")]) 2849 2850;; "s" for signed operations and "u" for unsigned ones. 2851(define_int_attr su [(UNSPEC_SADDV "s") 2852 (UNSPEC_UADDV "u") 2853 (UNSPEC_UNPACKSHI "s") 2854 (UNSPEC_UNPACKUHI "u") 2855 (UNSPEC_UNPACKSLO "s") 2856 (UNSPEC_UNPACKULO "u") 2857 (UNSPEC_SMUL_HIGHPART "s") 2858 (UNSPEC_UMUL_HIGHPART "u") 2859 (UNSPEC_COND_FCVTZS "s") 2860 (UNSPEC_COND_FCVTZU "u") 2861 (UNSPEC_COND_SCVTF "s") 2862 (UNSPEC_COND_UCVTF "u") 2863 (UNSPEC_SMULHS "s") (UNSPEC_UMULHS "u") 2864 (UNSPEC_SMULHRS "s") (UNSPEC_UMULHRS "u")]) 2865 2866(define_int_attr sur [(UNSPEC_SHADD "s") (UNSPEC_UHADD "u") 2867 (UNSPEC_SRHADD "sr") (UNSPEC_URHADD "ur") 2868 (UNSPEC_SHSUB "s") (UNSPEC_UHSUB "u") 2869 (UNSPEC_ADDHN "") (UNSPEC_RADDHN "r") 2870 (UNSPEC_SABAL "s") (UNSPEC_UABAL "u") 2871 (UNSPEC_SABDL2 "s") (UNSPEC_UABDL2 "u") 2872 (UNSPEC_SADALP "s") (UNSPEC_UADALP "u") 2873 (UNSPEC_SUBHN "") (UNSPEC_RSUBHN "r") 2874 (UNSPEC_ADDHN2 "") (UNSPEC_RADDHN2 "r") 2875 (UNSPEC_SUBHN2 "") (UNSPEC_RSUBHN2 "r") 2876 (UNSPEC_SQXTN "s") (UNSPEC_UQXTN "u") 2877 (UNSPEC_USQADD "us") (UNSPEC_SUQADD "su") 2878 (UNSPEC_SSLI "s") (UNSPEC_USLI "u") 2879 (UNSPEC_SSRI "s") (UNSPEC_USRI "u") 2880 (UNSPEC_USRA "u") (UNSPEC_SSRA "s") 2881 (UNSPEC_URSRA "ur") (UNSPEC_SRSRA "sr") 2882 (UNSPEC_URSHR "ur") (UNSPEC_SRSHR "sr") 2883 (UNSPEC_SQSHLU "s") (UNSPEC_SQSHL "s") 2884 (UNSPEC_UQSHL "u") 2885 (UNSPEC_SQSHRUN "s") (UNSPEC_SQRSHRUN "s") 2886 (UNSPEC_SQSHRN "s") (UNSPEC_UQSHRN "u") 2887 (UNSPEC_SQRSHRN "s") (UNSPEC_UQRSHRN "u") 2888 (UNSPEC_USHL "u") (UNSPEC_SSHL "s") 2889 (UNSPEC_USHLL "u") (UNSPEC_SSHLL "s") 2890 (UNSPEC_URSHL "ur") (UNSPEC_SRSHL "sr") 2891 (UNSPEC_UQRSHL "u") (UNSPEC_SQRSHL "s") 2892 (UNSPEC_SDOT "s") (UNSPEC_UDOT "u") 2893 (UNSPEC_USDOT "us") (UNSPEC_SUDOT "su") 2894 (UNSPEC_SMATMUL "s") (UNSPEC_UMATMUL "u") 2895 (UNSPEC_USMATMUL "us") 2896]) 2897 2898(define_int_attr r [(UNSPEC_SQDMULH "") (UNSPEC_SQRDMULH "r") 2899 (UNSPEC_SQSHRUN "") (UNSPEC_SQRSHRUN "r") 2900 (UNSPEC_SQSHRN "") (UNSPEC_UQSHRN "") 2901 (UNSPEC_SQRSHRN "r") (UNSPEC_UQRSHRN "r") 2902 (UNSPEC_SQSHL "") (UNSPEC_UQSHL "") 2903 (UNSPEC_SQRSHL "r")(UNSPEC_UQRSHL "r") 2904 (UNSPEC_SMULHS "") (UNSPEC_UMULHS "") 2905 (UNSPEC_SMULHRS "r") (UNSPEC_UMULHRS "r") 2906]) 2907 2908(define_int_attr lr [(UNSPEC_SSLI "l") (UNSPEC_USLI "l") 2909 (UNSPEC_SSRI "r") (UNSPEC_USRI "r") 2910 (UNSPEC_SQSHL "l") (UNSPEC_UQSHL "l") 2911 (UNSPEC_SQSHLU "l") 2912 (UNSPEC_SRSHR "r") (UNSPEC_URSHR "r") 2913 (UNSPEC_ASRD "r") 2914 (UNSPEC_SLI "l") (UNSPEC_SRI "r")]) 2915 2916(define_int_attr u [(UNSPEC_SQSHLU "u") (UNSPEC_SQSHL "") (UNSPEC_UQSHL "") 2917 (UNSPEC_SQSHRUN "u") (UNSPEC_SQRSHRUN "u") 2918 (UNSPEC_SQSHRN "") (UNSPEC_UQSHRN "") 2919 (UNSPEC_SQRSHRN "") (UNSPEC_UQRSHRN "") 2920 (UNSPEC_SHADD "") (UNSPEC_UHADD "u") 2921 (UNSPEC_SRHADD "") (UNSPEC_URHADD "u")]) 2922 2923(define_int_attr fn [(UNSPEC_LDFF1 "f") (UNSPEC_LDNF1 "n")]) 2924 2925(define_int_attr ab [(UNSPEC_CLASTA "a") (UNSPEC_CLASTB "b") 2926 (UNSPEC_LASTA "a") (UNSPEC_LASTB "b")]) 2927 2928(define_int_attr bt [(UNSPEC_BFMLALB "b") (UNSPEC_BFMLALT "t")]) 2929 2930(define_int_attr addsub [(UNSPEC_SHADD "add") 2931 (UNSPEC_UHADD "add") 2932 (UNSPEC_SRHADD "add") 2933 (UNSPEC_URHADD "add") 2934 (UNSPEC_SHSUB "sub") 2935 (UNSPEC_UHSUB "sub") 2936 (UNSPEC_ADDHN "add") 2937 (UNSPEC_SUBHN "sub") 2938 (UNSPEC_RADDHN "add") 2939 (UNSPEC_RSUBHN "sub") 2940 (UNSPEC_ADDHN2 "add") 2941 (UNSPEC_SUBHN2 "sub") 2942 (UNSPEC_RADDHN2 "add") 2943 (UNSPEC_RSUBHN2 "sub")]) 2944 2945;; BSL variants: first commutative operand. 2946(define_int_attr bsl_1st [(1 "w") (2 "0")]) 2947 2948;; BSL variants: second commutative operand. 2949(define_int_attr bsl_2nd [(1 "0") (2 "w")]) 2950 2951;; BSL variants: duplicated input operand. 2952(define_int_attr bsl_dup [(1 "1") (2 "2")]) 2953 2954;; BSL variants: operand which requires preserving via movprfx. 2955(define_int_attr bsl_mov [(1 "2") (2 "1")]) 2956 2957(define_int_attr offsetlr [(UNSPEC_SSLI "") (UNSPEC_USLI "") 2958 (UNSPEC_SSRI "offset_") 2959 (UNSPEC_USRI "offset_")]) 2960 2961;; Standard pattern names for floating-point rounding instructions. 2962(define_int_attr frint_pattern [(UNSPEC_FRINTZ "btrunc") 2963 (UNSPEC_FRINTP "ceil") 2964 (UNSPEC_FRINTM "floor") 2965 (UNSPEC_FRINTI "nearbyint") 2966 (UNSPEC_FRINTX "rint") 2967 (UNSPEC_FRINTA "round") 2968 (UNSPEC_FRINTN "frintn")]) 2969 2970;; frint suffix for floating-point rounding instructions. 2971(define_int_attr frint_suffix [(UNSPEC_FRINTZ "z") (UNSPEC_FRINTP "p") 2972 (UNSPEC_FRINTM "m") (UNSPEC_FRINTI "i") 2973 (UNSPEC_FRINTX "x") (UNSPEC_FRINTA "a") 2974 (UNSPEC_FRINTN "n")]) 2975 2976(define_int_attr fcvt_pattern [(UNSPEC_FRINTZ "btrunc") (UNSPEC_FRINTA "round") 2977 (UNSPEC_FRINTP "ceil") (UNSPEC_FRINTM "floor") 2978 (UNSPEC_FRINTN "frintn")]) 2979 2980(define_int_attr fcvt_fixed_insn [(UNSPEC_SCVTF "scvtf") 2981 (UNSPEC_UCVTF "ucvtf") 2982 (UNSPEC_FCVTZS "fcvtzs") 2983 (UNSPEC_FCVTZU "fcvtzu")]) 2984 2985;; Pointer authentication mnemonic prefix. 2986(define_int_attr pauth_mnem_prefix [(UNSPEC_PACIASP "pacia") 2987 (UNSPEC_PACIBSP "pacib") 2988 (UNSPEC_PACIA1716 "pacia") 2989 (UNSPEC_PACIB1716 "pacib") 2990 (UNSPEC_AUTIASP "autia") 2991 (UNSPEC_AUTIBSP "autib") 2992 (UNSPEC_AUTIA1716 "autia") 2993 (UNSPEC_AUTIB1716 "autib")]) 2994 2995(define_int_attr pauth_key [(UNSPEC_PACIASP "AARCH64_KEY_A") 2996 (UNSPEC_PACIBSP "AARCH64_KEY_B") 2997 (UNSPEC_PACIA1716 "AARCH64_KEY_A") 2998 (UNSPEC_PACIB1716 "AARCH64_KEY_B") 2999 (UNSPEC_AUTIASP "AARCH64_KEY_A") 3000 (UNSPEC_AUTIBSP "AARCH64_KEY_B") 3001 (UNSPEC_AUTIA1716 "AARCH64_KEY_A") 3002 (UNSPEC_AUTIB1716 "AARCH64_KEY_B")]) 3003 3004;; Pointer authentication HINT number for NOP space instructions using A and 3005;; B key. 3006(define_int_attr pauth_hint_num [(UNSPEC_PACIASP "25") 3007 (UNSPEC_PACIBSP "27") 3008 (UNSPEC_AUTIASP "29") 3009 (UNSPEC_AUTIBSP "31") 3010 (UNSPEC_PACIA1716 "8") 3011 (UNSPEC_PACIB1716 "10") 3012 (UNSPEC_AUTIA1716 "12") 3013 (UNSPEC_AUTIB1716 "14")]) 3014 3015(define_int_attr perm_insn [(UNSPEC_ZIP1 "zip1") (UNSPEC_ZIP2 "zip2") 3016 (UNSPEC_ZIP1Q "zip1") (UNSPEC_ZIP2Q "zip2") 3017 (UNSPEC_TRN1 "trn1") (UNSPEC_TRN2 "trn2") 3018 (UNSPEC_TRN1Q "trn1") (UNSPEC_TRN2Q "trn2") 3019 (UNSPEC_UZP1 "uzp1") (UNSPEC_UZP2 "uzp2") 3020 (UNSPEC_UZP1Q "uzp1") (UNSPEC_UZP2Q "uzp2")]) 3021 3022; op code for REV instructions (size within which elements are reversed). 3023(define_int_attr rev_op [(UNSPEC_REV64 "64") (UNSPEC_REV32 "32") 3024 (UNSPEC_REV16 "16")]) 3025 3026(define_int_attr perm_hilo [(UNSPEC_UNPACKSHI "hi") (UNSPEC_UNPACKUHI "hi") 3027 (UNSPEC_UNPACKSLO "lo") (UNSPEC_UNPACKULO "lo")]) 3028 3029;; Return true if the associated optab refers to the high-numbered lanes, 3030;; false if it refers to the low-numbered lanes. The convention is for 3031;; "hi" to refer to the low-numbered lanes (the first ones in memory) 3032;; for big-endian. 3033(define_int_attr hi_lanes_optab [(UNSPEC_UNPACKSHI "!BYTES_BIG_ENDIAN") 3034 (UNSPEC_UNPACKUHI "!BYTES_BIG_ENDIAN") 3035 (UNSPEC_UNPACKSLO "BYTES_BIG_ENDIAN") 3036 (UNSPEC_UNPACKULO "BYTES_BIG_ENDIAN")]) 3037 3038(define_int_attr crc_variant [(UNSPEC_CRC32B "crc32b") (UNSPEC_CRC32H "crc32h") 3039 (UNSPEC_CRC32W "crc32w") (UNSPEC_CRC32X "crc32x") 3040 (UNSPEC_CRC32CB "crc32cb") (UNSPEC_CRC32CH "crc32ch") 3041 (UNSPEC_CRC32CW "crc32cw") (UNSPEC_CRC32CX "crc32cx")]) 3042 3043(define_int_attr crc_mode [(UNSPEC_CRC32B "QI") (UNSPEC_CRC32H "HI") 3044 (UNSPEC_CRC32W "SI") (UNSPEC_CRC32X "DI") 3045 (UNSPEC_CRC32CB "QI") (UNSPEC_CRC32CH "HI") 3046 (UNSPEC_CRC32CW "SI") (UNSPEC_CRC32CX "DI")]) 3047 3048(define_int_attr aes_op [(UNSPEC_AESE "e") (UNSPEC_AESD "d")]) 3049(define_int_attr aesmc_op [(UNSPEC_AESMC "mc") (UNSPEC_AESIMC "imc")]) 3050 3051(define_int_attr sha1_op [(UNSPEC_SHA1C "c") (UNSPEC_SHA1P "p") 3052 (UNSPEC_SHA1M "m")]) 3053 3054(define_int_attr sha256_op [(UNSPEC_SHA256H "") (UNSPEC_SHA256H2 "2")]) 3055 3056(define_int_attr rdma_as [(UNSPEC_SQRDMLAH "a") (UNSPEC_SQRDMLSH "s")]) 3057 3058(define_int_attr sha512_op [(UNSPEC_SHA512H "") (UNSPEC_SHA512H2 "2")]) 3059 3060(define_int_attr sm3tt_op [(UNSPEC_SM3TT1A "1a") (UNSPEC_SM3TT1B "1b") 3061 (UNSPEC_SM3TT2A "2a") (UNSPEC_SM3TT2B "2b")]) 3062 3063(define_int_attr sm3part_op [(UNSPEC_SM3PARTW1 "1") (UNSPEC_SM3PARTW2 "2")]) 3064 3065(define_int_attr f16mac1 [(UNSPEC_FMLAL "a") (UNSPEC_FMLSL "s") 3066 (UNSPEC_FMLAL2 "a") (UNSPEC_FMLSL2 "s")]) 3067 3068(define_int_attr frintnzs_op [(UNSPEC_FRINT32Z "frint32z") (UNSPEC_FRINT32X "frint32x") 3069 (UNSPEC_FRINT64Z "frint64z") (UNSPEC_FRINT64X "frint64x")]) 3070 3071;; The condition associated with an UNSPEC_COND_<xx>. 3072(define_int_attr cmp_op [(UNSPEC_COND_CMPEQ_WIDE "eq") 3073 (UNSPEC_COND_CMPGE_WIDE "ge") 3074 (UNSPEC_COND_CMPGT_WIDE "gt") 3075 (UNSPEC_COND_CMPHI_WIDE "hi") 3076 (UNSPEC_COND_CMPHS_WIDE "hs") 3077 (UNSPEC_COND_CMPLE_WIDE "le") 3078 (UNSPEC_COND_CMPLO_WIDE "lo") 3079 (UNSPEC_COND_CMPLS_WIDE "ls") 3080 (UNSPEC_COND_CMPLT_WIDE "lt") 3081 (UNSPEC_COND_CMPNE_WIDE "ne") 3082 (UNSPEC_COND_FCMEQ "eq") 3083 (UNSPEC_COND_FCMGE "ge") 3084 (UNSPEC_COND_FCMGT "gt") 3085 (UNSPEC_COND_FCMLE "le") 3086 (UNSPEC_COND_FCMLT "lt") 3087 (UNSPEC_COND_FCMNE "ne") 3088 (UNSPEC_WHILEGE "ge") 3089 (UNSPEC_WHILEGT "gt") 3090 (UNSPEC_WHILEHI "hi") 3091 (UNSPEC_WHILEHS "hs") 3092 (UNSPEC_WHILELE "le") 3093 (UNSPEC_WHILELO "lo") 3094 (UNSPEC_WHILELS "ls") 3095 (UNSPEC_WHILELT "lt") 3096 (UNSPEC_WHILERW "rw") 3097 (UNSPEC_WHILEWR "wr")]) 3098 3099(define_int_attr while_optab_cmp [(UNSPEC_WHILEGE "ge") 3100 (UNSPEC_WHILEGT "gt") 3101 (UNSPEC_WHILEHI "ugt") 3102 (UNSPEC_WHILEHS "uge") 3103 (UNSPEC_WHILELE "le") 3104 (UNSPEC_WHILELO "ult") 3105 (UNSPEC_WHILELS "ule") 3106 (UNSPEC_WHILELT "lt") 3107 (UNSPEC_WHILERW "rw") 3108 (UNSPEC_WHILEWR "wr")]) 3109 3110(define_int_attr raw_war [(UNSPEC_WHILERW "raw") 3111 (UNSPEC_WHILEWR "war")]) 3112 3113(define_int_attr brk_op [(UNSPEC_BRKA "a") (UNSPEC_BRKB "b") 3114 (UNSPEC_BRKN "n") 3115 (UNSPEC_BRKPA "pa") (UNSPEC_BRKPB "pb")]) 3116 3117(define_int_attr sve_pred_op [(UNSPEC_PFIRST "pfirst") (UNSPEC_PNEXT "pnext")]) 3118 3119(define_int_attr sve_int_op [(UNSPEC_ADCLB "adclb") 3120 (UNSPEC_ADCLT "adclt") 3121 (UNSPEC_ADDHNB "addhnb") 3122 (UNSPEC_ADDHNT "addhnt") 3123 (UNSPEC_ADDP "addp") 3124 (UNSPEC_ANDV "andv") 3125 (UNSPEC_ASHIFTRT_WIDE "asr") 3126 (UNSPEC_ASHIFT_WIDE "lsl") 3127 (UNSPEC_ASRD "asrd") 3128 (UNSPEC_BDEP "bdep") 3129 (UNSPEC_BEXT "bext") 3130 (UNSPEC_BGRP "bgrp") 3131 (UNSPEC_CADD90 "cadd") 3132 (UNSPEC_CADD270 "cadd") 3133 (UNSPEC_CDOT "cdot") 3134 (UNSPEC_CDOT90 "cdot") 3135 (UNSPEC_CDOT180 "cdot") 3136 (UNSPEC_CDOT270 "cdot") 3137 (UNSPEC_CMLA "cmla") 3138 (UNSPEC_CMLA90 "cmla") 3139 (UNSPEC_CMLA180 "cmla") 3140 (UNSPEC_CMLA270 "cmla") 3141 (UNSPEC_EORBT "eorbt") 3142 (UNSPEC_EORTB "eortb") 3143 (UNSPEC_IORV "orv") 3144 (UNSPEC_LSHIFTRT_WIDE "lsr") 3145 (UNSPEC_MATCH "match") 3146 (UNSPEC_NMATCH "nmatch") 3147 (UNSPEC_PMULLB "pmullb") 3148 (UNSPEC_PMULLB_PAIR "pmullb") 3149 (UNSPEC_PMULLT "pmullt") 3150 (UNSPEC_PMULLT_PAIR "pmullt") 3151 (UNSPEC_RADDHNB "raddhnb") 3152 (UNSPEC_RADDHNT "raddhnt") 3153 (UNSPEC_RBIT "rbit") 3154 (UNSPEC_REVB "revb") 3155 (UNSPEC_REVH "revh") 3156 (UNSPEC_REVW "revw") 3157 (UNSPEC_RSHRNB "rshrnb") 3158 (UNSPEC_RSHRNT "rshrnt") 3159 (UNSPEC_RSQRTE "ursqrte") 3160 (UNSPEC_RSUBHNB "rsubhnb") 3161 (UNSPEC_RSUBHNT "rsubhnt") 3162 (UNSPEC_SABDLB "sabdlb") 3163 (UNSPEC_SABDLT "sabdlt") 3164 (UNSPEC_SADALP "sadalp") 3165 (UNSPEC_SADDLB "saddlb") 3166 (UNSPEC_SADDLBT "saddlbt") 3167 (UNSPEC_SADDLT "saddlt") 3168 (UNSPEC_SADDWB "saddwb") 3169 (UNSPEC_SADDWT "saddwt") 3170 (UNSPEC_SBCLB "sbclb") 3171 (UNSPEC_SBCLT "sbclt") 3172 (UNSPEC_SHADD "shadd") 3173 (UNSPEC_SHRNB "shrnb") 3174 (UNSPEC_SHRNT "shrnt") 3175 (UNSPEC_SHSUB "shsub") 3176 (UNSPEC_SLI "sli") 3177 (UNSPEC_SMAXP "smaxp") 3178 (UNSPEC_SMAXV "smaxv") 3179 (UNSPEC_SMINP "sminp") 3180 (UNSPEC_SMINV "sminv") 3181 (UNSPEC_SMUL_HIGHPART "smulh") 3182 (UNSPEC_SMULLB "smullb") 3183 (UNSPEC_SMULLT "smullt") 3184 (UNSPEC_SQCADD90 "sqcadd") 3185 (UNSPEC_SQCADD270 "sqcadd") 3186 (UNSPEC_SQDMULH "sqdmulh") 3187 (UNSPEC_SQDMULLB "sqdmullb") 3188 (UNSPEC_SQDMULLBT "sqdmullbt") 3189 (UNSPEC_SQDMULLT "sqdmullt") 3190 (UNSPEC_SQRDCMLAH "sqrdcmlah") 3191 (UNSPEC_SQRDCMLAH90 "sqrdcmlah") 3192 (UNSPEC_SQRDCMLAH180 "sqrdcmlah") 3193 (UNSPEC_SQRDCMLAH270 "sqrdcmlah") 3194 (UNSPEC_SQRDMLAH "sqrdmlah") 3195 (UNSPEC_SQRDMLSH "sqrdmlsh") 3196 (UNSPEC_SQRDMULH "sqrdmulh") 3197 (UNSPEC_SQRSHL "sqrshl") 3198 (UNSPEC_SQRSHRNB "sqrshrnb") 3199 (UNSPEC_SQRSHRNT "sqrshrnt") 3200 (UNSPEC_SQRSHRUNB "sqrshrunb") 3201 (UNSPEC_SQRSHRUNT "sqrshrunt") 3202 (UNSPEC_SQSHL "sqshl") 3203 (UNSPEC_SQSHLU "sqshlu") 3204 (UNSPEC_SQSHRNB "sqshrnb") 3205 (UNSPEC_SQSHRNT "sqshrnt") 3206 (UNSPEC_SQSHRUNB "sqshrunb") 3207 (UNSPEC_SQSHRUNT "sqshrunt") 3208 (UNSPEC_SQXTNB "sqxtnb") 3209 (UNSPEC_SQXTNT "sqxtnt") 3210 (UNSPEC_SQXTUNB "sqxtunb") 3211 (UNSPEC_SQXTUNT "sqxtunt") 3212 (UNSPEC_SRHADD "srhadd") 3213 (UNSPEC_SRI "sri") 3214 (UNSPEC_SRSHL "srshl") 3215 (UNSPEC_SRSHR "srshr") 3216 (UNSPEC_SSHLLB "sshllb") 3217 (UNSPEC_SSHLLT "sshllt") 3218 (UNSPEC_SSUBLB "ssublb") 3219 (UNSPEC_SSUBLBT "ssublbt") 3220 (UNSPEC_SSUBLT "ssublt") 3221 (UNSPEC_SSUBLTB "ssubltb") 3222 (UNSPEC_SSUBWB "ssubwb") 3223 (UNSPEC_SSUBWT "ssubwt") 3224 (UNSPEC_SUBHNB "subhnb") 3225 (UNSPEC_SUBHNT "subhnt") 3226 (UNSPEC_SUQADD "suqadd") 3227 (UNSPEC_UABDLB "uabdlb") 3228 (UNSPEC_UABDLT "uabdlt") 3229 (UNSPEC_UADALP "uadalp") 3230 (UNSPEC_UADDLB "uaddlb") 3231 (UNSPEC_UADDLT "uaddlt") 3232 (UNSPEC_UADDWB "uaddwb") 3233 (UNSPEC_UADDWT "uaddwt") 3234 (UNSPEC_UHADD "uhadd") 3235 (UNSPEC_UHSUB "uhsub") 3236 (UNSPEC_UMAXP "umaxp") 3237 (UNSPEC_UMAXV "umaxv") 3238 (UNSPEC_UMINP "uminp") 3239 (UNSPEC_UMINV "uminv") 3240 (UNSPEC_UMUL_HIGHPART "umulh") 3241 (UNSPEC_UMULLB "umullb") 3242 (UNSPEC_UMULLT "umullt") 3243 (UNSPEC_UQRSHL "uqrshl") 3244 (UNSPEC_UQRSHRNB "uqrshrnb") 3245 (UNSPEC_UQRSHRNT "uqrshrnt") 3246 (UNSPEC_UQSHL "uqshl") 3247 (UNSPEC_UQSHRNB "uqshrnb") 3248 (UNSPEC_UQSHRNT "uqshrnt") 3249 (UNSPEC_UQXTNB "uqxtnb") 3250 (UNSPEC_UQXTNT "uqxtnt") 3251 (UNSPEC_URECPE "urecpe") 3252 (UNSPEC_URHADD "urhadd") 3253 (UNSPEC_URSHL "urshl") 3254 (UNSPEC_URSHR "urshr") 3255 (UNSPEC_USHLLB "ushllb") 3256 (UNSPEC_USHLLT "ushllt") 3257 (UNSPEC_USQADD "usqadd") 3258 (UNSPEC_USUBLB "usublb") 3259 (UNSPEC_USUBLT "usublt") 3260 (UNSPEC_USUBWB "usubwb") 3261 (UNSPEC_USUBWT "usubwt") 3262 (UNSPEC_XORV "eorv")]) 3263 3264(define_int_attr sve_int_op_rev [(UNSPEC_SHADD "shadd") 3265 (UNSPEC_SHSUB "shsubr") 3266 (UNSPEC_SQRSHL "sqrshlr") 3267 (UNSPEC_SRHADD "srhadd") 3268 (UNSPEC_SRSHL "srshlr") 3269 (UNSPEC_UHADD "uhadd") 3270 (UNSPEC_UHSUB "uhsubr") 3271 (UNSPEC_UQRSHL "uqrshlr") 3272 (UNSPEC_URHADD "urhadd") 3273 (UNSPEC_URSHL "urshlr")]) 3274 3275(define_int_attr sve_int_add_op [(UNSPEC_SABDLB "sabalb") 3276 (UNSPEC_SABDLT "sabalt") 3277 (UNSPEC_SMULLB "smlalb") 3278 (UNSPEC_SMULLT "smlalt") 3279 (UNSPEC_UABDLB "uabalb") 3280 (UNSPEC_UABDLT "uabalt") 3281 (UNSPEC_UMULLB "umlalb") 3282 (UNSPEC_UMULLT "umlalt")]) 3283 3284(define_int_attr sve_int_qadd_op [(UNSPEC_SQDMULLB "sqdmlalb") 3285 (UNSPEC_SQDMULLBT "sqdmlalbt") 3286 (UNSPEC_SQDMULLT "sqdmlalt")]) 3287 3288(define_int_attr sve_int_sub_op [(UNSPEC_SMULLB "smlslb") 3289 (UNSPEC_SMULLT "smlslt") 3290 (UNSPEC_UMULLB "umlslb") 3291 (UNSPEC_UMULLT "umlslt")]) 3292 3293(define_int_attr sve_int_qsub_op [(UNSPEC_SQDMULLB "sqdmlslb") 3294 (UNSPEC_SQDMULLBT "sqdmlslbt") 3295 (UNSPEC_SQDMULLT "sqdmlslt")]) 3296 3297(define_int_attr sve_fp_op [(UNSPEC_BFDOT "bfdot") 3298 (UNSPEC_BFMLALB "bfmlalb") 3299 (UNSPEC_BFMLALT "bfmlalt") 3300 (UNSPEC_BFMMLA "bfmmla") 3301 (UNSPEC_FRECPE "frecpe") 3302 (UNSPEC_FRECPS "frecps") 3303 (UNSPEC_RSQRTE "frsqrte") 3304 (UNSPEC_RSQRTS "frsqrts") 3305 (UNSPEC_FADDP "faddp") 3306 (UNSPEC_FADDV "faddv") 3307 (UNSPEC_FEXPA "fexpa") 3308 (UNSPEC_FMAXNMP "fmaxnmp") 3309 (UNSPEC_FMAXNMV "fmaxnmv") 3310 (UNSPEC_FMAXP "fmaxp") 3311 (UNSPEC_FMAXV "fmaxv") 3312 (UNSPEC_FMINNMP "fminnmp") 3313 (UNSPEC_FMINNMV "fminnmv") 3314 (UNSPEC_FMINP "fminp") 3315 (UNSPEC_FMINV "fminv") 3316 (UNSPEC_FMLA "fmla") 3317 (UNSPEC_FMLALB "fmlalb") 3318 (UNSPEC_FMLALT "fmlalt") 3319 (UNSPEC_FMLS "fmls") 3320 (UNSPEC_FMLSLB "fmlslb") 3321 (UNSPEC_FMLSLT "fmlslt") 3322 (UNSPEC_FMMLA "fmmla") 3323 (UNSPEC_FTSMUL "ftsmul") 3324 (UNSPEC_FTSSEL "ftssel") 3325 (UNSPEC_COND_FABS "fabs") 3326 (UNSPEC_COND_FADD "fadd") 3327 (UNSPEC_COND_FCVTLT "fcvtlt") 3328 (UNSPEC_COND_FCVTX "fcvtx") 3329 (UNSPEC_COND_FDIV "fdiv") 3330 (UNSPEC_COND_FLOGB "flogb") 3331 (UNSPEC_COND_FMAX "fmax") 3332 (UNSPEC_COND_FMAXNM "fmaxnm") 3333 (UNSPEC_COND_FMIN "fmin") 3334 (UNSPEC_COND_FMINNM "fminnm") 3335 (UNSPEC_COND_FMUL "fmul") 3336 (UNSPEC_COND_FMULX "fmulx") 3337 (UNSPEC_COND_FNEG "fneg") 3338 (UNSPEC_COND_FRECPX "frecpx") 3339 (UNSPEC_COND_FRINTA "frinta") 3340 (UNSPEC_COND_FRINTI "frinti") 3341 (UNSPEC_COND_FRINTM "frintm") 3342 (UNSPEC_COND_FRINTN "frintn") 3343 (UNSPEC_COND_FRINTP "frintp") 3344 (UNSPEC_COND_FRINTX "frintx") 3345 (UNSPEC_COND_FRINTZ "frintz") 3346 (UNSPEC_COND_FSCALE "fscale") 3347 (UNSPEC_COND_FSQRT "fsqrt") 3348 (UNSPEC_COND_FSUB "fsub")]) 3349 3350(define_int_attr sve_fp_op_rev [(UNSPEC_COND_FADD "fadd") 3351 (UNSPEC_COND_FDIV "fdivr") 3352 (UNSPEC_COND_FMAX "fmax") 3353 (UNSPEC_COND_FMAXNM "fmaxnm") 3354 (UNSPEC_COND_FMIN "fmin") 3355 (UNSPEC_COND_FMINNM "fminnm") 3356 (UNSPEC_COND_FMUL "fmul") 3357 (UNSPEC_COND_FMULX "fmulx") 3358 (UNSPEC_COND_FSUB "fsubr")]) 3359 3360(define_int_attr rot [(UNSPEC_CADD90 "90") 3361 (UNSPEC_CADD270 "270") 3362 (UNSPEC_CDOT "0") 3363 (UNSPEC_CDOT90 "90") 3364 (UNSPEC_CDOT180 "180") 3365 (UNSPEC_CDOT270 "270") 3366 (UNSPEC_CMLA "0") 3367 (UNSPEC_CMLA90 "90") 3368 (UNSPEC_CMLA180 "180") 3369 (UNSPEC_CMLA270 "270") 3370 (UNSPEC_FCADD90 "90") 3371 (UNSPEC_FCADD270 "270") 3372 (UNSPEC_FCMLA "0") 3373 (UNSPEC_FCMLA90 "90") 3374 (UNSPEC_FCMLA180 "180") 3375 (UNSPEC_FCMLA270 "270") 3376 (UNSPEC_SQCADD90 "90") 3377 (UNSPEC_SQCADD270 "270") 3378 (UNSPEC_SQRDCMLAH "0") 3379 (UNSPEC_SQRDCMLAH90 "90") 3380 (UNSPEC_SQRDCMLAH180 "180") 3381 (UNSPEC_SQRDCMLAH270 "270") 3382 (UNSPEC_COND_FCADD90 "90") 3383 (UNSPEC_COND_FCADD270 "270") 3384 (UNSPEC_COND_FCMLA "0") 3385 (UNSPEC_COND_FCMLA90 "90") 3386 (UNSPEC_COND_FCMLA180 "180") 3387 (UNSPEC_COND_FCMLA270 "270")]) 3388 3389(define_int_attr sve_fmla_op [(UNSPEC_COND_FMLA "fmla") 3390 (UNSPEC_COND_FMLS "fmls") 3391 (UNSPEC_COND_FNMLA "fnmla") 3392 (UNSPEC_COND_FNMLS "fnmls")]) 3393 3394(define_int_attr sve_fmad_op [(UNSPEC_COND_FMLA "fmad") 3395 (UNSPEC_COND_FMLS "fmsb") 3396 (UNSPEC_COND_FNMLA "fnmad") 3397 (UNSPEC_COND_FNMLS "fnmsb")]) 3398 3399;; The register constraint to use for the final operand in a binary BRK. 3400(define_int_attr brk_reg_con [(UNSPEC_BRKN "0") 3401 (UNSPEC_BRKPA "Upa") (UNSPEC_BRKPB "Upa")]) 3402 3403;; The register number to print for the above. 3404(define_int_attr brk_reg_opno [(UNSPEC_BRKN "0") 3405 (UNSPEC_BRKPA "3") (UNSPEC_BRKPB "3")]) 3406 3407;; The predicate to use for the first input operand in a floating-point 3408;; <optab><mode>3 pattern. 3409(define_int_attr sve_pred_fp_rhs1_operand 3410 [(UNSPEC_COND_FADD "register_operand") 3411 (UNSPEC_COND_FDIV "register_operand") 3412 (UNSPEC_COND_FMAX "register_operand") 3413 (UNSPEC_COND_FMAXNM "register_operand") 3414 (UNSPEC_COND_FMIN "register_operand") 3415 (UNSPEC_COND_FMINNM "register_operand") 3416 (UNSPEC_COND_FMUL "register_operand") 3417 (UNSPEC_COND_FMULX "register_operand") 3418 (UNSPEC_COND_FSUB "aarch64_sve_float_arith_operand")]) 3419 3420;; The predicate to use for the second input operand in a floating-point 3421;; <optab><mode>3 pattern. 3422(define_int_attr sve_pred_fp_rhs2_operand 3423 [(UNSPEC_COND_FADD "aarch64_sve_float_arith_with_sub_operand") 3424 (UNSPEC_COND_FDIV "register_operand") 3425 (UNSPEC_COND_FMAX "aarch64_sve_float_maxmin_operand") 3426 (UNSPEC_COND_FMAXNM "aarch64_sve_float_maxmin_operand") 3427 (UNSPEC_COND_FMIN "aarch64_sve_float_maxmin_operand") 3428 (UNSPEC_COND_FMINNM "aarch64_sve_float_maxmin_operand") 3429 (UNSPEC_COND_FMUL "aarch64_sve_float_mul_operand") 3430 (UNSPEC_COND_FMULX "register_operand") 3431 (UNSPEC_COND_FSUB "register_operand")]) 3432 3433;; Likewise for immediates only. 3434(define_int_attr sve_pred_fp_rhs2_immediate 3435 [(UNSPEC_COND_FMAX "aarch64_sve_float_maxmin_immediate") 3436 (UNSPEC_COND_FMAXNM "aarch64_sve_float_maxmin_immediate") 3437 (UNSPEC_COND_FMIN "aarch64_sve_float_maxmin_immediate") 3438 (UNSPEC_COND_FMINNM "aarch64_sve_float_maxmin_immediate") 3439 (UNSPEC_COND_FMUL "aarch64_sve_float_mul_immediate")]) 3440 3441;; The maximum number of element bits that an instruction can handle. 3442(define_int_attr max_elem_bits [(UNSPEC_UADDV "64") (UNSPEC_SADDV "32") 3443 (UNSPEC_PFIRST "8") (UNSPEC_PNEXT "64")]) 3444 3445;; The minimum number of element bits that an instruction can handle. 3446(define_int_attr min_elem_bits [(UNSPEC_RBIT "8") 3447 (UNSPEC_REVB "16") 3448 (UNSPEC_REVH "32") 3449 (UNSPEC_REVW "64")]) 3450 3451(define_int_attr unspec [(UNSPEC_WHILERW "UNSPEC_WHILERW") 3452 (UNSPEC_WHILEWR "UNSPEC_WHILEWR")]) 3453