1;; Machine description for AArch64 architecture. 2;; Copyright (C) 2009-2020 Free Software Foundation, Inc. 3;; Contributed by ARM Ltd. 4;; 5;; This file is part of GCC. 6;; 7;; GCC is free software; you can redistribute it and/or modify it 8;; under the terms of the GNU General Public License as published by 9;; the Free Software Foundation; either version 3, or (at your option) 10;; any later version. 11;; 12;; GCC is distributed in the hope that it will be useful, but 13;; WITHOUT ANY WARRANTY; without even the implied warranty of 14;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15;; General Public License for more details. 16;; 17;; You should have received a copy of the GNU General Public License 18;; along with GCC; see the file COPYING3. If not see 19;; <http://www.gnu.org/licenses/>. 20 21(define_register_constraint "k" "STACK_REG" 22 "@internal The stack register.") 23 24(define_register_constraint "Ucs" "TAILCALL_ADDR_REGS" 25 "@internal Registers suitable for an indirect tail call") 26 27(define_register_constraint "Ucr" 28 "aarch64_harden_sls_blr_p () ? STUB_REGS : GENERAL_REGS" 29 "@internal Registers to be used for an indirect call. 30 This is usually the general registers, but when we are hardening against 31 Straight Line Speculation we disallow x16, x17, and x30 so we can use 32 indirection stubs. These indirection stubs cannot use the above registers 33 since they will be reached by a BL that may have to go through a linker 34 veneer.") 35 36(define_register_constraint "w" "FP_REGS" 37 "Floating point and SIMD vector registers.") 38 39(define_register_constraint "Upa" "PR_REGS" 40 "SVE predicate registers p0 - p15.") 41 42(define_register_constraint "Upl" "PR_LO_REGS" 43 "SVE predicate registers p0 - p7.") 44 45(define_register_constraint "x" "FP_LO_REGS" 46 "Floating point and SIMD vector registers V0 - V15.") 47 48(define_register_constraint "y" "FP_LO8_REGS" 49 "Floating point and SIMD vector registers V0 - V7.") 50 51(define_constraint "c" 52 "@internal The condition code register." 53 (match_operand 0 "cc_register")) 54 55(define_constraint "I" 56 "A constant that can be used with an ADD operation." 57 (and (match_code "const_int") 58 (match_test "aarch64_uimm12_shift (ival)"))) 59 60(define_constraint "Uaa" 61 "@internal A constant that matches two uses of add instructions." 62 (and (match_code "const_int") 63 (match_test "aarch64_pluslong_strict_immedate (op, VOIDmode)"))) 64 65(define_constraint "Uai" 66 "@internal 67 A constraint that matches a VG-based constant that can be added by 68 a single INC or DEC." 69 (match_operand 0 "aarch64_sve_scalar_inc_dec_immediate")) 70 71(define_constraint "Uav" 72 "@internal 73 A constraint that matches a VG-based constant that can be added by 74 a single ADDVL or ADDPL." 75 (match_operand 0 "aarch64_sve_addvl_addpl_immediate")) 76 77(define_constraint "Uat" 78 "@internal 79 A constraint that matches a VG-based constant that can be added by 80 using multiple instructions, with one temporary register." 81 (match_operand 0 "aarch64_split_add_offset_immediate")) 82 83(define_constraint "J" 84 "A constant that can be used with a SUB operation (once negated)." 85 (and (match_code "const_int") 86 (match_test "aarch64_uimm12_shift (-ival)"))) 87 88;; We can't use the mode of a CONST_INT to determine the context in 89;; which it is being used, so we must have a separate constraint for 90;; each context. 91 92(define_constraint "K" 93 "A constant that can be used with a 32-bit logical operation." 94 (and (match_code "const_int") 95 (match_test "aarch64_bitmask_imm (ival, SImode)"))) 96 97(define_constraint "L" 98 "A constant that can be used with a 64-bit logical operation." 99 (and (match_code "const_int") 100 (match_test "aarch64_bitmask_imm (ival, DImode)"))) 101 102(define_constraint "M" 103 "A constant that can be used with a 32-bit MOV immediate operation." 104 (and (match_code "const_int") 105 (match_test "aarch64_move_imm (ival, SImode)"))) 106 107(define_constraint "N" 108 "A constant that can be used with a 64-bit MOV immediate operation." 109 (and (match_code "const_int") 110 (match_test "aarch64_move_imm (ival, DImode)"))) 111 112(define_constraint "Uti" 113 "A constant that can be used with a 128-bit MOV immediate operation." 114 (and (ior (match_code "const_int") 115 (match_code "const_wide_int")) 116 (match_test "aarch64_mov128_immediate (op)"))) 117 118(define_constraint "UsO" 119 "A constant that can be used with a 32-bit and operation." 120 (and (match_code "const_int") 121 (match_test "aarch64_and_bitmask_imm (ival, SImode)"))) 122 123(define_constraint "UsP" 124 "A constant that can be used with a 64-bit and operation." 125 (and (match_code "const_int") 126 (match_test "aarch64_and_bitmask_imm (ival, DImode)"))) 127 128(define_constraint "S" 129 "A constraint that matches an absolute symbolic address." 130 (and (match_code "const,symbol_ref,label_ref") 131 (match_test "aarch64_symbolic_address_p (op)"))) 132 133(define_constraint "Y" 134 "Floating point constant zero." 135 (and (match_code "const_double") 136 (match_test "aarch64_float_const_zero_rtx_p (op)"))) 137 138(define_constraint "Z" 139 "Integer or floating-point constant zero." 140 (match_test "op == CONST0_RTX (GET_MODE (op))")) 141 142(define_constraint "Ush" 143 "A constraint that matches an absolute symbolic address high part." 144 (and (match_code "high") 145 (match_test "aarch64_valid_symref (XEXP (op, 0), GET_MODE (XEXP (op, 0)))"))) 146 147(define_constraint "Usa" 148 "@internal 149 A constraint that matches an absolute symbolic address that can be 150 loaded by a single ADR." 151 (and (match_code "const,symbol_ref,label_ref") 152 (match_test "aarch64_symbolic_address_p (op)") 153 (match_test "aarch64_mov_operand_p (op, GET_MODE (op))"))) 154 155(define_constraint "Uss" 156 "@internal 157 A constraint that matches an immediate shift constant in SImode." 158 (and (match_code "const_int") 159 (match_test "(unsigned HOST_WIDE_INT) ival < 32"))) 160 161(define_constraint "Usn" 162 "A constant that can be used with a CCMN operation (once negated)." 163 (and (match_code "const_int") 164 (match_test "IN_RANGE (ival, -31, 0)"))) 165 166(define_constraint "Usd" 167 "@internal 168 A constraint that matches an immediate shift constant in DImode." 169 (and (match_code "const_int") 170 (match_test "(unsigned HOST_WIDE_INT) ival < 64"))) 171 172(define_constraint "Usf" 173 "@internal Usf is a symbol reference under the context where plt stub allowed." 174 (and (match_code "symbol_ref") 175 (match_test "!(aarch64_is_noplt_call_p (op) 176 || aarch64_is_long_call_p (op))"))) 177 178(define_constraint "Usg" 179 "@internal 180 A constraint that matches an immediate right shift constant in SImode 181 suitable for a SISD instruction." 182 (and (match_code "const_int") 183 (match_test "IN_RANGE (ival, 1, 31)"))) 184 185(define_constraint "Usj" 186 "@internal 187 A constraint that matches an immediate right shift constant in DImode 188 suitable for a SISD instruction." 189 (and (match_code "const_int") 190 (match_test "IN_RANGE (ival, 1, 63)"))) 191 192(define_constraint "UsM" 193 "@internal 194 A constraint that matches the immediate constant -1." 195 (match_test "op == constm1_rtx")) 196 197(define_constraint "Ulc" 198 "@internal 199 A constraint that matches a constant integer whose bits are consecutive ones 200 from the MSB." 201 (and (match_code "const_int") 202 (match_test "aarch64_high_bits_all_ones_p (ival)"))) 203 204(define_constraint "Usv" 205 "@internal 206 A constraint that matches a VG-based constant that can be loaded by 207 a single CNT[BHWD]." 208 (match_operand 0 "aarch64_sve_cnt_immediate")) 209 210(define_constraint "Usi" 211 "@internal 212 A constraint that matches an immediate operand valid for 213 the SVE INDEX instruction." 214 (match_operand 0 "aarch64_sve_index_immediate")) 215 216(define_constraint "Ui1" 217 "@internal 218 A constraint that matches the immediate constant +1." 219 (match_test "op == const1_rtx")) 220 221(define_constraint "Ui2" 222 "@internal 223 A constraint that matches the integers 0...3." 224 (and (match_code "const_int") 225 (match_test "(unsigned HOST_WIDE_INT) ival <= 3"))) 226 227(define_constraint "Ui3" 228 "@internal 229 A constraint that matches the integers 0...4." 230 (and (match_code "const_int") 231 (match_test "(unsigned HOST_WIDE_INT) ival <= 4"))) 232 233(define_constraint "Ui7" 234 "@internal 235 A constraint that matches the integers 0...7." 236 (and (match_code "const_int") 237 (match_test "(unsigned HOST_WIDE_INT) ival <= 7"))) 238 239(define_constraint "Up3" 240 "@internal 241 A constraint that matches the integers 2^(0...4)." 242 (and (match_code "const_int") 243 (match_test "(unsigned) exact_log2 (ival) <= 4"))) 244 245(define_constraint "Uph" 246 "@internal 247 A constraint that matches HImode integers zero extendable to 248 SImode plus_operand." 249 (and (match_code "const_int") 250 (match_test "aarch64_plushi_immediate (op, VOIDmode)"))) 251 252(define_memory_constraint "Q" 253 "A memory address which uses a single base register with no offset." 254 (and (match_code "mem") 255 (match_test "REG_P (XEXP (op, 0))"))) 256 257(define_memory_constraint "Ust" 258 "@internal 259 A memory address with 9bit unscaled offset." 260 (match_operand 0 "aarch64_9bit_offset_memory_operand")) 261 262(define_memory_constraint "Ump" 263 "@internal 264 A memory address suitable for a load/store pair operation." 265 (and (match_code "mem") 266 (match_test "aarch64_legitimate_address_p (GET_MODE (op), XEXP (op, 0), 267 true, ADDR_QUERY_LDP_STP)"))) 268 269;; Used for storing or loading pairs in an AdvSIMD register using an STP/LDP 270;; as a vector-concat. The address mode uses the same constraints as if it 271;; were for a single value. 272(define_memory_constraint "Umn" 273 "@internal 274 A memory address suitable for a load/store pair operation." 275 (and (match_code "mem") 276 (match_test "aarch64_legitimate_address_p (GET_MODE (op), XEXP (op, 0), 277 true, 278 ADDR_QUERY_LDP_STP_N)"))) 279 280(define_address_constraint "UPb" 281 "@internal 282 An address valid for SVE PRFB instructions." 283 (match_test "aarch64_sve_prefetch_operand_p (op, VNx16QImode)")) 284 285(define_address_constraint "UPd" 286 "@internal 287 An address valid for SVE PRFD instructions." 288 (match_test "aarch64_sve_prefetch_operand_p (op, VNx2DImode)")) 289 290(define_address_constraint "UPh" 291 "@internal 292 An address valid for SVE PRFH instructions." 293 (match_test "aarch64_sve_prefetch_operand_p (op, VNx8HImode)")) 294 295(define_address_constraint "UPw" 296 "@internal 297 An address valid for SVE PRFW instructions." 298 (match_test "aarch64_sve_prefetch_operand_p (op, VNx4SImode)")) 299 300(define_memory_constraint "Utf" 301 "@internal 302 An address valid for SVE LDFF1 instructions." 303 (and (match_code "mem") 304 (match_test "aarch64_sve_ldff1_operand_p (op)"))) 305 306(define_memory_constraint "Utn" 307 "@internal 308 An address valid for SVE LDNF1 instructions." 309 (and (match_code "mem") 310 (match_test "aarch64_sve_ldnf1_operand_p (op)"))) 311 312(define_memory_constraint "Utr" 313 "@internal 314 An address valid for SVE LDR and STR instructions (as distinct from 315 LD[1234] and ST[1234] patterns)." 316 (and (match_code "mem") 317 (match_test "aarch64_sve_ldr_operand_p (op)"))) 318 319(define_memory_constraint "Utv" 320 "@internal 321 An address valid for loading/storing opaque structure 322 types wider than TImode." 323 (and (match_code "mem") 324 (match_test "aarch64_simd_mem_operand_p (op)"))) 325 326(define_memory_constraint "Utq" 327 "@internal 328 An address valid for loading or storing a 128-bit AdvSIMD register" 329 (and (match_code "mem") 330 (match_test "aarch64_legitimate_address_p (GET_MODE (op), 331 XEXP (op, 0), 1)") 332 (match_test "aarch64_legitimate_address_p (V2DImode, 333 XEXP (op, 0), 1)"))) 334 335(define_memory_constraint "UtQ" 336 "@internal 337 An address valid for SVE LD1RQs." 338 (and (match_code "mem") 339 (match_test "aarch64_sve_ld1rq_operand_p (op)"))) 340 341(define_memory_constraint "UOb" 342 "@internal 343 An address valid for SVE LD1ROH." 344 (and (match_code "mem") 345 (match_test "aarch64_sve_ld1ro_operand_p (op, QImode)"))) 346 347(define_memory_constraint "UOh" 348 "@internal 349 An address valid for SVE LD1ROH." 350 (and (match_code "mem") 351 (match_test "aarch64_sve_ld1ro_operand_p (op, HImode)"))) 352 353 354(define_memory_constraint "UOw" 355 "@internal 356 An address valid for SVE LD1ROW." 357 (and (match_code "mem") 358 (match_test "aarch64_sve_ld1ro_operand_p (op, SImode)"))) 359 360(define_memory_constraint "UOd" 361 "@internal 362 An address valid for SVE LD1ROD." 363 (and (match_code "mem") 364 (match_test "aarch64_sve_ld1ro_operand_p (op, DImode)"))) 365 366(define_memory_constraint "Uty" 367 "@internal 368 An address valid for SVE LD1Rs." 369 (and (match_code "mem") 370 (match_test "aarch64_sve_ld1r_operand_p (op)"))) 371 372(define_memory_constraint "Utx" 373 "@internal 374 An address valid for SVE structure mov patterns (as distinct from 375 LD[234] and ST[234] patterns)." 376 (match_operand 0 "aarch64_sve_struct_memory_operand")) 377 378(define_constraint "Ufc" 379 "A floating point constant which can be used with an\ 380 FMOV immediate operation." 381 (and (match_code "const_double,const_vector") 382 (match_test "aarch64_float_const_representable_p (op)"))) 383 384(define_constraint "Uvi" 385 "A floating point constant which can be used with a\ 386 MOVI immediate operation." 387 (and (match_code "const_double") 388 (match_test "aarch64_can_const_movi_rtx_p (op, GET_MODE (op))"))) 389 390(define_constraint "Do" 391 "@internal 392 A constraint that matches vector of immediates for orr." 393 (and (match_code "const_vector") 394 (match_test "aarch64_simd_valid_immediate (op, NULL, 395 AARCH64_CHECK_ORR)"))) 396 397(define_constraint "Db" 398 "@internal 399 A constraint that matches vector of immediates for bic." 400 (and (match_code "const_vector") 401 (match_test "aarch64_simd_valid_immediate (op, NULL, 402 AARCH64_CHECK_BIC)"))) 403 404(define_constraint "Dn" 405 "@internal 406 A constraint that matches vector of immediates." 407 (and (match_code "const,const_vector") 408 (match_test "aarch64_simd_valid_immediate (op, NULL)"))) 409 410(define_constraint "Dh" 411 "@internal 412 A constraint that matches an immediate operand valid for\ 413 AdvSIMD scalar move in HImode." 414 (and (match_code "const_int") 415 (match_test "aarch64_simd_scalar_immediate_valid_for_move (op, 416 HImode)"))) 417 418(define_constraint "Dq" 419 "@internal 420 A constraint that matches an immediate operand valid for\ 421 AdvSIMD scalar move in QImode." 422 (and (match_code "const_int") 423 (match_test "aarch64_simd_scalar_immediate_valid_for_move (op, 424 QImode)"))) 425 426(define_constraint "Dt" 427 "@internal 428 A const_double which is the reciprocal of an exact power of two, can be 429 used in an scvtf with fract bits operation" 430 (and (match_code "const_double") 431 (match_test "aarch64_fpconst_pow2_recip (op) > 0"))) 432 433(define_constraint "Dl" 434 "@internal 435 A constraint that matches vector of immediates for left shifts." 436 (and (match_code "const,const_vector") 437 (match_test "aarch64_simd_shift_imm_p (op, GET_MODE (op), 438 true)"))) 439 440(define_constraint "Dr" 441 "@internal 442 A constraint that matches vector of immediates for right shifts." 443 (and (match_code "const,const_vector") 444 (match_test "aarch64_simd_shift_imm_p (op, GET_MODE (op), 445 false)"))) 446(define_constraint "Dz" 447 "@internal 448 A constraint that matches a vector of immediate zero." 449 (and (match_code "const,const_vector") 450 (match_test "op == CONST0_RTX (GET_MODE (op))"))) 451 452(define_constraint "Dm" 453 "@internal 454 A constraint that matches a vector of immediate minus one." 455 (and (match_code "const,const_vector") 456 (match_test "op == CONST1_RTX (GET_MODE (op))"))) 457 458(define_constraint "Dd" 459 "@internal 460 A constraint that matches an integer immediate operand valid\ 461 for AdvSIMD scalar operations in DImode." 462 (and (match_code "const_int") 463 (match_test "aarch64_can_const_movi_rtx_p (op, DImode)"))) 464 465(define_constraint "Ds" 466 "@internal 467 A constraint that matches an integer immediate operand valid\ 468 for AdvSIMD scalar operations in SImode." 469 (and (match_code "const_int") 470 (match_test "aarch64_can_const_movi_rtx_p (op, SImode)"))) 471 472(define_address_constraint "Dp" 473 "@internal 474 An address valid for a prefetch instruction." 475 (match_test "aarch64_address_valid_for_prefetch_p (op, true)")) 476 477(define_constraint "vgb" 478 "@internal 479 A constraint that matches an immediate offset valid for SVE LD1B 480 gather instructions." 481 (match_operand 0 "aarch64_sve_gather_immediate_b")) 482 483(define_constraint "vgd" 484 "@internal 485 A constraint that matches an immediate offset valid for SVE LD1D 486 gather instructions." 487 (match_operand 0 "aarch64_sve_gather_immediate_d")) 488 489(define_constraint "vgh" 490 "@internal 491 A constraint that matches an immediate offset valid for SVE LD1H 492 gather instructions." 493 (match_operand 0 "aarch64_sve_gather_immediate_h")) 494 495(define_constraint "vgw" 496 "@internal 497 A constraint that matches an immediate offset valid for SVE LD1W 498 gather instructions." 499 (match_operand 0 "aarch64_sve_gather_immediate_w")) 500 501(define_constraint "vsa" 502 "@internal 503 A constraint that matches an immediate operand valid for SVE 504 arithmetic instructions." 505 (match_operand 0 "aarch64_sve_arith_immediate")) 506 507(define_constraint "vsb" 508 "@internal 509 A constraint that matches an immediate operand valid for SVE UMAX 510 and UMIN operations." 511 (match_operand 0 "aarch64_sve_vsb_immediate")) 512 513(define_constraint "vsc" 514 "@internal 515 A constraint that matches a signed immediate operand valid for SVE 516 CMP instructions." 517 (match_operand 0 "aarch64_sve_cmp_vsc_immediate")) 518 519(define_constraint "vss" 520 "@internal 521 A constraint that matches a signed immediate operand valid for SVE 522 DUP instructions." 523 (match_test "aarch64_sve_dup_immediate_p (op)")) 524 525(define_constraint "vsd" 526 "@internal 527 A constraint that matches an unsigned immediate operand valid for SVE 528 CMP instructions." 529 (match_operand 0 "aarch64_sve_cmp_vsd_immediate")) 530 531(define_constraint "vsi" 532 "@internal 533 A constraint that matches a vector count operand valid for SVE INC and 534 DEC instructions." 535 (match_operand 0 "aarch64_sve_vector_inc_dec_immediate")) 536 537(define_constraint "vsn" 538 "@internal 539 A constraint that matches an immediate operand whose negative 540 is valid for SVE SUB instructions." 541 (match_operand 0 "aarch64_sve_sub_arith_immediate")) 542 543(define_constraint "vsQ" 544 "@internal 545 Like vsa, but additionally check that the immediate is nonnegative 546 when interpreted as a signed value." 547 (match_operand 0 "aarch64_sve_qadd_immediate")) 548 549(define_constraint "vsS" 550 "@internal 551 Like vsn, but additionally check that the immediate is negative 552 when interpreted as a signed value." 553 (match_operand 0 "aarch64_sve_qsub_immediate")) 554 555(define_constraint "vsl" 556 "@internal 557 A constraint that matches an immediate operand valid for SVE logical 558 operations." 559 (match_operand 0 "aarch64_sve_logical_immediate")) 560 561(define_constraint "vsm" 562 "@internal 563 A constraint that matches an immediate operand valid for SVE MUL, 564 SMAX and SMIN operations." 565 (match_operand 0 "aarch64_sve_vsm_immediate")) 566 567(define_constraint "vsA" 568 "@internal 569 A constraint that matches an immediate operand valid for SVE FADD 570 and FSUB operations." 571 (match_operand 0 "aarch64_sve_float_arith_immediate")) 572 573;; "B" for "bound". 574(define_constraint "vsB" 575 "@internal 576 A constraint that matches an immediate operand valid for SVE FMAX 577 and FMIN operations." 578 (match_operand 0 "aarch64_sve_float_maxmin_immediate")) 579 580(define_constraint "vsM" 581 "@internal 582 A constraint that matches an immediate operand valid for SVE FMUL 583 operations." 584 (match_operand 0 "aarch64_sve_float_mul_immediate")) 585 586(define_constraint "vsN" 587 "@internal 588 A constraint that matches the negative of vsA" 589 (match_operand 0 "aarch64_sve_float_negated_arith_immediate")) 590