aarch64.h revision 1.7
1/* Machine description for AArch64 architecture. 2 Copyright (C) 2009-2017 Free Software Foundation, Inc. 3 Contributed by ARM Ltd. 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify it 8 under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 GCC is distributed in the hope that it will be useful, but 13 WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GCC; see the file COPYING3. If not see 19 <http://www.gnu.org/licenses/>. */ 20 21 22#ifndef GCC_AARCH64_H 23#define GCC_AARCH64_H 24 25/* Target CPU builtins. */ 26#define TARGET_CPU_CPP_BUILTINS() \ 27 aarch64_cpu_cpp_builtins (pfile) 28 29 30 31#define REGISTER_TARGET_PRAGMAS() aarch64_register_pragmas () 32 33/* Target machine storage layout. */ 34 35#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 36 if (GET_MODE_CLASS (MODE) == MODE_INT \ 37 && GET_MODE_SIZE (MODE) < 4) \ 38 { \ 39 if (MODE == QImode || MODE == HImode) \ 40 { \ 41 MODE = SImode; \ 42 } \ 43 } 44 45/* Bits are always numbered from the LSBit. */ 46#define BITS_BIG_ENDIAN 0 47 48/* Big/little-endian flavour. */ 49#define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) 50#define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN) 51 52/* AdvSIMD is supported in the default configuration, unless disabled by 53 -mgeneral-regs-only or by the +nosimd extension. */ 54#define TARGET_SIMD (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_SIMD) 55#define TARGET_FLOAT (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_FP) 56 57#define UNITS_PER_WORD 8 58 59#define UNITS_PER_VREG 16 60 61#define PARM_BOUNDARY 64 62 63#define STACK_BOUNDARY 128 64 65#define FUNCTION_BOUNDARY 32 66 67#define EMPTY_FIELD_BOUNDARY 32 68 69#define BIGGEST_ALIGNMENT 128 70 71#define SHORT_TYPE_SIZE 16 72 73#define INT_TYPE_SIZE 32 74 75#define LONG_TYPE_SIZE (TARGET_ILP32 ? 32 : 64) 76 77#define POINTER_SIZE (TARGET_ILP32 ? 32 : 64) 78 79#define LONG_LONG_TYPE_SIZE 64 80 81#define FLOAT_TYPE_SIZE 32 82 83#define DOUBLE_TYPE_SIZE 64 84 85#define LONG_DOUBLE_TYPE_SIZE 128 86 87/* The architecture reserves all bits of the address for hardware use, 88 so the vbit must go into the delta field of pointers to member 89 functions. This is the same config as that in the AArch32 90 port. */ 91#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta 92 93/* Make strings word-aligned so that strcpy from constants will be 94 faster. */ 95#define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 96 ((TREE_CODE (EXP) == STRING_CST \ 97 && !optimize_size \ 98 && (ALIGN) < BITS_PER_WORD) \ 99 ? BITS_PER_WORD : ALIGN) 100 101#define DATA_ALIGNMENT(EXP, ALIGN) \ 102 ((((ALIGN) < BITS_PER_WORD) \ 103 && (TREE_CODE (EXP) == ARRAY_TYPE \ 104 || TREE_CODE (EXP) == UNION_TYPE \ 105 || TREE_CODE (EXP) == RECORD_TYPE)) \ 106 ? BITS_PER_WORD : (ALIGN)) 107 108#define LOCAL_ALIGNMENT(EXP, ALIGN) DATA_ALIGNMENT(EXP, ALIGN) 109 110#define STRUCTURE_SIZE_BOUNDARY 8 111 112/* Defined by the ABI */ 113#define WCHAR_TYPE "unsigned int" 114#define WCHAR_TYPE_SIZE 32 115 116/* Using long long breaks -ansi and -std=c90, so these will need to be 117 made conditional for an LLP64 ABI. */ 118 119#define SIZE_TYPE "long unsigned int" 120 121#define PTRDIFF_TYPE "long int" 122 123#define PCC_BITFIELD_TYPE_MATTERS 1 124 125/* Major revision number of the ARM Architecture implemented by the target. */ 126extern unsigned aarch64_architecture_version; 127 128/* Instruction tuning/selection flags. */ 129 130/* Bit values used to identify processor capabilities. */ 131#define AARCH64_FL_SIMD (1 << 0) /* Has SIMD instructions. */ 132#define AARCH64_FL_FP (1 << 1) /* Has FP. */ 133#define AARCH64_FL_CRYPTO (1 << 2) /* Has crypto. */ 134#define AARCH64_FL_CRC (1 << 3) /* Has CRC. */ 135/* ARMv8.1-A architecture extensions. */ 136#define AARCH64_FL_LSE (1 << 4) /* Has Large System Extensions. */ 137#define AARCH64_FL_V8_1 (1 << 5) /* Has ARMv8.1-A extensions. */ 138/* ARMv8.2-A architecture extensions. */ 139#define AARCH64_FL_V8_2 (1 << 8) /* Has ARMv8.2-A features. */ 140#define AARCH64_FL_F16 (1 << 9) /* Has ARMv8.2-A FP16 extensions. */ 141/* ARMv8.3-A architecture extensions. */ 142#define AARCH64_FL_V8_3 (1 << 10) /* Has ARMv8.3-A features. */ 143 144/* Has FP and SIMD. */ 145#define AARCH64_FL_FPSIMD (AARCH64_FL_FP | AARCH64_FL_SIMD) 146 147/* Has FP without SIMD. */ 148#define AARCH64_FL_FPQ16 (AARCH64_FL_FP & ~AARCH64_FL_SIMD) 149 150/* Architecture flags that effect instruction selection. */ 151#define AARCH64_FL_FOR_ARCH8 (AARCH64_FL_FPSIMD) 152#define AARCH64_FL_FOR_ARCH8_1 \ 153 (AARCH64_FL_FOR_ARCH8 | AARCH64_FL_LSE | AARCH64_FL_CRC | AARCH64_FL_V8_1) 154#define AARCH64_FL_FOR_ARCH8_2 \ 155 (AARCH64_FL_FOR_ARCH8_1 | AARCH64_FL_V8_2) 156#define AARCH64_FL_FOR_ARCH8_3 \ 157 (AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_V8_3) 158 159/* Macros to test ISA flags. */ 160 161#define AARCH64_ISA_CRC (aarch64_isa_flags & AARCH64_FL_CRC) 162#define AARCH64_ISA_CRYPTO (aarch64_isa_flags & AARCH64_FL_CRYPTO) 163#define AARCH64_ISA_FP (aarch64_isa_flags & AARCH64_FL_FP) 164#define AARCH64_ISA_SIMD (aarch64_isa_flags & AARCH64_FL_SIMD) 165#define AARCH64_ISA_LSE (aarch64_isa_flags & AARCH64_FL_LSE) 166#define AARCH64_ISA_RDMA (aarch64_isa_flags & AARCH64_FL_V8_1) 167#define AARCH64_ISA_V8_2 (aarch64_isa_flags & AARCH64_FL_V8_2) 168#define AARCH64_ISA_F16 (aarch64_isa_flags & AARCH64_FL_F16) 169#define AARCH64_ISA_V8_3 (aarch64_isa_flags & AARCH64_FL_V8_3) 170 171/* Crypto is an optional extension to AdvSIMD. */ 172#define TARGET_CRYPTO (TARGET_SIMD && AARCH64_ISA_CRYPTO) 173 174/* CRC instructions that can be enabled through +crc arch extension. */ 175#define TARGET_CRC32 (AARCH64_ISA_CRC) 176 177/* Atomic instructions that can be enabled through the +lse extension. */ 178#define TARGET_LSE (AARCH64_ISA_LSE) 179 180/* ARMv8.2-A FP16 support that can be enabled through the +fp16 extension. */ 181#define TARGET_FP_F16INST (TARGET_FLOAT && AARCH64_ISA_F16) 182#define TARGET_SIMD_F16INST (TARGET_SIMD && AARCH64_ISA_F16) 183 184/* ARMv8.3-A features. */ 185#define TARGET_ARMV8_3 (AARCH64_ISA_V8_3) 186 187/* Make sure this is always defined so we don't have to check for ifdefs 188 but rather use normal ifs. */ 189#ifndef TARGET_FIX_ERR_A53_835769_DEFAULT 190#define TARGET_FIX_ERR_A53_835769_DEFAULT 0 191#else 192#undef TARGET_FIX_ERR_A53_835769_DEFAULT 193#define TARGET_FIX_ERR_A53_835769_DEFAULT 1 194#endif 195 196/* Apply the workaround for Cortex-A53 erratum 835769. */ 197#define TARGET_FIX_ERR_A53_835769 \ 198 ((aarch64_fix_a53_err835769 == 2) \ 199 ? TARGET_FIX_ERR_A53_835769_DEFAULT : aarch64_fix_a53_err835769) 200 201/* Make sure this is always defined so we don't have to check for ifdefs 202 but rather use normal ifs. */ 203#ifndef TARGET_FIX_ERR_A53_843419_DEFAULT 204#define TARGET_FIX_ERR_A53_843419_DEFAULT 0 205#else 206#undef TARGET_FIX_ERR_A53_843419_DEFAULT 207#define TARGET_FIX_ERR_A53_843419_DEFAULT 1 208#endif 209 210/* Apply the workaround for Cortex-A53 erratum 843419. */ 211#define TARGET_FIX_ERR_A53_843419 \ 212 ((aarch64_fix_a53_err843419 == 2) \ 213 ? TARGET_FIX_ERR_A53_843419_DEFAULT : aarch64_fix_a53_err843419) 214 215/* ARMv8.1-A Adv.SIMD support. */ 216#define TARGET_SIMD_RDMA (TARGET_SIMD && AARCH64_ISA_RDMA) 217 218/* Standard register usage. */ 219 220/* 31 64-bit general purpose registers R0-R30: 221 R30 LR (link register) 222 R29 FP (frame pointer) 223 R19-R28 Callee-saved registers 224 R18 The platform register; use as temporary register. 225 R17 IP1 The second intra-procedure-call temporary register 226 (can be used by call veneers and PLT code); otherwise use 227 as a temporary register 228 R16 IP0 The first intra-procedure-call temporary register (can 229 be used by call veneers and PLT code); otherwise use as a 230 temporary register 231 R9-R15 Temporary registers 232 R8 Structure value parameter / temporary register 233 R0-R7 Parameter/result registers 234 235 SP stack pointer, encoded as X/R31 where permitted. 236 ZR zero register, encoded as X/R31 elsewhere 237 238 32 x 128-bit floating-point/vector registers 239 V16-V31 Caller-saved (temporary) registers 240 V8-V15 Callee-saved registers 241 V0-V7 Parameter/result registers 242 243 The vector register V0 holds scalar B0, H0, S0 and D0 in its least 244 significant bits. Unlike AArch32 S1 is not packed into D0, 245 etc. */ 246 247/* Note that we don't mark X30 as a call-clobbered register. The idea is 248 that it's really the call instructions themselves which clobber X30. 249 We don't care what the called function does with it afterwards. 250 251 This approach makes it easier to implement sibcalls. Unlike normal 252 calls, sibcalls don't clobber X30, so the register reaches the 253 called function intact. EPILOGUE_USES says that X30 is useful 254 to the called function. */ 255 256#define FIXED_REGISTERS \ 257 { \ 258 0, 0, 0, 0, 0, 0, 0, 0, /* R0 - R7 */ \ 259 0, 0, 0, 0, 0, 0, 0, 0, /* R8 - R15 */ \ 260 0, 0, 0, 0, 0, 0, 0, 0, /* R16 - R23 */ \ 261 0, 0, 0, 0, 0, 1, 0, 1, /* R24 - R30, SP */ \ 262 0, 0, 0, 0, 0, 0, 0, 0, /* V0 - V7 */ \ 263 0, 0, 0, 0, 0, 0, 0, 0, /* V8 - V15 */ \ 264 0, 0, 0, 0, 0, 0, 0, 0, /* V16 - V23 */ \ 265 0, 0, 0, 0, 0, 0, 0, 0, /* V24 - V31 */ \ 266 1, 1, 1, /* SFP, AP, CC */ \ 267 } 268 269#define CALL_USED_REGISTERS \ 270 { \ 271 1, 1, 1, 1, 1, 1, 1, 1, /* R0 - R7 */ \ 272 1, 1, 1, 1, 1, 1, 1, 1, /* R8 - R15 */ \ 273 1, 1, 1, 0, 0, 0, 0, 0, /* R16 - R23 */ \ 274 0, 0, 0, 0, 0, 1, 1, 1, /* R24 - R30, SP */ \ 275 1, 1, 1, 1, 1, 1, 1, 1, /* V0 - V7 */ \ 276 0, 0, 0, 0, 0, 0, 0, 0, /* V8 - V15 */ \ 277 1, 1, 1, 1, 1, 1, 1, 1, /* V16 - V23 */ \ 278 1, 1, 1, 1, 1, 1, 1, 1, /* V24 - V31 */ \ 279 1, 1, 1, /* SFP, AP, CC */ \ 280 } 281 282#define REGISTER_NAMES \ 283 { \ 284 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", \ 285 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", \ 286 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", \ 287 "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", \ 288 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", \ 289 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", \ 290 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", \ 291 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", \ 292 "sfp", "ap", "cc", \ 293 } 294 295/* Generate the register aliases for core register N */ 296#define R_ALIASES(N) {"r" # N, R0_REGNUM + (N)}, \ 297 {"w" # N, R0_REGNUM + (N)} 298 299#define V_ALIASES(N) {"q" # N, V0_REGNUM + (N)}, \ 300 {"d" # N, V0_REGNUM + (N)}, \ 301 {"s" # N, V0_REGNUM + (N)}, \ 302 {"h" # N, V0_REGNUM + (N)}, \ 303 {"b" # N, V0_REGNUM + (N)} 304 305/* Provide aliases for all of the ISA defined register name forms. 306 These aliases are convenient for use in the clobber lists of inline 307 asm statements. */ 308 309#define ADDITIONAL_REGISTER_NAMES \ 310 { R_ALIASES(0), R_ALIASES(1), R_ALIASES(2), R_ALIASES(3), \ 311 R_ALIASES(4), R_ALIASES(5), R_ALIASES(6), R_ALIASES(7), \ 312 R_ALIASES(8), R_ALIASES(9), R_ALIASES(10), R_ALIASES(11), \ 313 R_ALIASES(12), R_ALIASES(13), R_ALIASES(14), R_ALIASES(15), \ 314 R_ALIASES(16), R_ALIASES(17), R_ALIASES(18), R_ALIASES(19), \ 315 R_ALIASES(20), R_ALIASES(21), R_ALIASES(22), R_ALIASES(23), \ 316 R_ALIASES(24), R_ALIASES(25), R_ALIASES(26), R_ALIASES(27), \ 317 R_ALIASES(28), R_ALIASES(29), R_ALIASES(30), {"wsp", R0_REGNUM + 31}, \ 318 V_ALIASES(0), V_ALIASES(1), V_ALIASES(2), V_ALIASES(3), \ 319 V_ALIASES(4), V_ALIASES(5), V_ALIASES(6), V_ALIASES(7), \ 320 V_ALIASES(8), V_ALIASES(9), V_ALIASES(10), V_ALIASES(11), \ 321 V_ALIASES(12), V_ALIASES(13), V_ALIASES(14), V_ALIASES(15), \ 322 V_ALIASES(16), V_ALIASES(17), V_ALIASES(18), V_ALIASES(19), \ 323 V_ALIASES(20), V_ALIASES(21), V_ALIASES(22), V_ALIASES(23), \ 324 V_ALIASES(24), V_ALIASES(25), V_ALIASES(26), V_ALIASES(27), \ 325 V_ALIASES(28), V_ALIASES(29), V_ALIASES(30), V_ALIASES(31) \ 326 } 327 328/* Say that the epilogue uses the return address register. Note that 329 in the case of sibcalls, the values "used by the epilogue" are 330 considered live at the start of the called function. */ 331 332#define EPILOGUE_USES(REGNO) \ 333 (epilogue_completed && (REGNO) == LR_REGNUM) 334 335/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 336 the stack pointer does not matter. The value is tested only in 337 functions that have frame pointers. */ 338#define EXIT_IGNORE_STACK 1 339 340#define STATIC_CHAIN_REGNUM R18_REGNUM 341#define HARD_FRAME_POINTER_REGNUM R29_REGNUM 342#define FRAME_POINTER_REGNUM SFP_REGNUM 343#define STACK_POINTER_REGNUM SP_REGNUM 344#define ARG_POINTER_REGNUM AP_REGNUM 345#define FIRST_PSEUDO_REGISTER 67 346 347/* The number of (integer) argument register available. */ 348#define NUM_ARG_REGS 8 349#define NUM_FP_ARG_REGS 8 350 351/* A Homogeneous Floating-Point or Short-Vector Aggregate may have at most 352 four members. */ 353#define HA_MAX_NUM_FLDS 4 354 355/* External dwarf register number scheme. These number are used to 356 identify registers in dwarf debug information, the values are 357 defined by the AArch64 ABI. The numbering scheme is independent of 358 GCC's internal register numbering scheme. */ 359 360#define AARCH64_DWARF_R0 0 361 362/* The number of R registers, note 31! not 32. */ 363#define AARCH64_DWARF_NUMBER_R 31 364 365#define AARCH64_DWARF_SP 31 366#define AARCH64_DWARF_V0 64 367 368/* The number of V registers. */ 369#define AARCH64_DWARF_NUMBER_V 32 370 371/* For signal frames we need to use an alternative return column. This 372 value must not correspond to a hard register and must be out of the 373 range of DWARF_FRAME_REGNUM(). */ 374#define DWARF_ALT_FRAME_RETURN_COLUMN \ 375 (AARCH64_DWARF_V0 + AARCH64_DWARF_NUMBER_V) 376 377/* We add 1 extra frame register for use as the 378 DWARF_ALT_FRAME_RETURN_COLUMN. */ 379#define DWARF_FRAME_REGISTERS (DWARF_ALT_FRAME_RETURN_COLUMN + 1) 380 381 382#define DBX_REGISTER_NUMBER(REGNO) aarch64_dbx_register_number (REGNO) 383/* Provide a definition of DWARF_FRAME_REGNUM here so that fallback unwinders 384 can use DWARF_ALT_FRAME_RETURN_COLUMN defined below. This is just the same 385 as the default definition in dwarf2out.c. */ 386#undef DWARF_FRAME_REGNUM 387#define DWARF_FRAME_REGNUM(REGNO) DBX_REGISTER_NUMBER (REGNO) 388 389#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM) 390 391#define HARD_REGNO_NREGS(REGNO, MODE) aarch64_hard_regno_nregs (REGNO, MODE) 392 393#define HARD_REGNO_MODE_OK(REGNO, MODE) aarch64_hard_regno_mode_ok (REGNO, MODE) 394 395#define MODES_TIEABLE_P(MODE1, MODE2) aarch64_modes_tieable_p (MODE1, MODE2) 396 397#define DWARF2_UNWIND_INFO 1 398 399/* Use R0 through R3 to pass exception handling information. */ 400#define EH_RETURN_DATA_REGNO(N) \ 401 ((N) < 4 ? ((unsigned int) R0_REGNUM + (N)) : INVALID_REGNUM) 402 403/* Select a format to encode pointers in exception handling data. */ 404#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 405 aarch64_asm_preferred_eh_data_format ((CODE), (GLOBAL)) 406 407/* Output the assembly strings we want to add to a function definition. */ 408#define ASM_DECLARE_FUNCTION_NAME(STR, NAME, DECL) \ 409 aarch64_declare_function_name (STR, NAME, DECL) 410 411/* For EH returns X4 contains the stack adjustment. */ 412#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, R4_REGNUM) 413#define EH_RETURN_HANDLER_RTX aarch64_eh_return_handler_rtx () 414 415/* Don't use __builtin_setjmp until we've defined it. */ 416#undef DONT_USE_BUILTIN_SETJMP 417#define DONT_USE_BUILTIN_SETJMP 1 418 419/* Register in which the structure value is to be returned. */ 420#define AARCH64_STRUCT_VALUE_REGNUM R8_REGNUM 421 422/* Non-zero if REGNO is part of the Core register set. 423 424 The rather unusual way of expressing this check is to avoid 425 warnings when building the compiler when R0_REGNUM is 0 and REGNO 426 is unsigned. */ 427#define GP_REGNUM_P(REGNO) \ 428 (((unsigned) (REGNO - R0_REGNUM)) <= (R30_REGNUM - R0_REGNUM)) 429 430#define FP_REGNUM_P(REGNO) \ 431 (((unsigned) (REGNO - V0_REGNUM)) <= (V31_REGNUM - V0_REGNUM)) 432 433#define FP_LO_REGNUM_P(REGNO) \ 434 (((unsigned) (REGNO - V0_REGNUM)) <= (V15_REGNUM - V0_REGNUM)) 435 436 437/* Register and constant classes. */ 438 439enum reg_class 440{ 441 NO_REGS, 442 TAILCALL_ADDR_REGS, 443 GENERAL_REGS, 444 STACK_REG, 445 POINTER_REGS, 446 FP_LO_REGS, 447 FP_REGS, 448 ALL_REGS, 449 LIM_REG_CLASSES /* Last */ 450}; 451 452#define N_REG_CLASSES ((int) LIM_REG_CLASSES) 453 454#define REG_CLASS_NAMES \ 455{ \ 456 "NO_REGS", \ 457 "TAILCALL_ADDR_REGS", \ 458 "GENERAL_REGS", \ 459 "STACK_REG", \ 460 "POINTER_REGS", \ 461 "FP_LO_REGS", \ 462 "FP_REGS", \ 463 "ALL_REGS" \ 464} 465 466#define REG_CLASS_CONTENTS \ 467{ \ 468 { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ 469 { 0x0004ffff, 0x00000000, 0x00000000 }, /* TAILCALL_ADDR_REGS */\ 470 { 0x7fffffff, 0x00000000, 0x00000003 }, /* GENERAL_REGS */ \ 471 { 0x80000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \ 472 { 0xffffffff, 0x00000000, 0x00000003 }, /* POINTER_REGS */ \ 473 { 0x00000000, 0x0000ffff, 0x00000000 }, /* FP_LO_REGS */ \ 474 { 0x00000000, 0xffffffff, 0x00000000 }, /* FP_REGS */ \ 475 { 0xffffffff, 0xffffffff, 0x00000007 } /* ALL_REGS */ \ 476} 477 478#define REGNO_REG_CLASS(REGNO) aarch64_regno_regclass (REGNO) 479 480#define INDEX_REG_CLASS GENERAL_REGS 481#define BASE_REG_CLASS POINTER_REGS 482 483/* Register pairs used to eliminate unneeded registers that point into 484 the stack frame. */ 485#define ELIMINABLE_REGS \ 486{ \ 487 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ 488 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ 489 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ 490 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ 491} 492 493#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 494 (OFFSET) = aarch64_initial_elimination_offset (FROM, TO) 495 496/* CPU/ARCH option handling. */ 497#include "config/aarch64/aarch64-opts.h" 498 499enum target_cpus 500{ 501#define AARCH64_CORE(NAME, INTERNAL_IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART, VARIANT) \ 502 TARGET_CPU_##INTERNAL_IDENT, 503#include "aarch64-cores.def" 504 TARGET_CPU_generic 505}; 506 507/* If there is no CPU defined at configure, use generic as default. */ 508#ifndef TARGET_CPU_DEFAULT 509#define TARGET_CPU_DEFAULT \ 510 (TARGET_CPU_generic | (AARCH64_CPU_DEFAULT_FLAGS << 6)) 511#endif 512 513/* If inserting NOP before a mult-accumulate insn remember to adjust the 514 length so that conditional branching code is updated appropriately. */ 515#define ADJUST_INSN_LENGTH(insn, length) \ 516 do \ 517 { \ 518 if (aarch64_madd_needs_nop (insn)) \ 519 length += 4; \ 520 } while (0) 521 522#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 523 aarch64_final_prescan_insn (INSN); \ 524 525/* The processor for which instructions should be scheduled. */ 526extern enum aarch64_processor aarch64_tune; 527 528/* RTL generation support. */ 529#define INIT_EXPANDERS aarch64_init_expanders () 530 531 532/* Stack layout; function entry, exit and calling. */ 533#define STACK_GROWS_DOWNWARD 1 534 535#define FRAME_GROWS_DOWNWARD 1 536 537#define STARTING_FRAME_OFFSET 0 538 539#define ACCUMULATE_OUTGOING_ARGS 1 540 541#define FIRST_PARM_OFFSET(FNDECL) 0 542 543/* Fix for VFP */ 544#define LIBCALL_VALUE(MODE) \ 545 gen_rtx_REG (MODE, FLOAT_MODE_P (MODE) ? V0_REGNUM : R0_REGNUM) 546 547#define DEFAULT_PCC_STRUCT_RETURN 0 548 549#ifdef HOST_WIDE_INT 550struct GTY (()) aarch64_frame 551{ 552 HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER]; 553 554 /* The number of extra stack bytes taken up by register varargs. 555 This area is allocated by the callee at the very top of the 556 frame. This value is rounded up to a multiple of 557 STACK_BOUNDARY. */ 558 HOST_WIDE_INT saved_varargs_size; 559 560 /* The size of the saved callee-save int/FP registers. */ 561 562 HOST_WIDE_INT saved_regs_size; 563 564 /* Offset from the base of the frame (incomming SP) to the 565 top of the locals area. This value is always a multiple of 566 STACK_BOUNDARY. */ 567 HOST_WIDE_INT locals_offset; 568 569 /* Offset from the base of the frame (incomming SP) to the 570 hard_frame_pointer. This value is always a multiple of 571 STACK_BOUNDARY. */ 572 HOST_WIDE_INT hard_fp_offset; 573 574 /* The size of the frame. This value is the offset from base of the 575 * frame (incomming SP) to the stack_pointer. This value is always 576 * a multiple of STACK_BOUNDARY. */ 577 HOST_WIDE_INT frame_size; 578 579 /* The size of the initial stack adjustment before saving callee-saves. */ 580 HOST_WIDE_INT initial_adjust; 581 582 /* The writeback value when pushing callee-save registers. 583 It is zero when no push is used. */ 584 HOST_WIDE_INT callee_adjust; 585 586 /* The offset from SP to the callee-save registers after initial_adjust. 587 It may be non-zero if no push is used (ie. callee_adjust == 0). */ 588 HOST_WIDE_INT callee_offset; 589 590 /* The size of the stack adjustment after saving callee-saves. */ 591 HOST_WIDE_INT final_adjust; 592 593 unsigned wb_candidate1; 594 unsigned wb_candidate2; 595 596 bool laid_out; 597}; 598 599typedef struct GTY (()) machine_function 600{ 601 struct aarch64_frame frame; 602 /* One entry for each hard register. */ 603 bool reg_is_wrapped_separately[LAST_SAVED_REGNUM]; 604} machine_function; 605#endif 606 607/* Which ABI to use. */ 608enum aarch64_abi_type 609{ 610 AARCH64_ABI_LP64 = 0, 611 AARCH64_ABI_ILP32 = 1 612}; 613 614#ifndef AARCH64_ABI_DEFAULT 615#define AARCH64_ABI_DEFAULT AARCH64_ABI_LP64 616#endif 617 618#define TARGET_ILP32 (aarch64_abi & AARCH64_ABI_ILP32) 619 620enum arm_pcs 621{ 622 ARM_PCS_AAPCS64, /* Base standard AAPCS for 64 bit. */ 623 ARM_PCS_UNKNOWN 624}; 625 626 627 628 629/* We can't use machine_mode inside a generator file because it 630 hasn't been created yet; we shouldn't be using any code that 631 needs the real definition though, so this ought to be safe. */ 632#ifdef GENERATOR_FILE 633#define MACHMODE int 634#else 635#include "insn-modes.h" 636#define MACHMODE machine_mode 637#endif 638 639#ifndef USED_FOR_TARGET 640/* AAPCS related state tracking. */ 641typedef struct 642{ 643 enum arm_pcs pcs_variant; 644 int aapcs_arg_processed; /* No need to lay out this argument again. */ 645 int aapcs_ncrn; /* Next Core register number. */ 646 int aapcs_nextncrn; /* Next next core register number. */ 647 int aapcs_nvrn; /* Next Vector register number. */ 648 int aapcs_nextnvrn; /* Next Next Vector register number. */ 649 rtx aapcs_reg; /* Register assigned to this argument. This 650 is NULL_RTX if this parameter goes on 651 the stack. */ 652 MACHMODE aapcs_vfp_rmode; 653 int aapcs_stack_words; /* If the argument is passed on the stack, this 654 is the number of words needed, after rounding 655 up. Only meaningful when 656 aapcs_reg == NULL_RTX. */ 657 int aapcs_stack_size; /* The total size (in words, per 8 byte) of the 658 stack arg area so far. */ 659} CUMULATIVE_ARGS; 660#endif 661 662#define FUNCTION_ARG_PADDING(MODE, TYPE) \ 663 (aarch64_pad_arg_upward (MODE, TYPE) ? upward : downward) 664 665#define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ 666 (aarch64_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward) 667 668#define PAD_VARARGS_DOWN 0 669 670#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 671 aarch64_init_cumulative_args (&(CUM), FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) 672 673#define FUNCTION_ARG_REGNO_P(REGNO) \ 674 aarch64_function_arg_regno_p(REGNO) 675 676 677/* ISA Features. */ 678 679/* Addressing modes, etc. */ 680#define HAVE_POST_INCREMENT 1 681#define HAVE_PRE_INCREMENT 1 682#define HAVE_POST_DECREMENT 1 683#define HAVE_PRE_DECREMENT 1 684#define HAVE_POST_MODIFY_DISP 1 685#define HAVE_PRE_MODIFY_DISP 1 686 687#define MAX_REGS_PER_ADDRESS 2 688 689#define CONSTANT_ADDRESS_P(X) aarch64_constant_address_p(X) 690 691#define REGNO_OK_FOR_BASE_P(REGNO) \ 692 aarch64_regno_ok_for_base_p (REGNO, true) 693 694#define REGNO_OK_FOR_INDEX_P(REGNO) \ 695 aarch64_regno_ok_for_index_p (REGNO, true) 696 697#define LEGITIMATE_PIC_OPERAND_P(X) \ 698 aarch64_legitimate_pic_operand_p (X) 699 700#define CASE_VECTOR_MODE Pmode 701 702#define DEFAULT_SIGNED_CHAR 0 703 704/* An integer expression for the size in bits of the largest integer machine 705 mode that should actually be used. We allow pairs of registers. */ 706#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode) 707 708/* Maximum bytes moved by a single instruction (load/store pair). */ 709#define MOVE_MAX (UNITS_PER_WORD * 2) 710 711/* The base cost overhead of a memcpy call, for MOVE_RATIO and friends. */ 712#define AARCH64_CALL_RATIO 8 713 714/* MOVE_RATIO dictates when we will use the move_by_pieces infrastructure. 715 move_by_pieces will continually copy the largest safe chunks. So a 716 7-byte copy is a 4-byte + 2-byte + byte copy. This proves inefficient 717 for both size and speed of copy, so we will instead use the "movmem" 718 standard name to implement the copy. This logic does not apply when 719 targeting -mstrict-align, so keep a sensible default in that case. */ 720#define MOVE_RATIO(speed) \ 721 (!STRICT_ALIGNMENT ? 2 : (((speed) ? 15 : AARCH64_CALL_RATIO) / 2)) 722 723/* For CLEAR_RATIO, when optimizing for size, give a better estimate 724 of the length of a memset call, but use the default otherwise. */ 725#define CLEAR_RATIO(speed) \ 726 ((speed) ? 15 : AARCH64_CALL_RATIO) 727 728/* SET_RATIO is similar to CLEAR_RATIO, but for a non-zero constant, so when 729 optimizing for size adjust the ratio to account for the overhead of loading 730 the constant. */ 731#define SET_RATIO(speed) \ 732 ((speed) ? 15 : AARCH64_CALL_RATIO - 2) 733 734/* Disable auto-increment in move_by_pieces et al. Use of auto-increment is 735 rarely a good idea in straight-line code since it adds an extra address 736 dependency between each instruction. Better to use incrementing offsets. */ 737#define USE_LOAD_POST_INCREMENT(MODE) 0 738#define USE_LOAD_POST_DECREMENT(MODE) 0 739#define USE_LOAD_PRE_INCREMENT(MODE) 0 740#define USE_LOAD_PRE_DECREMENT(MODE) 0 741#define USE_STORE_POST_INCREMENT(MODE) 0 742#define USE_STORE_POST_DECREMENT(MODE) 0 743#define USE_STORE_PRE_INCREMENT(MODE) 0 744#define USE_STORE_PRE_DECREMENT(MODE) 0 745 746/* WORD_REGISTER_OPERATIONS does not hold for AArch64. 747 The assigned word_mode is DImode but operations narrower than SImode 748 behave as 32-bit operations if using the W-form of the registers rather 749 than as word_mode (64-bit) operations as WORD_REGISTER_OPERATIONS 750 expects. */ 751#define WORD_REGISTER_OPERATIONS 0 752 753/* Define if loading from memory in MODE, an integral mode narrower than 754 BITS_PER_WORD will either zero-extend or sign-extend. The value of this 755 macro should be the code that says which one of the two operations is 756 implicitly done, or UNKNOWN if none. */ 757#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 758 759/* Define this macro to be non-zero if instructions will fail to work 760 if given data not on the nominal alignment. */ 761#define STRICT_ALIGNMENT TARGET_STRICT_ALIGN 762 763/* Define this macro to be non-zero if accessing less than a word of 764 memory is no faster than accessing a word of memory, i.e., if such 765 accesses require more than one instruction or if there is no 766 difference in cost. 767 Although there's no difference in instruction count or cycles, 768 in AArch64 we don't want to expand to a sub-word to a 64-bit access 769 if we don't have to, for power-saving reasons. */ 770#define SLOW_BYTE_ACCESS 0 771 772#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 773 774#define NO_FUNCTION_CSE 1 775 776/* Specify the machine mode that the hardware addresses have. 777 After generation of rtl, the compiler makes no further distinction 778 between pointers and any other objects of this machine mode. */ 779#define Pmode DImode 780 781/* A C expression whose value is zero if pointers that need to be extended 782 from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and 783 greater then zero if they are zero-extended and less then zero if the 784 ptr_extend instruction should be used. */ 785#define POINTERS_EXTEND_UNSIGNED 1 786 787/* Mode of a function address in a call instruction (for indexing purposes). */ 788#define FUNCTION_MODE Pmode 789 790#define SELECT_CC_MODE(OP, X, Y) aarch64_select_cc_mode (OP, X, Y) 791 792#define REVERSIBLE_CC_MODE(MODE) 1 793 794#define REVERSE_CONDITION(CODE, MODE) \ 795 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \ 796 ? reverse_condition_maybe_unordered (CODE) \ 797 : reverse_condition (CODE)) 798 799#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 800 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) 801#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 802 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) 803 804#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM) 805 806#define RETURN_ADDR_RTX aarch64_return_addr 807 808/* 3 insns + padding + 2 pointer-sized entries. */ 809#define TRAMPOLINE_SIZE (TARGET_ILP32 ? 24 : 32) 810 811/* Trampolines contain dwords, so must be dword aligned. */ 812#define TRAMPOLINE_ALIGNMENT 64 813 814/* Put trampolines in the text section so that mapping symbols work 815 correctly. */ 816#define TRAMPOLINE_SECTION text_section 817 818/* To start with. */ 819#define BRANCH_COST(SPEED_P, PREDICTABLE_P) \ 820 (aarch64_branch_cost (SPEED_P, PREDICTABLE_P)) 821 822 823/* Assembly output. */ 824 825/* For now we'll make all jump tables pc-relative. */ 826#define CASE_VECTOR_PC_RELATIVE 1 827 828#define CASE_VECTOR_SHORTEN_MODE(min, max, body) \ 829 ((min < -0x1fff0 || max > 0x1fff0) ? SImode \ 830 : (min < -0x1f0 || max > 0x1f0) ? HImode \ 831 : QImode) 832 833/* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */ 834#define ADDR_VEC_ALIGN(JUMPTABLE) 0 835 836#define MCOUNT_NAME "_mcount" 837 838#define NO_PROFILE_COUNTERS 1 839 840/* Emit rtl for profiling. Output assembler code to FILE 841 to call "_mcount" for profiling a function entry. */ 842#define PROFILE_HOOK(LABEL) \ 843 { \ 844 rtx fun, lr; \ 845 lr = get_hard_reg_initial_val (Pmode, LR_REGNUM); \ 846 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_NAME); \ 847 emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lr, Pmode); \ 848 } 849 850/* All the work done in PROFILE_HOOK, but still required. */ 851#define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0) 852 853/* For some reason, the Linux headers think they know how to define 854 these macros. They don't!!! */ 855#undef ASM_APP_ON 856#undef ASM_APP_OFF 857#define ASM_APP_ON "\t" ASM_COMMENT_START " Start of user assembly\n" 858#define ASM_APP_OFF "\t" ASM_COMMENT_START " End of user assembly\n" 859 860#define CONSTANT_POOL_BEFORE_FUNCTION 0 861 862/* This definition should be relocated to aarch64-elf-raw.h. This macro 863 should be undefined in aarch64-linux.h and a clear_cache pattern 864 implmented to emit either the call to __aarch64_sync_cache_range() 865 directly or preferably the appropriate sycall or cache clear 866 instructions inline. */ 867#define CLEAR_INSN_CACHE(beg, end) \ 868 extern void __aarch64_sync_cache_range (void *, void *); \ 869 __aarch64_sync_cache_range (beg, end) 870 871#define SHIFT_COUNT_TRUNCATED (!TARGET_SIMD) 872 873/* Choose appropriate mode for caller saves, so we do the minimum 874 required size of load/store. */ 875#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 876 aarch64_hard_regno_caller_save_mode ((REGNO), (NREGS), (MODE)) 877 878/* Callee only saves lower 64-bits of a 128-bit register. Tell the 879 compiler the callee clobbers the top 64-bits when restoring the 880 bottom 64-bits. */ 881#define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \ 882 (FP_REGNUM_P (REGNO) && GET_MODE_SIZE (MODE) > 8) 883 884#undef SWITCHABLE_TARGET 885#define SWITCHABLE_TARGET 1 886 887/* Check TLS Descriptors mechanism is selected. */ 888#define TARGET_TLS_DESC (aarch64_tls_dialect == TLS_DESCRIPTORS) 889 890extern enum aarch64_code_model aarch64_cmodel; 891 892/* When using the tiny addressing model conditional and unconditional branches 893 can span the whole of the available address space (1MB). */ 894#define HAS_LONG_COND_BRANCH \ 895 (aarch64_cmodel == AARCH64_CMODEL_TINY \ 896 || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC) 897 898#define HAS_LONG_UNCOND_BRANCH \ 899 (aarch64_cmodel == AARCH64_CMODEL_TINY \ 900 || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC) 901 902#define TARGET_SUPPORTS_WIDE_INT 1 903 904/* Modes valid for AdvSIMD D registers, i.e. that fit in half a Q register. */ 905#define AARCH64_VALID_SIMD_DREG_MODE(MODE) \ 906 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \ 907 || (MODE) == V2SFmode || (MODE) == V4HFmode || (MODE) == DImode \ 908 || (MODE) == DFmode) 909 910/* Modes valid for AdvSIMD Q registers. */ 911#define AARCH64_VALID_SIMD_QREG_MODE(MODE) \ 912 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \ 913 || (MODE) == V4SFmode || (MODE) == V8HFmode || (MODE) == V2DImode \ 914 || (MODE) == V2DFmode) 915 916#define ENDIAN_LANE_N(mode, n) \ 917 (BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 - n : n) 918 919/* Support for a configure-time default CPU, etc. We currently support 920 --with-arch and --with-cpu. Both are ignored if either is specified 921 explicitly on the command line at run time. */ 922#define OPTION_DEFAULT_SPECS \ 923 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \ 924 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, 925 926#define MCPU_TO_MARCH_SPEC \ 927 " %{mcpu=*:-march=%:rewrite_mcpu(%{mcpu=*:%*})}" 928 929extern const char *aarch64_rewrite_mcpu (int argc, const char **argv); 930#define MCPU_TO_MARCH_SPEC_FUNCTIONS \ 931 { "rewrite_mcpu", aarch64_rewrite_mcpu }, 932 933#if defined(__aarch64__) 934extern const char *host_detect_local_cpu (int argc, const char **argv); 935# define EXTRA_SPEC_FUNCTIONS \ 936 { "local_cpu_detect", host_detect_local_cpu }, \ 937 MCPU_TO_MARCH_SPEC_FUNCTIONS 938 939# define MCPU_MTUNE_NATIVE_SPECS \ 940 " %{march=native:%<march=native %:local_cpu_detect(arch)}" \ 941 " %{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)}" \ 942 " %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" 943#else 944# define MCPU_MTUNE_NATIVE_SPECS "" 945# define EXTRA_SPEC_FUNCTIONS MCPU_TO_MARCH_SPEC_FUNCTIONS 946#endif 947 948#define ASM_CPU_SPEC \ 949 MCPU_TO_MARCH_SPEC 950 951#define EXTRA_SPECS \ 952 { "asm_cpu_spec", ASM_CPU_SPEC } 953 954#define ASM_OUTPUT_POOL_EPILOGUE aarch64_asm_output_pool_epilogue 955 956/* This type is the user-visible __fp16, and a pointer to that type. We 957 need it in many places in the backend. Defined in aarch64-builtins.c. */ 958extern tree aarch64_fp16_type_node; 959extern tree aarch64_fp16_ptr_type_node; 960 961/* The generic unwind code in libgcc does not initialize the frame pointer. 962 So in order to unwind a function using a frame pointer, the very first 963 function that is unwound must save the frame pointer. That way the frame 964 pointer is restored and its value is now valid - otherwise _Unwind_GetGR 965 crashes. Libgcc can now be safely built with -fomit-frame-pointer. */ 966#define LIBGCC2_UNWIND_ATTRIBUTE \ 967 __attribute__((optimize ("no-omit-frame-pointer"))) 968 969#endif /* GCC_AARCH64_H */ 970