1/* Machine description for AArch64 architecture. 2 Copyright (C) 2012-2020 Free Software Foundation, Inc. 3 Contributed by ARM Ltd. 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify it 8 under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 GCC is distributed in the hope that it will be useful, but 13 WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GCC; see the file COPYING3. If not see 19 <http://www.gnu.org/licenses/>. */ 20 21/* In the list below, the BUILTIN_<ITERATOR> macros expand to create 22 builtins for each of the modes described by <ITERATOR>. When adding 23 new builtins to this list, a helpful idiom to follow is to add 24 a line for each pattern in the md file. Thus, ADDP, which has one 25 pattern defined for the VD_BHSI iterator, and one for DImode, has two 26 entries below. 27 28 Parameter 1 is the 'type' of the intrinsic. This is used to 29 describe the type modifiers (for example; unsigned) applied to 30 each of the parameters to the intrinsic function. 31 32 Parameter 2 is the name of the intrinsic. This is appended 33 to `__builtin_aarch64_<name><mode>` to give the intrinsic name 34 as exported to the front-ends. 35 36 Parameter 3 describes how to map from the name to the CODE_FOR_ 37 macro holding the RTL pattern for the intrinsic. This mapping is: 38 0 - CODE_FOR_aarch64_<name><mode> 39 1-9 - CODE_FOR_<name><mode><1-9> 40 10 - CODE_FOR_<name><mode>. */ 41 42 BUILTIN_VDC (COMBINE, combine, 0) 43 VAR1 (COMBINEP, combine, 0, di) 44 BUILTIN_VB (BINOP, pmul, 0) 45 BUILTIN_VHSDF_HSDF (BINOP, fmulx, 0) 46 BUILTIN_VHSDF_DF (UNOP, sqrt, 2) 47 BUILTIN_VD_BHSI (BINOP, addp, 0) 48 VAR1 (UNOP, addp, 0, di) 49 BUILTIN_VDQ_BHSI (UNOP, clrsb, 2) 50 BUILTIN_VDQ_BHSI (UNOP, clz, 2) 51 BUILTIN_VS (UNOP, ctz, 2) 52 BUILTIN_VB (UNOP, popcount, 2) 53 54 /* Implemented by aarch64_<sur>q<r>shl<mode>. */ 55 BUILTIN_VSDQ_I (BINOP, sqshl, 0) 56 BUILTIN_VSDQ_I (BINOP_UUS, uqshl, 0) 57 BUILTIN_VSDQ_I (BINOP, sqrshl, 0) 58 BUILTIN_VSDQ_I (BINOP_UUS, uqrshl, 0) 59 /* Implemented by aarch64_<su_optab><optab><mode>. */ 60 BUILTIN_VSDQ_I (BINOP, sqadd, 0) 61 BUILTIN_VSDQ_I (BINOPU, uqadd, 0) 62 BUILTIN_VSDQ_I (BINOP, sqsub, 0) 63 BUILTIN_VSDQ_I (BINOPU, uqsub, 0) 64 /* Implemented by aarch64_<sur>qadd<mode>. */ 65 BUILTIN_VSDQ_I (BINOP_SSU, suqadd, 0) 66 BUILTIN_VSDQ_I (BINOP_UUS, usqadd, 0) 67 68 /* Implemented by aarch64_get_dreg<VSTRUCT:mode><VDC:mode>. */ 69 BUILTIN_VDC (GETREG, get_dregoi, 0) 70 BUILTIN_VDC (GETREG, get_dregci, 0) 71 BUILTIN_VDC (GETREG, get_dregxi, 0) 72 VAR1 (GETREGP, get_dregoi, 0, di) 73 VAR1 (GETREGP, get_dregci, 0, di) 74 VAR1 (GETREGP, get_dregxi, 0, di) 75 /* Implemented by aarch64_get_qreg<VSTRUCT:mode><VQ:mode>. */ 76 BUILTIN_VQ (GETREG, get_qregoi, 0) 77 BUILTIN_VQ (GETREG, get_qregci, 0) 78 BUILTIN_VQ (GETREG, get_qregxi, 0) 79 VAR1 (GETREGP, get_qregoi, 0, v2di) 80 VAR1 (GETREGP, get_qregci, 0, v2di) 81 VAR1 (GETREGP, get_qregxi, 0, v2di) 82 /* Implemented by aarch64_set_qreg<VSTRUCT:mode><VQ:mode>. */ 83 BUILTIN_VQ (SETREG, set_qregoi, 0) 84 BUILTIN_VQ (SETREG, set_qregci, 0) 85 BUILTIN_VQ (SETREG, set_qregxi, 0) 86 VAR1 (SETREGP, set_qregoi, 0, v2di) 87 VAR1 (SETREGP, set_qregci, 0, v2di) 88 VAR1 (SETREGP, set_qregxi, 0, v2di) 89 /* Implemented by aarch64_ld1x2<VQ:mode>. */ 90 BUILTIN_VQ (LOADSTRUCT, ld1x2, 0) 91 /* Implemented by aarch64_ld1x2<VDC:mode>. */ 92 BUILTIN_VDC (LOADSTRUCT, ld1x2, 0) 93 /* Implemented by aarch64_ld<VSTRUCT:nregs><VDC:mode>. */ 94 BUILTIN_VDC (LOADSTRUCT, ld2, 0) 95 BUILTIN_VDC (LOADSTRUCT, ld3, 0) 96 BUILTIN_VDC (LOADSTRUCT, ld4, 0) 97 /* Implemented by aarch64_ld<VSTRUCT:nregs><VQ:mode>. */ 98 BUILTIN_VQ (LOADSTRUCT, ld2, 0) 99 BUILTIN_VQ (LOADSTRUCT, ld3, 0) 100 BUILTIN_VQ (LOADSTRUCT, ld4, 0) 101 /* Implemented by aarch64_ld<VSTRUCT:nregs>r<VALLDIF:mode>. */ 102 BUILTIN_VALLDIF (LOADSTRUCT, ld2r, 0) 103 BUILTIN_VALLDIF (LOADSTRUCT, ld3r, 0) 104 BUILTIN_VALLDIF (LOADSTRUCT, ld4r, 0) 105 /* Implemented by aarch64_ld<VSTRUCT:nregs>_lane<VQ:mode>. */ 106 BUILTIN_VALLDIF (LOADSTRUCT_LANE, ld2_lane, 0) 107 BUILTIN_VALLDIF (LOADSTRUCT_LANE, ld3_lane, 0) 108 BUILTIN_VALLDIF (LOADSTRUCT_LANE, ld4_lane, 0) 109 /* Implemented by aarch64_st<VSTRUCT:nregs><VDC:mode>. */ 110 BUILTIN_VDC (STORESTRUCT, st2, 0) 111 BUILTIN_VDC (STORESTRUCT, st3, 0) 112 BUILTIN_VDC (STORESTRUCT, st4, 0) 113 /* Implemented by aarch64_st<VSTRUCT:nregs><VQ:mode>. */ 114 BUILTIN_VQ (STORESTRUCT, st2, 0) 115 BUILTIN_VQ (STORESTRUCT, st3, 0) 116 BUILTIN_VQ (STORESTRUCT, st4, 0) 117 118 BUILTIN_VALLDIF (STORESTRUCT_LANE, st2_lane, 0) 119 BUILTIN_VALLDIF (STORESTRUCT_LANE, st3_lane, 0) 120 BUILTIN_VALLDIF (STORESTRUCT_LANE, st4_lane, 0) 121 122 BUILTIN_VQW (BINOP, saddl2, 0) 123 BUILTIN_VQW (BINOP, uaddl2, 0) 124 BUILTIN_VQW (BINOP, ssubl2, 0) 125 BUILTIN_VQW (BINOP, usubl2, 0) 126 BUILTIN_VQW (BINOP, saddw2, 0) 127 BUILTIN_VQW (BINOP, uaddw2, 0) 128 BUILTIN_VQW (BINOP, ssubw2, 0) 129 BUILTIN_VQW (BINOP, usubw2, 0) 130 /* Implemented by aarch64_<ANY_EXTEND:su><ADDSUB:optab>l<mode>. */ 131 BUILTIN_VD_BHSI (BINOP, saddl, 0) 132 BUILTIN_VD_BHSI (BINOP, uaddl, 0) 133 BUILTIN_VD_BHSI (BINOP, ssubl, 0) 134 BUILTIN_VD_BHSI (BINOP, usubl, 0) 135 /* Implemented by aarch64_<ANY_EXTEND:su><ADDSUB:optab>w<mode>. */ 136 BUILTIN_VD_BHSI (BINOP, saddw, 0) 137 BUILTIN_VD_BHSI (BINOP, uaddw, 0) 138 BUILTIN_VD_BHSI (BINOP, ssubw, 0) 139 BUILTIN_VD_BHSI (BINOP, usubw, 0) 140 /* Implemented by aarch64_<sur>h<addsub><mode>. */ 141 BUILTIN_VDQ_BHSI (BINOP, shadd, 0) 142 BUILTIN_VDQ_BHSI (BINOP, shsub, 0) 143 BUILTIN_VDQ_BHSI (BINOP, uhadd, 0) 144 BUILTIN_VDQ_BHSI (BINOP, uhsub, 0) 145 BUILTIN_VDQ_BHSI (BINOP, srhadd, 0) 146 BUILTIN_VDQ_BHSI (BINOP, urhadd, 0) 147 /* Implemented by aarch64_<sur><addsub>hn<mode>. */ 148 BUILTIN_VQN (BINOP, addhn, 0) 149 BUILTIN_VQN (BINOP, subhn, 0) 150 BUILTIN_VQN (BINOP, raddhn, 0) 151 BUILTIN_VQN (BINOP, rsubhn, 0) 152 /* Implemented by aarch64_<sur><addsub>hn2<mode>. */ 153 BUILTIN_VQN (TERNOP, addhn2, 0) 154 BUILTIN_VQN (TERNOP, subhn2, 0) 155 BUILTIN_VQN (TERNOP, raddhn2, 0) 156 BUILTIN_VQN (TERNOP, rsubhn2, 0) 157 158 BUILTIN_VSQN_HSDI (UNOPUS, sqmovun, 0) 159 /* Implemented by aarch64_<sur>qmovn<mode>. */ 160 BUILTIN_VSQN_HSDI (UNOP, sqmovn, 0) 161 BUILTIN_VSQN_HSDI (UNOP, uqmovn, 0) 162 /* Implemented by aarch64_s<optab><mode>. */ 163 BUILTIN_VSDQ_I (UNOP, sqabs, 0) 164 BUILTIN_VSDQ_I (UNOP, sqneg, 0) 165 166 /* Implemented by aarch64_sqdml<SBINQOPS:as>l<mode>. */ 167 BUILTIN_VSD_HSI (TERNOP, sqdmlal, 0) 168 BUILTIN_VSD_HSI (TERNOP, sqdmlsl, 0) 169 /* Implemented by aarch64_sqdml<SBINQOPS:as>l_lane<mode>. */ 170 BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlal_lane, 0) 171 BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlsl_lane, 0) 172 /* Implemented by aarch64_sqdml<SBINQOPS:as>l_laneq<mode>. */ 173 BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlal_laneq, 0) 174 BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlsl_laneq, 0) 175 /* Implemented by aarch64_sqdml<SBINQOPS:as>l_n<mode>. */ 176 BUILTIN_VD_HSI (TERNOP, sqdmlal_n, 0) 177 BUILTIN_VD_HSI (TERNOP, sqdmlsl_n, 0) 178 179 BUILTIN_VQ_HSI (TERNOP, sqdmlal2, 0) 180 BUILTIN_VQ_HSI (TERNOP, sqdmlsl2, 0) 181 BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlal2_lane, 0) 182 BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlsl2_lane, 0) 183 BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlal2_laneq, 0) 184 BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlsl2_laneq, 0) 185 BUILTIN_VQ_HSI (TERNOP, sqdmlal2_n, 0) 186 BUILTIN_VQ_HSI (TERNOP, sqdmlsl2_n, 0) 187 188 BUILTIN_VD_BHSI (BINOP, intrinsic_vec_smult_lo_, 0) 189 BUILTIN_VD_BHSI (BINOPU, intrinsic_vec_umult_lo_, 0) 190 191 BUILTIN_VQW (BINOP, vec_widen_smult_hi_, 10) 192 BUILTIN_VQW (BINOPU, vec_widen_umult_hi_, 10) 193 194 BUILTIN_VD_HSI (TERNOP_LANE, vec_smult_lane_, 0) 195 BUILTIN_VD_HSI (QUADOP_LANE, vec_smlal_lane_, 0) 196 BUILTIN_VD_HSI (TERNOP_LANE, vec_smult_laneq_, 0) 197 BUILTIN_VD_HSI (QUADOP_LANE, vec_smlal_laneq_, 0) 198 BUILTIN_VD_HSI (TERNOPU_LANE, vec_umult_lane_, 0) 199 BUILTIN_VD_HSI (QUADOPU_LANE, vec_umlal_lane_, 0) 200 BUILTIN_VD_HSI (TERNOPU_LANE, vec_umult_laneq_, 0) 201 BUILTIN_VD_HSI (QUADOPU_LANE, vec_umlal_laneq_, 0) 202 203 BUILTIN_VSD_HSI (BINOP, sqdmull, 0) 204 BUILTIN_VSD_HSI (TERNOP_LANE, sqdmull_lane, 0) 205 BUILTIN_VSD_HSI (TERNOP_LANE, sqdmull_laneq, 0) 206 BUILTIN_VD_HSI (BINOP, sqdmull_n, 0) 207 BUILTIN_VQ_HSI (BINOP, sqdmull2, 0) 208 BUILTIN_VQ_HSI (TERNOP_LANE, sqdmull2_lane, 0) 209 BUILTIN_VQ_HSI (TERNOP_LANE, sqdmull2_laneq, 0) 210 BUILTIN_VQ_HSI (BINOP, sqdmull2_n, 0) 211 /* Implemented by aarch64_sq<r>dmulh<mode>. */ 212 BUILTIN_VSDQ_HSI (BINOP, sqdmulh, 0) 213 BUILTIN_VSDQ_HSI (BINOP, sqrdmulh, 0) 214 /* Implemented by aarch64_sq<r>dmulh_lane<q><mode>. */ 215 BUILTIN_VSDQ_HSI (TERNOP_LANE, sqdmulh_lane, 0) 216 BUILTIN_VSDQ_HSI (TERNOP_LANE, sqdmulh_laneq, 0) 217 BUILTIN_VSDQ_HSI (TERNOP_LANE, sqrdmulh_lane, 0) 218 BUILTIN_VSDQ_HSI (TERNOP_LANE, sqrdmulh_laneq, 0) 219 220 BUILTIN_VSDQ_I_DI (BINOP, ashl, 3) 221 /* Implemented by aarch64_<sur>shl<mode>. */ 222 BUILTIN_VSDQ_I_DI (BINOP, sshl, 0) 223 BUILTIN_VSDQ_I_DI (BINOP_UUS, ushl, 0) 224 BUILTIN_VSDQ_I_DI (BINOP, srshl, 0) 225 BUILTIN_VSDQ_I_DI (BINOP_UUS, urshl, 0) 226 227 /* Implemented by aarch64_<sur><dotprod>{_lane}{q}<dot_mode>. */ 228 BUILTIN_VB (TERNOP, sdot, 0) 229 BUILTIN_VB (TERNOPU, udot, 0) 230 BUILTIN_VB (TERNOP_SSUS, usdot, 0) 231 BUILTIN_VB (QUADOP_LANE, sdot_lane, 0) 232 BUILTIN_VB (QUADOPU_LANE, udot_lane, 0) 233 BUILTIN_VB (QUADOP_LANE, sdot_laneq, 0) 234 BUILTIN_VB (QUADOPU_LANE, udot_laneq, 0) 235 BUILTIN_VB (QUADOPSSUS_LANE_QUADTUP, usdot_lane, 0) 236 BUILTIN_VB (QUADOPSSUS_LANE_QUADTUP, usdot_laneq, 0) 237 BUILTIN_VB (QUADOPSSSU_LANE_QUADTUP, sudot_lane, 0) 238 BUILTIN_VB (QUADOPSSSU_LANE_QUADTUP, sudot_laneq, 0) 239 240 /* Implemented by aarch64_fcadd<rot><mode>. */ 241 BUILTIN_VHSDF (BINOP, fcadd90, 0) 242 BUILTIN_VHSDF (BINOP, fcadd270, 0) 243 244 /* Implemented by aarch64_fcmla{_lane}{q}<rot><mode>. */ 245 BUILTIN_VHSDF (TERNOP, fcmla0, 0) 246 BUILTIN_VHSDF (TERNOP, fcmla90, 0) 247 BUILTIN_VHSDF (TERNOP, fcmla180, 0) 248 BUILTIN_VHSDF (TERNOP, fcmla270, 0) 249 BUILTIN_VHSDF (QUADOP_LANE_PAIR, fcmla_lane0, 0) 250 BUILTIN_VHSDF (QUADOP_LANE_PAIR, fcmla_lane90, 0) 251 BUILTIN_VHSDF (QUADOP_LANE_PAIR, fcmla_lane180, 0) 252 BUILTIN_VHSDF (QUADOP_LANE_PAIR, fcmla_lane270, 0) 253 254 BUILTIN_VQ_HSF (QUADOP_LANE_PAIR, fcmlaq_lane0, 0) 255 BUILTIN_VQ_HSF (QUADOP_LANE_PAIR, fcmlaq_lane90, 0) 256 BUILTIN_VQ_HSF (QUADOP_LANE_PAIR, fcmlaq_lane180, 0) 257 BUILTIN_VQ_HSF (QUADOP_LANE_PAIR, fcmlaq_lane270, 0) 258 259 BUILTIN_VDQ_I (SHIFTIMM, ashr, 3) 260 VAR1 (SHIFTIMM, ashr_simd, 0, di) 261 BUILTIN_VDQ_I (SHIFTIMM, lshr, 3) 262 VAR1 (USHIFTIMM, lshr_simd, 0, di) 263 /* Implemented by aarch64_<sur>shr_n<mode>. */ 264 BUILTIN_VSDQ_I_DI (SHIFTIMM, srshr_n, 0) 265 BUILTIN_VSDQ_I_DI (USHIFTIMM, urshr_n, 0) 266 /* Implemented by aarch64_<sur>sra_n<mode>. */ 267 BUILTIN_VSDQ_I_DI (SHIFTACC, ssra_n, 0) 268 BUILTIN_VSDQ_I_DI (USHIFTACC, usra_n, 0) 269 BUILTIN_VSDQ_I_DI (SHIFTACC, srsra_n, 0) 270 BUILTIN_VSDQ_I_DI (USHIFTACC, ursra_n, 0) 271 /* Implemented by aarch64_<sur>shll_n<mode>. */ 272 BUILTIN_VD_BHSI (SHIFTIMM, sshll_n, 0) 273 BUILTIN_VD_BHSI (USHIFTIMM, ushll_n, 0) 274 /* Implemented by aarch64_<sur>shll2_n<mode>. */ 275 BUILTIN_VQW (SHIFTIMM, sshll2_n, 0) 276 BUILTIN_VQW (SHIFTIMM, ushll2_n, 0) 277 /* Implemented by aarch64_<sur>q<r>shr<u>n_n<mode>. */ 278 BUILTIN_VSQN_HSDI (SHIFTIMM, sqshrun_n, 0) 279 BUILTIN_VSQN_HSDI (SHIFTIMM, sqrshrun_n, 0) 280 BUILTIN_VSQN_HSDI (SHIFTIMM, sqshrn_n, 0) 281 BUILTIN_VSQN_HSDI (USHIFTIMM, uqshrn_n, 0) 282 BUILTIN_VSQN_HSDI (SHIFTIMM, sqrshrn_n, 0) 283 BUILTIN_VSQN_HSDI (USHIFTIMM, uqrshrn_n, 0) 284 /* Implemented by aarch64_<sur>s<lr>i_n<mode>. */ 285 BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssri_n, 0) 286 BUILTIN_VSDQ_I_DI (USHIFTACC, usri_n, 0) 287 BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssli_n, 0) 288 VAR2 (SHIFTINSERTP, ssli_n, 0, di, v2di) 289 BUILTIN_VSDQ_I_DI (USHIFTACC, usli_n, 0) 290 /* Implemented by aarch64_<sur>qshl<u>_n<mode>. */ 291 BUILTIN_VSDQ_I (SHIFTIMM_USS, sqshlu_n, 0) 292 BUILTIN_VSDQ_I (SHIFTIMM, sqshl_n, 0) 293 BUILTIN_VSDQ_I (USHIFTIMM, uqshl_n, 0) 294 295 /* Implemented by aarch64_reduc_plus_<mode>. */ 296 BUILTIN_VALL (UNOP, reduc_plus_scal_, 10) 297 298 /* Implemented by reduc_<maxmin_uns>_scal_<mode> (producing scalar). */ 299 BUILTIN_VDQIF_F16 (UNOP, reduc_smax_scal_, 10) 300 BUILTIN_VDQIF_F16 (UNOP, reduc_smin_scal_, 10) 301 BUILTIN_VDQ_BHSI (UNOPU, reduc_umax_scal_, 10) 302 BUILTIN_VDQ_BHSI (UNOPU, reduc_umin_scal_, 10) 303 BUILTIN_VHSDF (UNOP, reduc_smax_nan_scal_, 10) 304 BUILTIN_VHSDF (UNOP, reduc_smin_nan_scal_, 10) 305 306 /* Implemented by <maxmin_uns><mode>3. 307 smax variants map to fmaxnm, 308 smax_nan variants map to fmax. */ 309 BUILTIN_VDQ_BHSI (BINOP, smax, 3) 310 BUILTIN_VDQ_BHSI (BINOP, smin, 3) 311 BUILTIN_VDQ_BHSI (BINOP, umax, 3) 312 BUILTIN_VDQ_BHSI (BINOP, umin, 3) 313 BUILTIN_VHSDF_DF (BINOP, smax_nan, 3) 314 BUILTIN_VHSDF_DF (BINOP, smin_nan, 3) 315 316 /* Implemented by <maxmin_uns><mode>3. */ 317 BUILTIN_VHSDF_HSDF (BINOP, fmax, 3) 318 BUILTIN_VHSDF_HSDF (BINOP, fmin, 3) 319 320 /* Implemented by aarch64_<maxmin_uns>p<mode>. */ 321 BUILTIN_VDQ_BHSI (BINOP, smaxp, 0) 322 BUILTIN_VDQ_BHSI (BINOP, sminp, 0) 323 BUILTIN_VDQ_BHSI (BINOP, umaxp, 0) 324 BUILTIN_VDQ_BHSI (BINOP, uminp, 0) 325 BUILTIN_VHSDF (BINOP, smaxp, 0) 326 BUILTIN_VHSDF (BINOP, sminp, 0) 327 BUILTIN_VHSDF (BINOP, smax_nanp, 0) 328 BUILTIN_VHSDF (BINOP, smin_nanp, 0) 329 330 /* Implemented by <frint_pattern><mode>2. */ 331 BUILTIN_VHSDF (UNOP, btrunc, 2) 332 BUILTIN_VHSDF (UNOP, ceil, 2) 333 BUILTIN_VHSDF (UNOP, floor, 2) 334 BUILTIN_VHSDF (UNOP, nearbyint, 2) 335 BUILTIN_VHSDF (UNOP, rint, 2) 336 BUILTIN_VHSDF (UNOP, round, 2) 337 BUILTIN_VHSDF_HSDF (UNOP, frintn, 2) 338 339 VAR1 (UNOP, btrunc, 2, hf) 340 VAR1 (UNOP, ceil, 2, hf) 341 VAR1 (UNOP, floor, 2, hf) 342 VAR1 (UNOP, nearbyint, 2, hf) 343 VAR1 (UNOP, rint, 2, hf) 344 VAR1 (UNOP, round, 2, hf) 345 346 /* Implemented by l<fcvt_pattern><su_optab><VQDF:mode><vcvt_target>2. */ 347 VAR1 (UNOP, lbtruncv4hf, 2, v4hi) 348 VAR1 (UNOP, lbtruncv8hf, 2, v8hi) 349 VAR1 (UNOP, lbtruncv2sf, 2, v2si) 350 VAR1 (UNOP, lbtruncv4sf, 2, v4si) 351 VAR1 (UNOP, lbtruncv2df, 2, v2di) 352 353 VAR1 (UNOPUS, lbtruncuv4hf, 2, v4hi) 354 VAR1 (UNOPUS, lbtruncuv8hf, 2, v8hi) 355 VAR1 (UNOPUS, lbtruncuv2sf, 2, v2si) 356 VAR1 (UNOPUS, lbtruncuv4sf, 2, v4si) 357 VAR1 (UNOPUS, lbtruncuv2df, 2, v2di) 358 359 VAR1 (UNOP, lroundv4hf, 2, v4hi) 360 VAR1 (UNOP, lroundv8hf, 2, v8hi) 361 VAR1 (UNOP, lroundv2sf, 2, v2si) 362 VAR1 (UNOP, lroundv4sf, 2, v4si) 363 VAR1 (UNOP, lroundv2df, 2, v2di) 364 /* Implemented by l<fcvt_pattern><su_optab><GPF_F16:mode><GPI:mode>2. */ 365 BUILTIN_GPI_I16 (UNOP, lroundhf, 2) 366 VAR1 (UNOP, lroundsf, 2, si) 367 VAR1 (UNOP, lrounddf, 2, di) 368 369 VAR1 (UNOPUS, lrounduv4hf, 2, v4hi) 370 VAR1 (UNOPUS, lrounduv8hf, 2, v8hi) 371 VAR1 (UNOPUS, lrounduv2sf, 2, v2si) 372 VAR1 (UNOPUS, lrounduv4sf, 2, v4si) 373 VAR1 (UNOPUS, lrounduv2df, 2, v2di) 374 BUILTIN_GPI_I16 (UNOPUS, lrounduhf, 2) 375 VAR1 (UNOPUS, lroundusf, 2, si) 376 VAR1 (UNOPUS, lroundudf, 2, di) 377 378 VAR1 (UNOP, lceilv4hf, 2, v4hi) 379 VAR1 (UNOP, lceilv8hf, 2, v8hi) 380 VAR1 (UNOP, lceilv2sf, 2, v2si) 381 VAR1 (UNOP, lceilv4sf, 2, v4si) 382 VAR1 (UNOP, lceilv2df, 2, v2di) 383 BUILTIN_GPI_I16 (UNOP, lceilhf, 2) 384 385 VAR1 (UNOPUS, lceiluv4hf, 2, v4hi) 386 VAR1 (UNOPUS, lceiluv8hf, 2, v8hi) 387 VAR1 (UNOPUS, lceiluv2sf, 2, v2si) 388 VAR1 (UNOPUS, lceiluv4sf, 2, v4si) 389 VAR1 (UNOPUS, lceiluv2df, 2, v2di) 390 BUILTIN_GPI_I16 (UNOPUS, lceiluhf, 2) 391 VAR1 (UNOPUS, lceilusf, 2, si) 392 VAR1 (UNOPUS, lceiludf, 2, di) 393 394 VAR1 (UNOP, lfloorv4hf, 2, v4hi) 395 VAR1 (UNOP, lfloorv8hf, 2, v8hi) 396 VAR1 (UNOP, lfloorv2sf, 2, v2si) 397 VAR1 (UNOP, lfloorv4sf, 2, v4si) 398 VAR1 (UNOP, lfloorv2df, 2, v2di) 399 BUILTIN_GPI_I16 (UNOP, lfloorhf, 2) 400 401 VAR1 (UNOPUS, lflooruv4hf, 2, v4hi) 402 VAR1 (UNOPUS, lflooruv8hf, 2, v8hi) 403 VAR1 (UNOPUS, lflooruv2sf, 2, v2si) 404 VAR1 (UNOPUS, lflooruv4sf, 2, v4si) 405 VAR1 (UNOPUS, lflooruv2df, 2, v2di) 406 BUILTIN_GPI_I16 (UNOPUS, lflooruhf, 2) 407 VAR1 (UNOPUS, lfloorusf, 2, si) 408 VAR1 (UNOPUS, lfloorudf, 2, di) 409 410 VAR1 (UNOP, lfrintnv4hf, 2, v4hi) 411 VAR1 (UNOP, lfrintnv8hf, 2, v8hi) 412 VAR1 (UNOP, lfrintnv2sf, 2, v2si) 413 VAR1 (UNOP, lfrintnv4sf, 2, v4si) 414 VAR1 (UNOP, lfrintnv2df, 2, v2di) 415 BUILTIN_GPI_I16 (UNOP, lfrintnhf, 2) 416 VAR1 (UNOP, lfrintnsf, 2, si) 417 VAR1 (UNOP, lfrintndf, 2, di) 418 419 VAR1 (UNOPUS, lfrintnuv4hf, 2, v4hi) 420 VAR1 (UNOPUS, lfrintnuv8hf, 2, v8hi) 421 VAR1 (UNOPUS, lfrintnuv2sf, 2, v2si) 422 VAR1 (UNOPUS, lfrintnuv4sf, 2, v4si) 423 VAR1 (UNOPUS, lfrintnuv2df, 2, v2di) 424 BUILTIN_GPI_I16 (UNOPUS, lfrintnuhf, 2) 425 VAR1 (UNOPUS, lfrintnusf, 2, si) 426 VAR1 (UNOPUS, lfrintnudf, 2, di) 427 428 /* Implemented by <optab><fcvt_target><VDQF:mode>2. */ 429 VAR1 (UNOP, floatv4hi, 2, v4hf) 430 VAR1 (UNOP, floatv8hi, 2, v8hf) 431 VAR1 (UNOP, floatv2si, 2, v2sf) 432 VAR1 (UNOP, floatv4si, 2, v4sf) 433 VAR1 (UNOP, floatv2di, 2, v2df) 434 435 VAR1 (UNOP, floatunsv4hi, 2, v4hf) 436 VAR1 (UNOP, floatunsv8hi, 2, v8hf) 437 VAR1 (UNOP, floatunsv2si, 2, v2sf) 438 VAR1 (UNOP, floatunsv4si, 2, v4sf) 439 VAR1 (UNOP, floatunsv2di, 2, v2df) 440 441 VAR5 (UNOPU, bswap, 2, v4hi, v8hi, v2si, v4si, v2di) 442 443 BUILTIN_VB (UNOP, rbit, 0) 444 445 /* Implemented by 446 aarch64_<PERMUTE:perm_insn><mode>. */ 447 BUILTIN_VALL (BINOP, zip1, 0) 448 BUILTIN_VALL (BINOP, zip2, 0) 449 BUILTIN_VALL (BINOP, uzp1, 0) 450 BUILTIN_VALL (BINOP, uzp2, 0) 451 BUILTIN_VALL (BINOP, trn1, 0) 452 BUILTIN_VALL (BINOP, trn2, 0) 453 454 BUILTIN_GPF_F16 (UNOP, frecpe, 0) 455 BUILTIN_GPF_F16 (UNOP, frecpx, 0) 456 457 BUILTIN_VDQ_SI (UNOP, urecpe, 0) 458 459 BUILTIN_VHSDF (UNOP, frecpe, 0) 460 BUILTIN_VHSDF_HSDF (BINOP, frecps, 0) 461 462 /* Implemented by a mixture of abs2 patterns. Note the DImode builtin is 463 only ever used for the int64x1_t intrinsic, there is no scalar version. */ 464 BUILTIN_VSDQ_I_DI (UNOP, abs, 0) 465 BUILTIN_VHSDF (UNOP, abs, 2) 466 VAR1 (UNOP, abs, 2, hf) 467 468 BUILTIN_VQ_HSF (UNOP, vec_unpacks_hi_, 10) 469 VAR1 (BINOP, float_truncate_hi_, 0, v4sf) 470 VAR1 (BINOP, float_truncate_hi_, 0, v8hf) 471 472 VAR1 (UNOP, float_extend_lo_, 0, v2df) 473 VAR1 (UNOP, float_extend_lo_, 0, v4sf) 474 BUILTIN_VDF (UNOP, float_truncate_lo_, 0) 475 476 /* Implemented by aarch64_ld1<VALL_F16:mode>. */ 477 BUILTIN_VALL_F16 (LOAD1, ld1, 0) 478 VAR1(STORE1P, ld1, 0, v2di) 479 480 /* Implemented by aarch64_st1<VALL_F16:mode>. */ 481 BUILTIN_VALL_F16 (STORE1, st1, 0) 482 VAR1(STORE1P, st1, 0, v2di) 483 484 /* Implemented by aarch64_ld1x3<VALLDIF:mode>. */ 485 BUILTIN_VALLDIF (LOADSTRUCT, ld1x3, 0) 486 487 /* Implemented by aarch64_ld1x4<VALLDIF:mode>. */ 488 BUILTIN_VALLDIF (LOADSTRUCT, ld1x4, 0) 489 490 /* Implemented by aarch64_st1x2<VALLDIF:mode>. */ 491 BUILTIN_VALLDIF (STORESTRUCT, st1x2, 0) 492 493 /* Implemented by aarch64_st1x3<VALLDIF:mode>. */ 494 BUILTIN_VALLDIF (STORESTRUCT, st1x3, 0) 495 496 /* Implemented by aarch64_st1x4<VALLDIF:mode>. */ 497 BUILTIN_VALLDIF (STORESTRUCT, st1x4, 0) 498 499 /* Implemented by fma<mode>4. */ 500 BUILTIN_VHSDF (TERNOP, fma, 4) 501 VAR1 (TERNOP, fma, 4, hf) 502 /* Implemented by fnma<mode>4. */ 503 BUILTIN_VHSDF (TERNOP, fnma, 4) 504 VAR1 (TERNOP, fnma, 4, hf) 505 506 /* Implemented by aarch64_simd_bsl<mode>. */ 507 BUILTIN_VDQQH (BSL_P, simd_bsl, 0) 508 VAR2 (BSL_P, simd_bsl,0, di, v2di) 509 BUILTIN_VSDQ_I_DI (BSL_U, simd_bsl, 0) 510 BUILTIN_VALLDIF (BSL_S, simd_bsl, 0) 511 512 /* Implemented by aarch64_crypto_aes<op><mode>. */ 513 VAR1 (BINOPU, crypto_aese, 0, v16qi) 514 VAR1 (BINOPU, crypto_aesd, 0, v16qi) 515 VAR1 (UNOPU, crypto_aesmc, 0, v16qi) 516 VAR1 (UNOPU, crypto_aesimc, 0, v16qi) 517 518 /* Implemented by aarch64_crypto_sha1<op><mode>. */ 519 VAR1 (UNOPU, crypto_sha1h, 0, si) 520 VAR1 (BINOPU, crypto_sha1su1, 0, v4si) 521 VAR1 (TERNOPU, crypto_sha1c, 0, v4si) 522 VAR1 (TERNOPU, crypto_sha1m, 0, v4si) 523 VAR1 (TERNOPU, crypto_sha1p, 0, v4si) 524 VAR1 (TERNOPU, crypto_sha1su0, 0, v4si) 525 526 /* Implemented by aarch64_crypto_sha256<op><mode>. */ 527 VAR1 (TERNOPU, crypto_sha256h, 0, v4si) 528 VAR1 (TERNOPU, crypto_sha256h2, 0, v4si) 529 VAR1 (BINOPU, crypto_sha256su0, 0, v4si) 530 VAR1 (TERNOPU, crypto_sha256su1, 0, v4si) 531 532 /* Implemented by aarch64_crypto_pmull<mode>. */ 533 VAR1 (BINOPP, crypto_pmull, 0, di) 534 VAR1 (BINOPP, crypto_pmull, 0, v2di) 535 536 /* Implemented by aarch64_tbl3<mode>. */ 537 VAR1 (BINOP, tbl3, 0, v8qi) 538 VAR1 (BINOP, tbl3, 0, v16qi) 539 540 /* Implemented by aarch64_qtbl3<mode>. */ 541 VAR1 (BINOP, qtbl3, 0, v8qi) 542 VAR1 (BINOP, qtbl3, 0, v16qi) 543 544 /* Implemented by aarch64_qtbl4<mode>. */ 545 VAR1 (BINOP, qtbl4, 0, v8qi) 546 VAR1 (BINOP, qtbl4, 0, v16qi) 547 548 /* Implemented by aarch64_tbx4<mode>. */ 549 VAR1 (TERNOP, tbx4, 0, v8qi) 550 VAR1 (TERNOP, tbx4, 0, v16qi) 551 552 /* Implemented by aarch64_qtbx3<mode>. */ 553 VAR1 (TERNOP, qtbx3, 0, v8qi) 554 VAR1 (TERNOP, qtbx3, 0, v16qi) 555 556 /* Implemented by aarch64_qtbx4<mode>. */ 557 VAR1 (TERNOP, qtbx4, 0, v8qi) 558 VAR1 (TERNOP, qtbx4, 0, v16qi) 559 560 /* Builtins for ARMv8.1-A Adv.SIMD instructions. */ 561 562 /* Implemented by aarch64_sqrdml<SQRDMLH_AS:rdma_as>h<mode>. */ 563 BUILTIN_VSDQ_HSI (TERNOP, sqrdmlah, 0) 564 BUILTIN_VSDQ_HSI (TERNOP, sqrdmlsh, 0) 565 566 /* Implemented by aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_lane<mode>. */ 567 BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlah_lane, 0) 568 BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlsh_lane, 0) 569 570 /* Implemented by aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode>. */ 571 BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlah_laneq, 0) 572 BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlsh_laneq, 0) 573 574 /* Implemented by <FCVT_F2FIXED/FIXED2F:fcvt_fixed_insn><*><*>3. */ 575 BUILTIN_VSDQ_HSDI (SHIFTIMM, scvtf, 3) 576 BUILTIN_VSDQ_HSDI (FCVTIMM_SUS, ucvtf, 3) 577 BUILTIN_VHSDF_HSDF (SHIFTIMM, fcvtzs, 3) 578 BUILTIN_VHSDF_HSDF (SHIFTIMM_USS, fcvtzu, 3) 579 VAR1 (SHIFTIMM, scvtfsi, 3, hf) 580 VAR1 (SHIFTIMM, scvtfdi, 3, hf) 581 VAR1 (FCVTIMM_SUS, ucvtfsi, 3, hf) 582 VAR1 (FCVTIMM_SUS, ucvtfdi, 3, hf) 583 BUILTIN_GPI (SHIFTIMM, fcvtzshf, 3) 584 BUILTIN_GPI (SHIFTIMM_USS, fcvtzuhf, 3) 585 586 /* Implemented by aarch64_rsqrte<mode>. */ 587 BUILTIN_VHSDF_HSDF (UNOP, rsqrte, 0) 588 589 /* Implemented by aarch64_rsqrts<mode>. */ 590 BUILTIN_VHSDF_HSDF (BINOP, rsqrts, 0) 591 592 /* Implemented by fabd<mode>3. */ 593 BUILTIN_VHSDF_HSDF (BINOP, fabd, 3) 594 595 /* Implemented by aarch64_faddp<mode>. */ 596 BUILTIN_VHSDF (BINOP, faddp, 0) 597 598 /* Implemented by aarch64_cm<optab><mode>. */ 599 BUILTIN_VHSDF_HSDF (BINOP_USS, cmeq, 0) 600 BUILTIN_VHSDF_HSDF (BINOP_USS, cmge, 0) 601 BUILTIN_VHSDF_HSDF (BINOP_USS, cmgt, 0) 602 BUILTIN_VHSDF_HSDF (BINOP_USS, cmle, 0) 603 BUILTIN_VHSDF_HSDF (BINOP_USS, cmlt, 0) 604 605 /* Implemented by neg<mode>2. */ 606 BUILTIN_VHSDF_HSDF (UNOP, neg, 2) 607 608 /* Implemented by aarch64_fac<optab><mode>. */ 609 BUILTIN_VHSDF_HSDF (BINOP_USS, faclt, 0) 610 BUILTIN_VHSDF_HSDF (BINOP_USS, facle, 0) 611 BUILTIN_VHSDF_HSDF (BINOP_USS, facgt, 0) 612 BUILTIN_VHSDF_HSDF (BINOP_USS, facge, 0) 613 614 /* Implemented by sqrt<mode>2. */ 615 VAR1 (UNOP, sqrt, 2, hf) 616 617 /* Implemented by <optab><mode>hf2. */ 618 VAR1 (UNOP, floatdi, 2, hf) 619 VAR1 (UNOP, floatsi, 2, hf) 620 VAR1 (UNOP, floathi, 2, hf) 621 VAR1 (UNOPUS, floatunsdi, 2, hf) 622 VAR1 (UNOPUS, floatunssi, 2, hf) 623 VAR1 (UNOPUS, floatunshi, 2, hf) 624 BUILTIN_GPI_I16 (UNOP, fix_trunchf, 2) 625 BUILTIN_GPI (UNOP, fix_truncsf, 2) 626 BUILTIN_GPI (UNOP, fix_truncdf, 2) 627 BUILTIN_GPI_I16 (UNOPUS, fixuns_trunchf, 2) 628 BUILTIN_GPI (UNOPUS, fixuns_truncsf, 2) 629 BUILTIN_GPI (UNOPUS, fixuns_truncdf, 2) 630 631 /* Implemented by aarch64_sm3ss1qv4si. */ 632 VAR1 (TERNOPU, sm3ss1q, 0, v4si) 633 /* Implemented by aarch64_sm3tt<sm3tt_op>qv4si. */ 634 VAR1 (QUADOPUI, sm3tt1aq, 0, v4si) 635 VAR1 (QUADOPUI, sm3tt1bq, 0, v4si) 636 VAR1 (QUADOPUI, sm3tt2aq, 0, v4si) 637 VAR1 (QUADOPUI, sm3tt2bq, 0, v4si) 638 /* Implemented by aarch64_sm3partw<sm3part_op>qv4si. */ 639 VAR1 (TERNOPU, sm3partw1q, 0, v4si) 640 VAR1 (TERNOPU, sm3partw2q, 0, v4si) 641 /* Implemented by aarch64_sm4eqv4si. */ 642 VAR1 (BINOPU, sm4eq, 0, v4si) 643 /* Implemented by aarch64_sm4ekeyqv4si. */ 644 VAR1 (BINOPU, sm4ekeyq, 0, v4si) 645 /* Implemented by aarch64_crypto_sha512hqv2di. */ 646 VAR1 (TERNOPU, crypto_sha512hq, 0, v2di) 647 /* Implemented by aarch64_sha512h2qv2di. */ 648 VAR1 (TERNOPU, crypto_sha512h2q, 0, v2di) 649 /* Implemented by aarch64_crypto_sha512su0qv2di. */ 650 VAR1 (BINOPU, crypto_sha512su0q, 0, v2di) 651 /* Implemented by aarch64_crypto_sha512su1qv2di. */ 652 VAR1 (TERNOPU, crypto_sha512su1q, 0, v2di) 653 /* Implemented by eor3q<mode>4. */ 654 BUILTIN_VQ_I (TERNOPU, eor3q, 4) 655 BUILTIN_VQ_I (TERNOP, eor3q, 4) 656 /* Implemented by aarch64_rax1qv2di. */ 657 VAR1 (BINOPU, rax1q, 0, v2di) 658 /* Implemented by aarch64_xarqv2di. */ 659 VAR1 (TERNOPUI, xarq, 0, v2di) 660 /* Implemented by bcaxq<mode>4. */ 661 BUILTIN_VQ_I (TERNOPU, bcaxq, 4) 662 BUILTIN_VQ_I (TERNOP, bcaxq, 4) 663 664 /* Implemented by aarch64_fml<f16mac1>l<f16quad>_low<mode>. */ 665 VAR1 (TERNOP, fmlal_low, 0, v2sf) 666 VAR1 (TERNOP, fmlsl_low, 0, v2sf) 667 VAR1 (TERNOP, fmlalq_low, 0, v4sf) 668 VAR1 (TERNOP, fmlslq_low, 0, v4sf) 669 /* Implemented by aarch64_fml<f16mac1>l<f16quad>_high<mode>. */ 670 VAR1 (TERNOP, fmlal_high, 0, v2sf) 671 VAR1 (TERNOP, fmlsl_high, 0, v2sf) 672 VAR1 (TERNOP, fmlalq_high, 0, v4sf) 673 VAR1 (TERNOP, fmlslq_high, 0, v4sf) 674 /* Implemented by aarch64_fml<f16mac1>l_lane_lowv2sf. */ 675 VAR1 (QUADOP_LANE, fmlal_lane_low, 0, v2sf) 676 VAR1 (QUADOP_LANE, fmlsl_lane_low, 0, v2sf) 677 /* Implemented by aarch64_fml<f16mac1>l_laneq_lowv2sf. */ 678 VAR1 (QUADOP_LANE, fmlal_laneq_low, 0, v2sf) 679 VAR1 (QUADOP_LANE, fmlsl_laneq_low, 0, v2sf) 680 /* Implemented by aarch64_fml<f16mac1>lq_lane_lowv4sf. */ 681 VAR1 (QUADOP_LANE, fmlalq_lane_low, 0, v4sf) 682 VAR1 (QUADOP_LANE, fmlslq_lane_low, 0, v4sf) 683 /* Implemented by aarch64_fml<f16mac1>lq_laneq_lowv4sf. */ 684 VAR1 (QUADOP_LANE, fmlalq_laneq_low, 0, v4sf) 685 VAR1 (QUADOP_LANE, fmlslq_laneq_low, 0, v4sf) 686 /* Implemented by aarch64_fml<f16mac1>l_lane_highv2sf. */ 687 VAR1 (QUADOP_LANE, fmlal_lane_high, 0, v2sf) 688 VAR1 (QUADOP_LANE, fmlsl_lane_high, 0, v2sf) 689 /* Implemented by aarch64_fml<f16mac1>l_laneq_highv2sf. */ 690 VAR1 (QUADOP_LANE, fmlal_laneq_high, 0, v2sf) 691 VAR1 (QUADOP_LANE, fmlsl_laneq_high, 0, v2sf) 692 /* Implemented by aarch64_fml<f16mac1>lq_lane_highv4sf. */ 693 VAR1 (QUADOP_LANE, fmlalq_lane_high, 0, v4sf) 694 VAR1 (QUADOP_LANE, fmlslq_lane_high, 0, v4sf) 695 /* Implemented by aarch64_fml<f16mac1>lq_laneq_highv4sf. */ 696 VAR1 (QUADOP_LANE, fmlalq_laneq_high, 0, v4sf) 697 VAR1 (QUADOP_LANE, fmlslq_laneq_high, 0, v4sf) 698 699 /* Implemented by aarch64_<frintnzs_op><mode>. */ 700 BUILTIN_VSFDF (UNOP, frint32z, 0) 701 BUILTIN_VSFDF (UNOP, frint32x, 0) 702 BUILTIN_VSFDF (UNOP, frint64z, 0) 703 BUILTIN_VSFDF (UNOP, frint64x, 0) 704 705 /* Implemented by aarch64_bfdot{_lane}{q}<mode>. */ 706 VAR2 (TERNOP, bfdot, 0, v2sf, v4sf) 707 VAR2 (QUADOP_LANE_PAIR, bfdot_lane, 0, v2sf, v4sf) 708 VAR2 (QUADOP_LANE_PAIR, bfdot_laneq, 0, v2sf, v4sf) 709 710 /* Implemented by aarch64_bfmmlaqv4sf */ 711 VAR1 (TERNOP, bfmmlaq, 0, v4sf) 712 713 /* Implemented by aarch64_bfmlal<bt>{_lane{q}}v4sf */ 714 VAR1 (TERNOP, bfmlalb, 0, v4sf) 715 VAR1 (TERNOP, bfmlalt, 0, v4sf) 716 VAR1 (QUADOP_LANE, bfmlalb_lane, 0, v4sf) 717 VAR1 (QUADOP_LANE, bfmlalt_lane, 0, v4sf) 718 VAR1 (QUADOP_LANE, bfmlalb_lane_q, 0, v4sf) 719 VAR1 (QUADOP_LANE, bfmlalt_lane_q, 0, v4sf) 720 721 /* Implemented by aarch64_vget_lo/hi_halfv8bf. */ 722 VAR1 (UNOP, vget_lo_half, 0, v8bf) 723 VAR1 (UNOP, vget_hi_half, 0, v8bf) 724 725 /* Implemented by aarch64_simd_<sur>mmlav16qi. */ 726 VAR1 (TERNOP, simd_smmla, 0, v16qi) 727 VAR1 (TERNOPU, simd_ummla, 0, v16qi) 728 VAR1 (TERNOP_SSUS, simd_usmmla, 0, v16qi) 729 730 /* Implemented by aarch64_bfcvtn{q}{2}<mode> */ 731 VAR1 (UNOP, bfcvtn, 0, v4bf) 732 VAR1 (UNOP, bfcvtn_q, 0, v8bf) 733 VAR1 (BINOP, bfcvtn2, 0, v8bf) 734 VAR1 (UNOP, bfcvt, 0, bf) 735 736 /* Implemented by aarch64_{v}bfcvt{_high}<mode>. */ 737 VAR2 (UNOP, vbfcvt, 0, v4bf, v8bf) 738 VAR1 (UNOP, vbfcvt_high, 0, v8bf) 739 VAR1 (UNOP, bfcvt, 0, sf) 740