1/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */ 2/* Instruction opcode table for m32r. 3 4THIS FILE IS MACHINE GENERATED WITH CGEN. 5 6Copyright (C) 1996-2022 Free Software Foundation, Inc. 7 8This file is part of the GNU Binutils and/or GDB, the GNU debugger. 9 10 This file is free software; you can redistribute it and/or modify 11 it under the terms of the GNU General Public License as published by 12 the Free Software Foundation; either version 3, or (at your option) 13 any later version. 14 15 It is distributed in the hope that it will be useful, but WITHOUT 16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 18 License for more details. 19 20 You should have received a copy of the GNU General Public License along 21 with this program; if not, write to the Free Software Foundation, Inc., 22 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. 23 24*/ 25 26#include "sysdep.h" 27#include "ansidecl.h" 28#include "bfd.h" 29#include "symcat.h" 30#include "m32r-desc.h" 31#include "m32r-opc.h" 32#include "libiberty.h" 33 34/* -- opc.c */ 35unsigned int 36m32r_cgen_dis_hash (const char * buf ATTRIBUTE_UNUSED, CGEN_INSN_INT value) 37{ 38 unsigned int x; 39 40 if (value & 0xffff0000) /* 32bit instructions. */ 41 value = (value >> 16) & 0xffff; 42 43 x = (value >> 8) & 0xf0; 44 if (x == 0x40 || x == 0xe0 || x == 0x60 || x == 0x50) 45 return x; 46 47 if (x == 0x70 || x == 0xf0) 48 return x | ((value >> 8) & 0x0f); 49 50 if (x == 0x30) 51 return x | ((value & 0x70) >> 4); 52 else 53 return x | ((value & 0xf0) >> 4); 54} 55 56/* -- */ 57/* The hash functions are recorded here to help keep assembler code out of 58 the disassembler and vice versa. */ 59 60static int asm_hash_insn_p (const CGEN_INSN *); 61static unsigned int asm_hash_insn (const char *); 62static int dis_hash_insn_p (const CGEN_INSN *); 63static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT); 64 65/* Instruction formats. */ 66 67#define F(f) & m32r_cgen_ifld_table[M32R_##f] 68static const CGEN_IFMT ifmt_empty ATTRIBUTE_UNUSED = { 69 0, 0, 0x0, { { 0 } } 70}; 71 72static const CGEN_IFMT ifmt_add ATTRIBUTE_UNUSED = { 73 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } } 74}; 75 76static const CGEN_IFMT ifmt_add3 ATTRIBUTE_UNUSED = { 77 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } 78}; 79 80static const CGEN_IFMT ifmt_and3 ATTRIBUTE_UNUSED = { 81 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } } 82}; 83 84static const CGEN_IFMT ifmt_or3 ATTRIBUTE_UNUSED = { 85 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } } 86}; 87 88static const CGEN_IFMT ifmt_addi ATTRIBUTE_UNUSED = { 89 16, 16, 0xf000, { { F (F_OP1) }, { F (F_R1) }, { F (F_SIMM8) }, { 0 } } 90}; 91 92static const CGEN_IFMT ifmt_addv3 ATTRIBUTE_UNUSED = { 93 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } 94}; 95 96static const CGEN_IFMT ifmt_bc8 ATTRIBUTE_UNUSED = { 97 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } } 98}; 99 100static const CGEN_IFMT ifmt_bc24 ATTRIBUTE_UNUSED = { 101 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } } 102}; 103 104static const CGEN_IFMT ifmt_beq ATTRIBUTE_UNUSED = { 105 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_DISP16) }, { 0 } } 106}; 107 108static const CGEN_IFMT ifmt_beqz ATTRIBUTE_UNUSED = { 109 32, 32, 0xfff00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_DISP16) }, { 0 } } 110}; 111 112static const CGEN_IFMT ifmt_cmp ATTRIBUTE_UNUSED = { 113 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } } 114}; 115 116static const CGEN_IFMT ifmt_cmpi ATTRIBUTE_UNUSED = { 117 32, 32, 0xfff00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } 118}; 119 120static const CGEN_IFMT ifmt_cmpz ATTRIBUTE_UNUSED = { 121 16, 16, 0xfff0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } } 122}; 123 124static const CGEN_IFMT ifmt_div ATTRIBUTE_UNUSED = { 125 32, 32, 0xf0f0ffff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } 126}; 127 128static const CGEN_IFMT ifmt_jc ATTRIBUTE_UNUSED = { 129 16, 16, 0xfff0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } } 130}; 131 132static const CGEN_IFMT ifmt_ld24 ATTRIBUTE_UNUSED = { 133 32, 32, 0xf0000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_UIMM24) }, { 0 } } 134}; 135 136static const CGEN_IFMT ifmt_ldi16 ATTRIBUTE_UNUSED = { 137 32, 32, 0xf0ff0000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } 138}; 139 140static const CGEN_IFMT ifmt_machi_a ATTRIBUTE_UNUSED = { 141 16, 16, 0xf070, { { F (F_OP1) }, { F (F_R1) }, { F (F_ACC) }, { F (F_OP23) }, { F (F_R2) }, { 0 } } 142}; 143 144static const CGEN_IFMT ifmt_mvfachi ATTRIBUTE_UNUSED = { 145 16, 16, 0xf0ff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } } 146}; 147 148static const CGEN_IFMT ifmt_mvfachi_a ATTRIBUTE_UNUSED = { 149 16, 16, 0xf0f3, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_OP3) }, { 0 } } 150}; 151 152static const CGEN_IFMT ifmt_mvfc ATTRIBUTE_UNUSED = { 153 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } } 154}; 155 156static const CGEN_IFMT ifmt_mvtachi ATTRIBUTE_UNUSED = { 157 16, 16, 0xf0ff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } } 158}; 159 160static const CGEN_IFMT ifmt_mvtachi_a ATTRIBUTE_UNUSED = { 161 16, 16, 0xf0f3, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_OP3) }, { 0 } } 162}; 163 164static const CGEN_IFMT ifmt_mvtc ATTRIBUTE_UNUSED = { 165 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } } 166}; 167 168static const CGEN_IFMT ifmt_nop ATTRIBUTE_UNUSED = { 169 16, 16, 0xffff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } } 170}; 171 172static const CGEN_IFMT ifmt_rac_dsi ATTRIBUTE_UNUSED = { 173 16, 16, 0xf3f2, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } } 174}; 175 176static const CGEN_IFMT ifmt_seth ATTRIBUTE_UNUSED = { 177 32, 32, 0xf0ff0000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_HI16) }, { 0 } } 178}; 179 180static const CGEN_IFMT ifmt_slli ATTRIBUTE_UNUSED = { 181 16, 16, 0xf0e0, { { F (F_OP1) }, { F (F_R1) }, { F (F_SHIFT_OP2) }, { F (F_UIMM5) }, { 0 } } 182}; 183 184static const CGEN_IFMT ifmt_st_d ATTRIBUTE_UNUSED = { 185 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } 186}; 187 188static const CGEN_IFMT ifmt_trap ATTRIBUTE_UNUSED = { 189 16, 16, 0xfff0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_UIMM4) }, { 0 } } 190}; 191 192static const CGEN_IFMT ifmt_satb ATTRIBUTE_UNUSED = { 193 32, 32, 0xf0f0ffff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } } 194}; 195 196static const CGEN_IFMT ifmt_clrpsw ATTRIBUTE_UNUSED = { 197 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_UIMM8) }, { 0 } } 198}; 199 200static const CGEN_IFMT ifmt_bset ATTRIBUTE_UNUSED = { 201 32, 32, 0xf8f00000, { { F (F_OP1) }, { F (F_BIT4) }, { F (F_UIMM3) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } 202}; 203 204static const CGEN_IFMT ifmt_btst ATTRIBUTE_UNUSED = { 205 16, 16, 0xf8f0, { { F (F_OP1) }, { F (F_BIT4) }, { F (F_UIMM3) }, { F (F_OP2) }, { F (F_R2) }, { 0 } } 206}; 207 208#undef F 209 210#define A(a) (1 << CGEN_INSN_##a) 211#define OPERAND(op) M32R_OPERAND_##op 212#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ 213#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) 214 215/* The instruction table. */ 216 217static const CGEN_OPCODE m32r_cgen_insn_opcode_table[MAX_INSNS] = 218{ 219 /* Special null first entry. 220 A `num' value of zero is thus invalid. 221 Also, the special `invalid' insn resides here. */ 222 { { 0, 0, 0, 0 }, {{0}}, 0, {0}}, 223/* add $dr,$sr */ 224 { 225 { 0, 0, 0, 0 }, 226 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 227 & ifmt_add, { 0xa0 } 228 }, 229/* add3 $dr,$sr,$hash$slo16 */ 230 { 231 { 0, 0, 0, 0 }, 232 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (SLO16), 0 } }, 233 & ifmt_add3, { 0x80a00000 } 234 }, 235/* and $dr,$sr */ 236 { 237 { 0, 0, 0, 0 }, 238 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 239 & ifmt_add, { 0xc0 } 240 }, 241/* and3 $dr,$sr,$uimm16 */ 242 { 243 { 0, 0, 0, 0 }, 244 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } }, 245 & ifmt_and3, { 0x80c00000 } 246 }, 247/* or $dr,$sr */ 248 { 249 { 0, 0, 0, 0 }, 250 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 251 & ifmt_add, { 0xe0 } 252 }, 253/* or3 $dr,$sr,$hash$ulo16 */ 254 { 255 { 0, 0, 0, 0 }, 256 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (ULO16), 0 } }, 257 & ifmt_or3, { 0x80e00000 } 258 }, 259/* xor $dr,$sr */ 260 { 261 { 0, 0, 0, 0 }, 262 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 263 & ifmt_add, { 0xd0 } 264 }, 265/* xor3 $dr,$sr,$uimm16 */ 266 { 267 { 0, 0, 0, 0 }, 268 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } }, 269 & ifmt_and3, { 0x80d00000 } 270 }, 271/* addi $dr,$simm8 */ 272 { 273 { 0, 0, 0, 0 }, 274 { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } }, 275 & ifmt_addi, { 0x4000 } 276 }, 277/* addv $dr,$sr */ 278 { 279 { 0, 0, 0, 0 }, 280 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 281 & ifmt_add, { 0x80 } 282 }, 283/* addv3 $dr,$sr,$simm16 */ 284 { 285 { 0, 0, 0, 0 }, 286 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } }, 287 & ifmt_addv3, { 0x80800000 } 288 }, 289/* addx $dr,$sr */ 290 { 291 { 0, 0, 0, 0 }, 292 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 293 & ifmt_add, { 0x90 } 294 }, 295/* bc.s $disp8 */ 296 { 297 { 0, 0, 0, 0 }, 298 { { MNEM, ' ', OP (DISP8), 0 } }, 299 & ifmt_bc8, { 0x7c00 } 300 }, 301/* bc.l $disp24 */ 302 { 303 { 0, 0, 0, 0 }, 304 { { MNEM, ' ', OP (DISP24), 0 } }, 305 & ifmt_bc24, { 0xfc000000 } 306 }, 307/* beq $src1,$src2,$disp16 */ 308 { 309 { 0, 0, 0, 0 }, 310 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } }, 311 & ifmt_beq, { 0xb0000000 } 312 }, 313/* beqz $src2,$disp16 */ 314 { 315 { 0, 0, 0, 0 }, 316 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } }, 317 & ifmt_beqz, { 0xb0800000 } 318 }, 319/* bgez $src2,$disp16 */ 320 { 321 { 0, 0, 0, 0 }, 322 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } }, 323 & ifmt_beqz, { 0xb0b00000 } 324 }, 325/* bgtz $src2,$disp16 */ 326 { 327 { 0, 0, 0, 0 }, 328 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } }, 329 & ifmt_beqz, { 0xb0d00000 } 330 }, 331/* blez $src2,$disp16 */ 332 { 333 { 0, 0, 0, 0 }, 334 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } }, 335 & ifmt_beqz, { 0xb0c00000 } 336 }, 337/* bltz $src2,$disp16 */ 338 { 339 { 0, 0, 0, 0 }, 340 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } }, 341 & ifmt_beqz, { 0xb0a00000 } 342 }, 343/* bnez $src2,$disp16 */ 344 { 345 { 0, 0, 0, 0 }, 346 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } }, 347 & ifmt_beqz, { 0xb0900000 } 348 }, 349/* bl.s $disp8 */ 350 { 351 { 0, 0, 0, 0 }, 352 { { MNEM, ' ', OP (DISP8), 0 } }, 353 & ifmt_bc8, { 0x7e00 } 354 }, 355/* bl.l $disp24 */ 356 { 357 { 0, 0, 0, 0 }, 358 { { MNEM, ' ', OP (DISP24), 0 } }, 359 & ifmt_bc24, { 0xfe000000 } 360 }, 361/* bcl.s $disp8 */ 362 { 363 { 0, 0, 0, 0 }, 364 { { MNEM, ' ', OP (DISP8), 0 } }, 365 & ifmt_bc8, { 0x7800 } 366 }, 367/* bcl.l $disp24 */ 368 { 369 { 0, 0, 0, 0 }, 370 { { MNEM, ' ', OP (DISP24), 0 } }, 371 & ifmt_bc24, { 0xf8000000 } 372 }, 373/* bnc.s $disp8 */ 374 { 375 { 0, 0, 0, 0 }, 376 { { MNEM, ' ', OP (DISP8), 0 } }, 377 & ifmt_bc8, { 0x7d00 } 378 }, 379/* bnc.l $disp24 */ 380 { 381 { 0, 0, 0, 0 }, 382 { { MNEM, ' ', OP (DISP24), 0 } }, 383 & ifmt_bc24, { 0xfd000000 } 384 }, 385/* bne $src1,$src2,$disp16 */ 386 { 387 { 0, 0, 0, 0 }, 388 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } }, 389 & ifmt_beq, { 0xb0100000 } 390 }, 391/* bra.s $disp8 */ 392 { 393 { 0, 0, 0, 0 }, 394 { { MNEM, ' ', OP (DISP8), 0 } }, 395 & ifmt_bc8, { 0x7f00 } 396 }, 397/* bra.l $disp24 */ 398 { 399 { 0, 0, 0, 0 }, 400 { { MNEM, ' ', OP (DISP24), 0 } }, 401 & ifmt_bc24, { 0xff000000 } 402 }, 403/* bncl.s $disp8 */ 404 { 405 { 0, 0, 0, 0 }, 406 { { MNEM, ' ', OP (DISP8), 0 } }, 407 & ifmt_bc8, { 0x7900 } 408 }, 409/* bncl.l $disp24 */ 410 { 411 { 0, 0, 0, 0 }, 412 { { MNEM, ' ', OP (DISP24), 0 } }, 413 & ifmt_bc24, { 0xf9000000 } 414 }, 415/* cmp $src1,$src2 */ 416 { 417 { 0, 0, 0, 0 }, 418 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, 419 & ifmt_cmp, { 0x40 } 420 }, 421/* cmpi $src2,$simm16 */ 422 { 423 { 0, 0, 0, 0 }, 424 { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } }, 425 & ifmt_cmpi, { 0x80400000 } 426 }, 427/* cmpu $src1,$src2 */ 428 { 429 { 0, 0, 0, 0 }, 430 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, 431 & ifmt_cmp, { 0x50 } 432 }, 433/* cmpui $src2,$simm16 */ 434 { 435 { 0, 0, 0, 0 }, 436 { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } }, 437 & ifmt_cmpi, { 0x80500000 } 438 }, 439/* cmpeq $src1,$src2 */ 440 { 441 { 0, 0, 0, 0 }, 442 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, 443 & ifmt_cmp, { 0x60 } 444 }, 445/* cmpz $src2 */ 446 { 447 { 0, 0, 0, 0 }, 448 { { MNEM, ' ', OP (SRC2), 0 } }, 449 & ifmt_cmpz, { 0x70 } 450 }, 451/* div $dr,$sr */ 452 { 453 { 0, 0, 0, 0 }, 454 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 455 & ifmt_div, { 0x90000000 } 456 }, 457/* divu $dr,$sr */ 458 { 459 { 0, 0, 0, 0 }, 460 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 461 & ifmt_div, { 0x90100000 } 462 }, 463/* rem $dr,$sr */ 464 { 465 { 0, 0, 0, 0 }, 466 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 467 & ifmt_div, { 0x90200000 } 468 }, 469/* remu $dr,$sr */ 470 { 471 { 0, 0, 0, 0 }, 472 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 473 & ifmt_div, { 0x90300000 } 474 }, 475/* remh $dr,$sr */ 476 { 477 { 0, 0, 0, 0 }, 478 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 479 & ifmt_div, { 0x90200010 } 480 }, 481/* remuh $dr,$sr */ 482 { 483 { 0, 0, 0, 0 }, 484 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 485 & ifmt_div, { 0x90300010 } 486 }, 487/* remb $dr,$sr */ 488 { 489 { 0, 0, 0, 0 }, 490 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 491 & ifmt_div, { 0x90200018 } 492 }, 493/* remub $dr,$sr */ 494 { 495 { 0, 0, 0, 0 }, 496 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 497 & ifmt_div, { 0x90300018 } 498 }, 499/* divuh $dr,$sr */ 500 { 501 { 0, 0, 0, 0 }, 502 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 503 & ifmt_div, { 0x90100010 } 504 }, 505/* divb $dr,$sr */ 506 { 507 { 0, 0, 0, 0 }, 508 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 509 & ifmt_div, { 0x90000018 } 510 }, 511/* divub $dr,$sr */ 512 { 513 { 0, 0, 0, 0 }, 514 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 515 & ifmt_div, { 0x90100018 } 516 }, 517/* divh $dr,$sr */ 518 { 519 { 0, 0, 0, 0 }, 520 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 521 & ifmt_div, { 0x90000010 } 522 }, 523/* jc $sr */ 524 { 525 { 0, 0, 0, 0 }, 526 { { MNEM, ' ', OP (SR), 0 } }, 527 & ifmt_jc, { 0x1cc0 } 528 }, 529/* jnc $sr */ 530 { 531 { 0, 0, 0, 0 }, 532 { { MNEM, ' ', OP (SR), 0 } }, 533 & ifmt_jc, { 0x1dc0 } 534 }, 535/* jl $sr */ 536 { 537 { 0, 0, 0, 0 }, 538 { { MNEM, ' ', OP (SR), 0 } }, 539 & ifmt_jc, { 0x1ec0 } 540 }, 541/* jmp $sr */ 542 { 543 { 0, 0, 0, 0 }, 544 { { MNEM, ' ', OP (SR), 0 } }, 545 & ifmt_jc, { 0x1fc0 } 546 }, 547/* ld $dr,@$sr */ 548 { 549 { 0, 0, 0, 0 }, 550 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } }, 551 & ifmt_add, { 0x20c0 } 552 }, 553/* ld $dr,@($slo16,$sr) */ 554 { 555 { 0, 0, 0, 0 }, 556 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } }, 557 & ifmt_add3, { 0xa0c00000 } 558 }, 559/* ldb $dr,@$sr */ 560 { 561 { 0, 0, 0, 0 }, 562 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } }, 563 & ifmt_add, { 0x2080 } 564 }, 565/* ldb $dr,@($slo16,$sr) */ 566 { 567 { 0, 0, 0, 0 }, 568 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } }, 569 & ifmt_add3, { 0xa0800000 } 570 }, 571/* ldh $dr,@$sr */ 572 { 573 { 0, 0, 0, 0 }, 574 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } }, 575 & ifmt_add, { 0x20a0 } 576 }, 577/* ldh $dr,@($slo16,$sr) */ 578 { 579 { 0, 0, 0, 0 }, 580 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } }, 581 & ifmt_add3, { 0xa0a00000 } 582 }, 583/* ldub $dr,@$sr */ 584 { 585 { 0, 0, 0, 0 }, 586 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } }, 587 & ifmt_add, { 0x2090 } 588 }, 589/* ldub $dr,@($slo16,$sr) */ 590 { 591 { 0, 0, 0, 0 }, 592 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } }, 593 & ifmt_add3, { 0xa0900000 } 594 }, 595/* lduh $dr,@$sr */ 596 { 597 { 0, 0, 0, 0 }, 598 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } }, 599 & ifmt_add, { 0x20b0 } 600 }, 601/* lduh $dr,@($slo16,$sr) */ 602 { 603 { 0, 0, 0, 0 }, 604 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } }, 605 & ifmt_add3, { 0xa0b00000 } 606 }, 607/* ld $dr,@$sr+ */ 608 { 609 { 0, 0, 0, 0 }, 610 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), '+', 0 } }, 611 & ifmt_add, { 0x20e0 } 612 }, 613/* ld24 $dr,$uimm24 */ 614 { 615 { 0, 0, 0, 0 }, 616 { { MNEM, ' ', OP (DR), ',', OP (UIMM24), 0 } }, 617 & ifmt_ld24, { 0xe0000000 } 618 }, 619/* ldi8 $dr,$simm8 */ 620 { 621 { 0, 0, 0, 0 }, 622 { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } }, 623 & ifmt_addi, { 0x6000 } 624 }, 625/* ldi16 $dr,$hash$slo16 */ 626 { 627 { 0, 0, 0, 0 }, 628 { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } }, 629 & ifmt_ldi16, { 0x90f00000 } 630 }, 631/* lock $dr,@$sr */ 632 { 633 { 0, 0, 0, 0 }, 634 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } }, 635 & ifmt_add, { 0x20d0 } 636 }, 637/* machi $src1,$src2 */ 638 { 639 { 0, 0, 0, 0 }, 640 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, 641 & ifmt_cmp, { 0x3040 } 642 }, 643/* machi $src1,$src2,$acc */ 644 { 645 { 0, 0, 0, 0 }, 646 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, 647 & ifmt_machi_a, { 0x3040 } 648 }, 649/* maclo $src1,$src2 */ 650 { 651 { 0, 0, 0, 0 }, 652 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, 653 & ifmt_cmp, { 0x3050 } 654 }, 655/* maclo $src1,$src2,$acc */ 656 { 657 { 0, 0, 0, 0 }, 658 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, 659 & ifmt_machi_a, { 0x3050 } 660 }, 661/* macwhi $src1,$src2 */ 662 { 663 { 0, 0, 0, 0 }, 664 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, 665 & ifmt_cmp, { 0x3060 } 666 }, 667/* macwhi $src1,$src2,$acc */ 668 { 669 { 0, 0, 0, 0 }, 670 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, 671 & ifmt_machi_a, { 0x3060 } 672 }, 673/* macwlo $src1,$src2 */ 674 { 675 { 0, 0, 0, 0 }, 676 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, 677 & ifmt_cmp, { 0x3070 } 678 }, 679/* macwlo $src1,$src2,$acc */ 680 { 681 { 0, 0, 0, 0 }, 682 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, 683 & ifmt_machi_a, { 0x3070 } 684 }, 685/* mul $dr,$sr */ 686 { 687 { 0, 0, 0, 0 }, 688 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 689 & ifmt_add, { 0x1060 } 690 }, 691/* mulhi $src1,$src2 */ 692 { 693 { 0, 0, 0, 0 }, 694 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, 695 & ifmt_cmp, { 0x3000 } 696 }, 697/* mulhi $src1,$src2,$acc */ 698 { 699 { 0, 0, 0, 0 }, 700 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, 701 & ifmt_machi_a, { 0x3000 } 702 }, 703/* mullo $src1,$src2 */ 704 { 705 { 0, 0, 0, 0 }, 706 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, 707 & ifmt_cmp, { 0x3010 } 708 }, 709/* mullo $src1,$src2,$acc */ 710 { 711 { 0, 0, 0, 0 }, 712 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, 713 & ifmt_machi_a, { 0x3010 } 714 }, 715/* mulwhi $src1,$src2 */ 716 { 717 { 0, 0, 0, 0 }, 718 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, 719 & ifmt_cmp, { 0x3020 } 720 }, 721/* mulwhi $src1,$src2,$acc */ 722 { 723 { 0, 0, 0, 0 }, 724 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, 725 & ifmt_machi_a, { 0x3020 } 726 }, 727/* mulwlo $src1,$src2 */ 728 { 729 { 0, 0, 0, 0 }, 730 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, 731 & ifmt_cmp, { 0x3030 } 732 }, 733/* mulwlo $src1,$src2,$acc */ 734 { 735 { 0, 0, 0, 0 }, 736 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, 737 & ifmt_machi_a, { 0x3030 } 738 }, 739/* mv $dr,$sr */ 740 { 741 { 0, 0, 0, 0 }, 742 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 743 & ifmt_add, { 0x1080 } 744 }, 745/* mvfachi $dr */ 746 { 747 { 0, 0, 0, 0 }, 748 { { MNEM, ' ', OP (DR), 0 } }, 749 & ifmt_mvfachi, { 0x50f0 } 750 }, 751/* mvfachi $dr,$accs */ 752 { 753 { 0, 0, 0, 0 }, 754 { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } }, 755 & ifmt_mvfachi_a, { 0x50f0 } 756 }, 757/* mvfaclo $dr */ 758 { 759 { 0, 0, 0, 0 }, 760 { { MNEM, ' ', OP (DR), 0 } }, 761 & ifmt_mvfachi, { 0x50f1 } 762 }, 763/* mvfaclo $dr,$accs */ 764 { 765 { 0, 0, 0, 0 }, 766 { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } }, 767 & ifmt_mvfachi_a, { 0x50f1 } 768 }, 769/* mvfacmi $dr */ 770 { 771 { 0, 0, 0, 0 }, 772 { { MNEM, ' ', OP (DR), 0 } }, 773 & ifmt_mvfachi, { 0x50f2 } 774 }, 775/* mvfacmi $dr,$accs */ 776 { 777 { 0, 0, 0, 0 }, 778 { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } }, 779 & ifmt_mvfachi_a, { 0x50f2 } 780 }, 781/* mvfc $dr,$scr */ 782 { 783 { 0, 0, 0, 0 }, 784 { { MNEM, ' ', OP (DR), ',', OP (SCR), 0 } }, 785 & ifmt_mvfc, { 0x1090 } 786 }, 787/* mvtachi $src1 */ 788 { 789 { 0, 0, 0, 0 }, 790 { { MNEM, ' ', OP (SRC1), 0 } }, 791 & ifmt_mvtachi, { 0x5070 } 792 }, 793/* mvtachi $src1,$accs */ 794 { 795 { 0, 0, 0, 0 }, 796 { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } }, 797 & ifmt_mvtachi_a, { 0x5070 } 798 }, 799/* mvtaclo $src1 */ 800 { 801 { 0, 0, 0, 0 }, 802 { { MNEM, ' ', OP (SRC1), 0 } }, 803 & ifmt_mvtachi, { 0x5071 } 804 }, 805/* mvtaclo $src1,$accs */ 806 { 807 { 0, 0, 0, 0 }, 808 { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } }, 809 & ifmt_mvtachi_a, { 0x5071 } 810 }, 811/* mvtc $sr,$dcr */ 812 { 813 { 0, 0, 0, 0 }, 814 { { MNEM, ' ', OP (SR), ',', OP (DCR), 0 } }, 815 & ifmt_mvtc, { 0x10a0 } 816 }, 817/* neg $dr,$sr */ 818 { 819 { 0, 0, 0, 0 }, 820 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 821 & ifmt_add, { 0x30 } 822 }, 823/* nop */ 824 { 825 { 0, 0, 0, 0 }, 826 { { MNEM, 0 } }, 827 & ifmt_nop, { 0x7000 } 828 }, 829/* not $dr,$sr */ 830 { 831 { 0, 0, 0, 0 }, 832 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 833 & ifmt_add, { 0xb0 } 834 }, 835/* rac */ 836 { 837 { 0, 0, 0, 0 }, 838 { { MNEM, 0 } }, 839 & ifmt_nop, { 0x5090 } 840 }, 841/* rac $accd,$accs,$imm1 */ 842 { 843 { 0, 0, 0, 0 }, 844 { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } }, 845 & ifmt_rac_dsi, { 0x5090 } 846 }, 847/* rach */ 848 { 849 { 0, 0, 0, 0 }, 850 { { MNEM, 0 } }, 851 & ifmt_nop, { 0x5080 } 852 }, 853/* rach $accd,$accs,$imm1 */ 854 { 855 { 0, 0, 0, 0 }, 856 { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } }, 857 & ifmt_rac_dsi, { 0x5080 } 858 }, 859/* rte */ 860 { 861 { 0, 0, 0, 0 }, 862 { { MNEM, 0 } }, 863 & ifmt_nop, { 0x10d6 } 864 }, 865/* seth $dr,$hash$hi16 */ 866 { 867 { 0, 0, 0, 0 }, 868 { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (HI16), 0 } }, 869 & ifmt_seth, { 0xd0c00000 } 870 }, 871/* sll $dr,$sr */ 872 { 873 { 0, 0, 0, 0 }, 874 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 875 & ifmt_add, { 0x1040 } 876 }, 877/* sll3 $dr,$sr,$simm16 */ 878 { 879 { 0, 0, 0, 0 }, 880 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } }, 881 & ifmt_addv3, { 0x90c00000 } 882 }, 883/* slli $dr,$uimm5 */ 884 { 885 { 0, 0, 0, 0 }, 886 { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } }, 887 & ifmt_slli, { 0x5040 } 888 }, 889/* sra $dr,$sr */ 890 { 891 { 0, 0, 0, 0 }, 892 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 893 & ifmt_add, { 0x1020 } 894 }, 895/* sra3 $dr,$sr,$simm16 */ 896 { 897 { 0, 0, 0, 0 }, 898 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } }, 899 & ifmt_addv3, { 0x90a00000 } 900 }, 901/* srai $dr,$uimm5 */ 902 { 903 { 0, 0, 0, 0 }, 904 { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } }, 905 & ifmt_slli, { 0x5020 } 906 }, 907/* srl $dr,$sr */ 908 { 909 { 0, 0, 0, 0 }, 910 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 911 & ifmt_add, { 0x1000 } 912 }, 913/* srl3 $dr,$sr,$simm16 */ 914 { 915 { 0, 0, 0, 0 }, 916 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } }, 917 & ifmt_addv3, { 0x90800000 } 918 }, 919/* srli $dr,$uimm5 */ 920 { 921 { 0, 0, 0, 0 }, 922 { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } }, 923 & ifmt_slli, { 0x5000 } 924 }, 925/* st $src1,@$src2 */ 926 { 927 { 0, 0, 0, 0 }, 928 { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } }, 929 & ifmt_cmp, { 0x2040 } 930 }, 931/* st $src1,@($slo16,$src2) */ 932 { 933 { 0, 0, 0, 0 }, 934 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } }, 935 & ifmt_st_d, { 0xa0400000 } 936 }, 937/* stb $src1,@$src2 */ 938 { 939 { 0, 0, 0, 0 }, 940 { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } }, 941 & ifmt_cmp, { 0x2000 } 942 }, 943/* stb $src1,@($slo16,$src2) */ 944 { 945 { 0, 0, 0, 0 }, 946 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } }, 947 & ifmt_st_d, { 0xa0000000 } 948 }, 949/* sth $src1,@$src2 */ 950 { 951 { 0, 0, 0, 0 }, 952 { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } }, 953 & ifmt_cmp, { 0x2020 } 954 }, 955/* sth $src1,@($slo16,$src2) */ 956 { 957 { 0, 0, 0, 0 }, 958 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } }, 959 & ifmt_st_d, { 0xa0200000 } 960 }, 961/* st $src1,@+$src2 */ 962 { 963 { 0, 0, 0, 0 }, 964 { { MNEM, ' ', OP (SRC1), ',', '@', '+', OP (SRC2), 0 } }, 965 & ifmt_cmp, { 0x2060 } 966 }, 967/* sth $src1,@$src2+ */ 968 { 969 { 0, 0, 0, 0 }, 970 { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), '+', 0 } }, 971 & ifmt_cmp, { 0x2030 } 972 }, 973/* stb $src1,@$src2+ */ 974 { 975 { 0, 0, 0, 0 }, 976 { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), '+', 0 } }, 977 & ifmt_cmp, { 0x2010 } 978 }, 979/* st $src1,@-$src2 */ 980 { 981 { 0, 0, 0, 0 }, 982 { { MNEM, ' ', OP (SRC1), ',', '@', '-', OP (SRC2), 0 } }, 983 & ifmt_cmp, { 0x2070 } 984 }, 985/* sub $dr,$sr */ 986 { 987 { 0, 0, 0, 0 }, 988 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 989 & ifmt_add, { 0x20 } 990 }, 991/* subv $dr,$sr */ 992 { 993 { 0, 0, 0, 0 }, 994 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 995 & ifmt_add, { 0x0 } 996 }, 997/* subx $dr,$sr */ 998 { 999 { 0, 0, 0, 0 }, 1000 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 1001 & ifmt_add, { 0x10 } 1002 }, 1003/* trap $uimm4 */ 1004 { 1005 { 0, 0, 0, 0 }, 1006 { { MNEM, ' ', OP (UIMM4), 0 } }, 1007 & ifmt_trap, { 0x10f0 } 1008 }, 1009/* unlock $src1,@$src2 */ 1010 { 1011 { 0, 0, 0, 0 }, 1012 { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } }, 1013 & ifmt_cmp, { 0x2050 } 1014 }, 1015/* satb $dr,$sr */ 1016 { 1017 { 0, 0, 0, 0 }, 1018 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 1019 & ifmt_satb, { 0x80600300 } 1020 }, 1021/* sath $dr,$sr */ 1022 { 1023 { 0, 0, 0, 0 }, 1024 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 1025 & ifmt_satb, { 0x80600200 } 1026 }, 1027/* sat $dr,$sr */ 1028 { 1029 { 0, 0, 0, 0 }, 1030 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 1031 & ifmt_satb, { 0x80600000 } 1032 }, 1033/* pcmpbz $src2 */ 1034 { 1035 { 0, 0, 0, 0 }, 1036 { { MNEM, ' ', OP (SRC2), 0 } }, 1037 & ifmt_cmpz, { 0x370 } 1038 }, 1039/* sadd */ 1040 { 1041 { 0, 0, 0, 0 }, 1042 { { MNEM, 0 } }, 1043 & ifmt_nop, { 0x50e4 } 1044 }, 1045/* macwu1 $src1,$src2 */ 1046 { 1047 { 0, 0, 0, 0 }, 1048 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, 1049 & ifmt_cmp, { 0x50b0 } 1050 }, 1051/* msblo $src1,$src2 */ 1052 { 1053 { 0, 0, 0, 0 }, 1054 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, 1055 & ifmt_cmp, { 0x50d0 } 1056 }, 1057/* mulwu1 $src1,$src2 */ 1058 { 1059 { 0, 0, 0, 0 }, 1060 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, 1061 & ifmt_cmp, { 0x50a0 } 1062 }, 1063/* maclh1 $src1,$src2 */ 1064 { 1065 { 0, 0, 0, 0 }, 1066 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, 1067 & ifmt_cmp, { 0x50c0 } 1068 }, 1069/* sc */ 1070 { 1071 { 0, 0, 0, 0 }, 1072 { { MNEM, 0 } }, 1073 & ifmt_nop, { 0x7401 } 1074 }, 1075/* snc */ 1076 { 1077 { 0, 0, 0, 0 }, 1078 { { MNEM, 0 } }, 1079 & ifmt_nop, { 0x7501 } 1080 }, 1081/* clrpsw $uimm8 */ 1082 { 1083 { 0, 0, 0, 0 }, 1084 { { MNEM, ' ', OP (UIMM8), 0 } }, 1085 & ifmt_clrpsw, { 0x7200 } 1086 }, 1087/* setpsw $uimm8 */ 1088 { 1089 { 0, 0, 0, 0 }, 1090 { { MNEM, ' ', OP (UIMM8), 0 } }, 1091 & ifmt_clrpsw, { 0x7100 } 1092 }, 1093/* bset $uimm3,@($slo16,$sr) */ 1094 { 1095 { 0, 0, 0, 0 }, 1096 { { MNEM, ' ', OP (UIMM3), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } }, 1097 & ifmt_bset, { 0xa0600000 } 1098 }, 1099/* bclr $uimm3,@($slo16,$sr) */ 1100 { 1101 { 0, 0, 0, 0 }, 1102 { { MNEM, ' ', OP (UIMM3), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } }, 1103 & ifmt_bset, { 0xa0700000 } 1104 }, 1105/* btst $uimm3,$sr */ 1106 { 1107 { 0, 0, 0, 0 }, 1108 { { MNEM, ' ', OP (UIMM3), ',', OP (SR), 0 } }, 1109 & ifmt_btst, { 0xf0 } 1110 }, 1111}; 1112 1113#undef A 1114#undef OPERAND 1115#undef MNEM 1116#undef OP 1117 1118/* Formats for ALIAS macro-insns. */ 1119 1120#define F(f) & m32r_cgen_ifld_table[M32R_##f] 1121static const CGEN_IFMT ifmt_bc8r ATTRIBUTE_UNUSED = { 1122 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } } 1123}; 1124 1125static const CGEN_IFMT ifmt_bc24r ATTRIBUTE_UNUSED = { 1126 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } } 1127}; 1128 1129static const CGEN_IFMT ifmt_bl8r ATTRIBUTE_UNUSED = { 1130 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } } 1131}; 1132 1133static const CGEN_IFMT ifmt_bl24r ATTRIBUTE_UNUSED = { 1134 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } } 1135}; 1136 1137static const CGEN_IFMT ifmt_bcl8r ATTRIBUTE_UNUSED = { 1138 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } } 1139}; 1140 1141static const CGEN_IFMT ifmt_bcl24r ATTRIBUTE_UNUSED = { 1142 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } } 1143}; 1144 1145static const CGEN_IFMT ifmt_bnc8r ATTRIBUTE_UNUSED = { 1146 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } } 1147}; 1148 1149static const CGEN_IFMT ifmt_bnc24r ATTRIBUTE_UNUSED = { 1150 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } } 1151}; 1152 1153static const CGEN_IFMT ifmt_bra8r ATTRIBUTE_UNUSED = { 1154 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } } 1155}; 1156 1157static const CGEN_IFMT ifmt_bra24r ATTRIBUTE_UNUSED = { 1158 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } } 1159}; 1160 1161static const CGEN_IFMT ifmt_bncl8r ATTRIBUTE_UNUSED = { 1162 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } } 1163}; 1164 1165static const CGEN_IFMT ifmt_bncl24r ATTRIBUTE_UNUSED = { 1166 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } } 1167}; 1168 1169static const CGEN_IFMT ifmt_ld_2 ATTRIBUTE_UNUSED = { 1170 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } } 1171}; 1172 1173static const CGEN_IFMT ifmt_ld_d2 ATTRIBUTE_UNUSED = { 1174 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } 1175}; 1176 1177static const CGEN_IFMT ifmt_ldb_2 ATTRIBUTE_UNUSED = { 1178 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } } 1179}; 1180 1181static const CGEN_IFMT ifmt_ldb_d2 ATTRIBUTE_UNUSED = { 1182 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } 1183}; 1184 1185static const CGEN_IFMT ifmt_ldh_2 ATTRIBUTE_UNUSED = { 1186 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } } 1187}; 1188 1189static const CGEN_IFMT ifmt_ldh_d2 ATTRIBUTE_UNUSED = { 1190 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } 1191}; 1192 1193static const CGEN_IFMT ifmt_ldub_2 ATTRIBUTE_UNUSED = { 1194 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } } 1195}; 1196 1197static const CGEN_IFMT ifmt_ldub_d2 ATTRIBUTE_UNUSED = { 1198 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } 1199}; 1200 1201static const CGEN_IFMT ifmt_lduh_2 ATTRIBUTE_UNUSED = { 1202 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } } 1203}; 1204 1205static const CGEN_IFMT ifmt_lduh_d2 ATTRIBUTE_UNUSED = { 1206 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } 1207}; 1208 1209static const CGEN_IFMT ifmt_pop ATTRIBUTE_UNUSED = { 1210 16, 16, 0xf0ff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } } 1211}; 1212 1213static const CGEN_IFMT ifmt_ldi8a ATTRIBUTE_UNUSED = { 1214 16, 16, 0xf000, { { F (F_OP1) }, { F (F_R1) }, { F (F_SIMM8) }, { 0 } } 1215}; 1216 1217static const CGEN_IFMT ifmt_ldi16a ATTRIBUTE_UNUSED = { 1218 32, 32, 0xf0ff0000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_R1) }, { F (F_SIMM16) }, { 0 } } 1219}; 1220 1221static const CGEN_IFMT ifmt_rac_d ATTRIBUTE_UNUSED = { 1222 16, 16, 0xf3ff, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } } 1223}; 1224 1225static const CGEN_IFMT ifmt_rac_ds ATTRIBUTE_UNUSED = { 1226 16, 16, 0xf3f3, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } } 1227}; 1228 1229static const CGEN_IFMT ifmt_rach_d ATTRIBUTE_UNUSED = { 1230 16, 16, 0xf3ff, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } } 1231}; 1232 1233static const CGEN_IFMT ifmt_rach_ds ATTRIBUTE_UNUSED = { 1234 16, 16, 0xf3f3, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } } 1235}; 1236 1237static const CGEN_IFMT ifmt_st_2 ATTRIBUTE_UNUSED = { 1238 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } } 1239}; 1240 1241static const CGEN_IFMT ifmt_st_d2 ATTRIBUTE_UNUSED = { 1242 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } 1243}; 1244 1245static const CGEN_IFMT ifmt_stb_2 ATTRIBUTE_UNUSED = { 1246 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } } 1247}; 1248 1249static const CGEN_IFMT ifmt_stb_d2 ATTRIBUTE_UNUSED = { 1250 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } 1251}; 1252 1253static const CGEN_IFMT ifmt_sth_2 ATTRIBUTE_UNUSED = { 1254 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } } 1255}; 1256 1257static const CGEN_IFMT ifmt_sth_d2 ATTRIBUTE_UNUSED = { 1258 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } 1259}; 1260 1261static const CGEN_IFMT ifmt_push ATTRIBUTE_UNUSED = { 1262 16, 16, 0xf0ff, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } } 1263}; 1264 1265#undef F 1266 1267/* Each non-simple macro entry points to an array of expansion possibilities. */ 1268 1269#define A(a) (1 << CGEN_INSN_##a) 1270#define OPERAND(op) M32R_OPERAND_##op 1271#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ 1272#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) 1273 1274/* The macro instruction table. */ 1275 1276static const CGEN_IBASE m32r_cgen_macro_insn_table[] = 1277{ 1278/* bc $disp8 */ 1279 { 1280 -1, "bc8r", "bc", 16, 1281 { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } 1282 }, 1283/* bc $disp24 */ 1284 { 1285 -1, "bc24r", "bc", 32, 1286 { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } 1287 }, 1288/* bl $disp8 */ 1289 { 1290 -1, "bl8r", "bl", 16, 1291 { 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } 1292 }, 1293/* bl $disp24 */ 1294 { 1295 -1, "bl24r", "bl", 32, 1296 { 0|A(RELAXED)|A(UNCOND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } 1297 }, 1298/* bcl $disp8 */ 1299 { 1300 -1, "bcl8r", "bcl", 16, 1301 { 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } } 1302 }, 1303/* bcl $disp24 */ 1304 { 1305 -1, "bcl24r", "bcl", 32, 1306 { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } } 1307 }, 1308/* bnc $disp8 */ 1309 { 1310 -1, "bnc8r", "bnc", 16, 1311 { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } 1312 }, 1313/* bnc $disp24 */ 1314 { 1315 -1, "bnc24r", "bnc", 32, 1316 { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } 1317 }, 1318/* bra $disp8 */ 1319 { 1320 -1, "bra8r", "bra", 16, 1321 { 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } 1322 }, 1323/* bra $disp24 */ 1324 { 1325 -1, "bra24r", "bra", 32, 1326 { 0|A(RELAXED)|A(UNCOND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } 1327 }, 1328/* bncl $disp8 */ 1329 { 1330 -1, "bncl8r", "bncl", 16, 1331 { 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } } 1332 }, 1333/* bncl $disp24 */ 1334 { 1335 -1, "bncl24r", "bncl", 32, 1336 { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } } 1337 }, 1338/* ld $dr,@($sr) */ 1339 { 1340 -1, "ld-2", "ld", 16, 1341 { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } 1342 }, 1343/* ld $dr,@($sr,$slo16) */ 1344 { 1345 -1, "ld-d2", "ld", 32, 1346 { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } 1347 }, 1348/* ldb $dr,@($sr) */ 1349 { 1350 -1, "ldb-2", "ldb", 16, 1351 { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } 1352 }, 1353/* ldb $dr,@($sr,$slo16) */ 1354 { 1355 -1, "ldb-d2", "ldb", 32, 1356 { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } 1357 }, 1358/* ldh $dr,@($sr) */ 1359 { 1360 -1, "ldh-2", "ldh", 16, 1361 { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } 1362 }, 1363/* ldh $dr,@($sr,$slo16) */ 1364 { 1365 -1, "ldh-d2", "ldh", 32, 1366 { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } 1367 }, 1368/* ldub $dr,@($sr) */ 1369 { 1370 -1, "ldub-2", "ldub", 16, 1371 { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } 1372 }, 1373/* ldub $dr,@($sr,$slo16) */ 1374 { 1375 -1, "ldub-d2", "ldub", 32, 1376 { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } 1377 }, 1378/* lduh $dr,@($sr) */ 1379 { 1380 -1, "lduh-2", "lduh", 16, 1381 { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } 1382 }, 1383/* lduh $dr,@($sr,$slo16) */ 1384 { 1385 -1, "lduh-d2", "lduh", 32, 1386 { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } 1387 }, 1388/* pop $dr */ 1389 { 1390 -1, "pop", "pop", 16, 1391 { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } 1392 }, 1393/* ldi $dr,$simm8 */ 1394 { 1395 -1, "ldi8a", "ldi", 16, 1396 { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1397 }, 1398/* ldi $dr,$hash$slo16 */ 1399 { 1400 -1, "ldi16a", "ldi", 32, 1401 { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } 1402 }, 1403/* rac $accd */ 1404 { 1405 -1, "rac-d", "rac", 16, 1406 { 0|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } } 1407 }, 1408/* rac $accd,$accs */ 1409 { 1410 -1, "rac-ds", "rac", 16, 1411 { 0|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } } 1412 }, 1413/* rach $accd */ 1414 { 1415 -1, "rach-d", "rach", 16, 1416 { 0|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } } 1417 }, 1418/* rach $accd,$accs */ 1419 { 1420 -1, "rach-ds", "rach", 16, 1421 { 0|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } } 1422 }, 1423/* st $src1,@($src2) */ 1424 { 1425 -1, "st-2", "st", 16, 1426 { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } 1427 }, 1428/* st $src1,@($src2,$slo16) */ 1429 { 1430 -1, "st-d2", "st", 32, 1431 { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } 1432 }, 1433/* stb $src1,@($src2) */ 1434 { 1435 -1, "stb-2", "stb", 16, 1436 { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } 1437 }, 1438/* stb $src1,@($src2,$slo16) */ 1439 { 1440 -1, "stb-d2", "stb", 32, 1441 { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } 1442 }, 1443/* sth $src1,@($src2) */ 1444 { 1445 -1, "sth-2", "sth", 16, 1446 { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } 1447 }, 1448/* sth $src1,@($src2,$slo16) */ 1449 { 1450 -1, "sth-d2", "sth", 32, 1451 { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } 1452 }, 1453/* push $src1 */ 1454 { 1455 -1, "push", "push", 16, 1456 { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } 1457 }, 1458}; 1459 1460/* The macro instruction opcode table. */ 1461 1462static const CGEN_OPCODE m32r_cgen_macro_insn_opcode_table[] = 1463{ 1464/* bc $disp8 */ 1465 { 1466 { 0, 0, 0, 0 }, 1467 { { MNEM, ' ', OP (DISP8), 0 } }, 1468 & ifmt_bc8r, { 0x7c00 } 1469 }, 1470/* bc $disp24 */ 1471 { 1472 { 0, 0, 0, 0 }, 1473 { { MNEM, ' ', OP (DISP24), 0 } }, 1474 & ifmt_bc24r, { 0xfc000000 } 1475 }, 1476/* bl $disp8 */ 1477 { 1478 { 0, 0, 0, 0 }, 1479 { { MNEM, ' ', OP (DISP8), 0 } }, 1480 & ifmt_bl8r, { 0x7e00 } 1481 }, 1482/* bl $disp24 */ 1483 { 1484 { 0, 0, 0, 0 }, 1485 { { MNEM, ' ', OP (DISP24), 0 } }, 1486 & ifmt_bl24r, { 0xfe000000 } 1487 }, 1488/* bcl $disp8 */ 1489 { 1490 { 0, 0, 0, 0 }, 1491 { { MNEM, ' ', OP (DISP8), 0 } }, 1492 & ifmt_bcl8r, { 0x7800 } 1493 }, 1494/* bcl $disp24 */ 1495 { 1496 { 0, 0, 0, 0 }, 1497 { { MNEM, ' ', OP (DISP24), 0 } }, 1498 & ifmt_bcl24r, { 0xf8000000 } 1499 }, 1500/* bnc $disp8 */ 1501 { 1502 { 0, 0, 0, 0 }, 1503 { { MNEM, ' ', OP (DISP8), 0 } }, 1504 & ifmt_bnc8r, { 0x7d00 } 1505 }, 1506/* bnc $disp24 */ 1507 { 1508 { 0, 0, 0, 0 }, 1509 { { MNEM, ' ', OP (DISP24), 0 } }, 1510 & ifmt_bnc24r, { 0xfd000000 } 1511 }, 1512/* bra $disp8 */ 1513 { 1514 { 0, 0, 0, 0 }, 1515 { { MNEM, ' ', OP (DISP8), 0 } }, 1516 & ifmt_bra8r, { 0x7f00 } 1517 }, 1518/* bra $disp24 */ 1519 { 1520 { 0, 0, 0, 0 }, 1521 { { MNEM, ' ', OP (DISP24), 0 } }, 1522 & ifmt_bra24r, { 0xff000000 } 1523 }, 1524/* bncl $disp8 */ 1525 { 1526 { 0, 0, 0, 0 }, 1527 { { MNEM, ' ', OP (DISP8), 0 } }, 1528 & ifmt_bncl8r, { 0x7900 } 1529 }, 1530/* bncl $disp24 */ 1531 { 1532 { 0, 0, 0, 0 }, 1533 { { MNEM, ' ', OP (DISP24), 0 } }, 1534 & ifmt_bncl24r, { 0xf9000000 } 1535 }, 1536/* ld $dr,@($sr) */ 1537 { 1538 { 0, 0, 0, 0 }, 1539 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } }, 1540 & ifmt_ld_2, { 0x20c0 } 1541 }, 1542/* ld $dr,@($sr,$slo16) */ 1543 { 1544 { 0, 0, 0, 0 }, 1545 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } }, 1546 & ifmt_ld_d2, { 0xa0c00000 } 1547 }, 1548/* ldb $dr,@($sr) */ 1549 { 1550 { 0, 0, 0, 0 }, 1551 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } }, 1552 & ifmt_ldb_2, { 0x2080 } 1553 }, 1554/* ldb $dr,@($sr,$slo16) */ 1555 { 1556 { 0, 0, 0, 0 }, 1557 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } }, 1558 & ifmt_ldb_d2, { 0xa0800000 } 1559 }, 1560/* ldh $dr,@($sr) */ 1561 { 1562 { 0, 0, 0, 0 }, 1563 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } }, 1564 & ifmt_ldh_2, { 0x20a0 } 1565 }, 1566/* ldh $dr,@($sr,$slo16) */ 1567 { 1568 { 0, 0, 0, 0 }, 1569 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } }, 1570 & ifmt_ldh_d2, { 0xa0a00000 } 1571 }, 1572/* ldub $dr,@($sr) */ 1573 { 1574 { 0, 0, 0, 0 }, 1575 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } }, 1576 & ifmt_ldub_2, { 0x2090 } 1577 }, 1578/* ldub $dr,@($sr,$slo16) */ 1579 { 1580 { 0, 0, 0, 0 }, 1581 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } }, 1582 & ifmt_ldub_d2, { 0xa0900000 } 1583 }, 1584/* lduh $dr,@($sr) */ 1585 { 1586 { 0, 0, 0, 0 }, 1587 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } }, 1588 & ifmt_lduh_2, { 0x20b0 } 1589 }, 1590/* lduh $dr,@($sr,$slo16) */ 1591 { 1592 { 0, 0, 0, 0 }, 1593 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } }, 1594 & ifmt_lduh_d2, { 0xa0b00000 } 1595 }, 1596/* pop $dr */ 1597 { 1598 { 0, 0, 0, 0 }, 1599 { { MNEM, ' ', OP (DR), 0 } }, 1600 & ifmt_pop, { 0x20ef } 1601 }, 1602/* ldi $dr,$simm8 */ 1603 { 1604 { 0, 0, 0, 0 }, 1605 { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } }, 1606 & ifmt_ldi8a, { 0x6000 } 1607 }, 1608/* ldi $dr,$hash$slo16 */ 1609 { 1610 { 0, 0, 0, 0 }, 1611 { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } }, 1612 & ifmt_ldi16a, { 0x90f00000 } 1613 }, 1614/* rac $accd */ 1615 { 1616 { 0, 0, 0, 0 }, 1617 { { MNEM, ' ', OP (ACCD), 0 } }, 1618 & ifmt_rac_d, { 0x5090 } 1619 }, 1620/* rac $accd,$accs */ 1621 { 1622 { 0, 0, 0, 0 }, 1623 { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 } }, 1624 & ifmt_rac_ds, { 0x5090 } 1625 }, 1626/* rach $accd */ 1627 { 1628 { 0, 0, 0, 0 }, 1629 { { MNEM, ' ', OP (ACCD), 0 } }, 1630 & ifmt_rach_d, { 0x5080 } 1631 }, 1632/* rach $accd,$accs */ 1633 { 1634 { 0, 0, 0, 0 }, 1635 { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 } }, 1636 & ifmt_rach_ds, { 0x5080 } 1637 }, 1638/* st $src1,@($src2) */ 1639 { 1640 { 0, 0, 0, 0 }, 1641 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } }, 1642 & ifmt_st_2, { 0x2040 } 1643 }, 1644/* st $src1,@($src2,$slo16) */ 1645 { 1646 { 0, 0, 0, 0 }, 1647 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } }, 1648 & ifmt_st_d2, { 0xa0400000 } 1649 }, 1650/* stb $src1,@($src2) */ 1651 { 1652 { 0, 0, 0, 0 }, 1653 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } }, 1654 & ifmt_stb_2, { 0x2000 } 1655 }, 1656/* stb $src1,@($src2,$slo16) */ 1657 { 1658 { 0, 0, 0, 0 }, 1659 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } }, 1660 & ifmt_stb_d2, { 0xa0000000 } 1661 }, 1662/* sth $src1,@($src2) */ 1663 { 1664 { 0, 0, 0, 0 }, 1665 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } }, 1666 & ifmt_sth_2, { 0x2020 } 1667 }, 1668/* sth $src1,@($src2,$slo16) */ 1669 { 1670 { 0, 0, 0, 0 }, 1671 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } }, 1672 & ifmt_sth_d2, { 0xa0200000 } 1673 }, 1674/* push $src1 */ 1675 { 1676 { 0, 0, 0, 0 }, 1677 { { MNEM, ' ', OP (SRC1), 0 } }, 1678 & ifmt_push, { 0x207f } 1679 }, 1680}; 1681 1682#undef A 1683#undef OPERAND 1684#undef MNEM 1685#undef OP 1686 1687#ifndef CGEN_ASM_HASH_P 1688#define CGEN_ASM_HASH_P(insn) 1 1689#endif 1690 1691#ifndef CGEN_DIS_HASH_P 1692#define CGEN_DIS_HASH_P(insn) 1 1693#endif 1694 1695/* Return non-zero if INSN is to be added to the hash table. 1696 Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */ 1697 1698static int 1699asm_hash_insn_p (const CGEN_INSN *insn ATTRIBUTE_UNUSED) 1700{ 1701 return CGEN_ASM_HASH_P (insn); 1702} 1703 1704static int 1705dis_hash_insn_p (const CGEN_INSN *insn) 1706{ 1707 /* If building the hash table and the NO-DIS attribute is present, 1708 ignore. */ 1709 if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_NO_DIS)) 1710 return 0; 1711 return CGEN_DIS_HASH_P (insn); 1712} 1713 1714#ifndef CGEN_ASM_HASH 1715#define CGEN_ASM_HASH_SIZE 127 1716#ifdef CGEN_MNEMONIC_OPERANDS 1717#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) 1718#else 1719#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) /*FIXME*/ 1720#endif 1721#endif 1722 1723/* It doesn't make much sense to provide a default here, 1724 but while this is under development we do. 1725 BUFFER is a pointer to the bytes of the insn, target order. 1726 VALUE is the first base_insn_bitsize bits as an int in host order. */ 1727 1728#ifndef CGEN_DIS_HASH 1729#define CGEN_DIS_HASH_SIZE 256 1730#define CGEN_DIS_HASH(buf, value) (*(unsigned char *) (buf)) 1731#endif 1732 1733/* The result is the hash value of the insn. 1734 Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */ 1735 1736static unsigned int 1737asm_hash_insn (const char *mnem) 1738{ 1739 return CGEN_ASM_HASH (mnem); 1740} 1741 1742/* BUF is a pointer to the bytes of the insn, target order. 1743 VALUE is the first base_insn_bitsize bits as an int in host order. */ 1744 1745static unsigned int 1746dis_hash_insn (const char *buf ATTRIBUTE_UNUSED, 1747 CGEN_INSN_INT value ATTRIBUTE_UNUSED) 1748{ 1749 return CGEN_DIS_HASH (buf, value); 1750} 1751 1752/* Set the recorded length of the insn in the CGEN_FIELDS struct. */ 1753 1754static void 1755set_fields_bitsize (CGEN_FIELDS *fields, int size) 1756{ 1757 CGEN_FIELDS_BITSIZE (fields) = size; 1758} 1759 1760/* Function to call before using the operand instance table. 1761 This plugs the opcode entries and macro instructions into the cpu table. */ 1762 1763void 1764m32r_cgen_init_opcode_table (CGEN_CPU_DESC cd) 1765{ 1766 int i; 1767 int num_macros = (sizeof (m32r_cgen_macro_insn_table) / 1768 sizeof (m32r_cgen_macro_insn_table[0])); 1769 const CGEN_IBASE *ib = & m32r_cgen_macro_insn_table[0]; 1770 const CGEN_OPCODE *oc = & m32r_cgen_macro_insn_opcode_table[0]; 1771 CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN)); 1772 1773 /* This test has been added to avoid a warning generated 1774 if memset is called with a third argument of value zero. */ 1775 if (num_macros >= 1) 1776 memset (insns, 0, num_macros * sizeof (CGEN_INSN)); 1777 for (i = 0; i < num_macros; ++i) 1778 { 1779 insns[i].base = &ib[i]; 1780 insns[i].opcode = &oc[i]; 1781 m32r_cgen_build_insn_regex (& insns[i]); 1782 } 1783 cd->macro_insn_table.init_entries = insns; 1784 cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE); 1785 cd->macro_insn_table.num_init_entries = num_macros; 1786 1787 oc = & m32r_cgen_insn_opcode_table[0]; 1788 insns = (CGEN_INSN *) cd->insn_table.init_entries; 1789 for (i = 0; i < MAX_INSNS; ++i) 1790 { 1791 insns[i].opcode = &oc[i]; 1792 m32r_cgen_build_insn_regex (& insns[i]); 1793 } 1794 1795 cd->sizeof_fields = sizeof (CGEN_FIELDS); 1796 cd->set_fields_bitsize = set_fields_bitsize; 1797 1798 cd->asm_hash_p = asm_hash_insn_p; 1799 cd->asm_hash = asm_hash_insn; 1800 cd->asm_hash_size = CGEN_ASM_HASH_SIZE; 1801 1802 cd->dis_hash_p = dis_hash_insn_p; 1803 cd->dis_hash = dis_hash_insn; 1804 cd->dis_hash_size = CGEN_DIS_HASH_SIZE; 1805} 1806