15152Sdholmes/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */ 212485Sdholmes/* CPU data header for m32r. 35152Sdholmes 45152SdholmesTHIS FILE IS MACHINE GENERATED WITH CGEN. 55152Sdholmes 65152SdholmesCopyright (C) 1996-2022 Free Software Foundation, Inc. 75152Sdholmes 85152SdholmesThis file is part of the GNU Binutils and/or GDB, the GNU debugger. 95152Sdholmes 105152Sdholmes This file is free software; you can redistribute it and/or modify 115152Sdholmes it under the terms of the GNU General Public License as published by 125152Sdholmes the Free Software Foundation; either version 3, or (at your option) 135152Sdholmes any later version. 145152Sdholmes 155152Sdholmes It is distributed in the hope that it will be useful, but WITHOUT 165152Sdholmes ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 175152Sdholmes or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 185152Sdholmes License for more details. 195152Sdholmes 205152Sdholmes You should have received a copy of the GNU General Public License along 215152Sdholmes with this program; if not, write to the Free Software Foundation, Inc., 225152Sdholmes 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. 235152Sdholmes 247561Sehelin*/ 257561Sehelin 2612357Slmesnik#ifndef M32R_CPU_H 2710736Sctornqvi#define M32R_CPU_H 2810736Sctornqvi 2912357Slmesnik#ifdef __cplusplus 3010736Sctornqviextern "C" { 3110736Sctornqvi#endif 3210736Sctornqvi 3310736Sctornqvi#define CGEN_ARCH m32r 3410736Sctornqvi 3512357Slmesnik/* Given symbol S, return m32r_cgen_<S>. */ 3610736Sctornqvi#define CGEN_SYM(s) m32r##_cgen_##s 3710736Sctornqvi 3812357Slmesnik 3910736Sctornqvi/* Selected cpu families. */ 4010736Sctornqvi#define HAVE_CPU_M32RBF 4112947Sctornqvi#define HAVE_CPU_M32RXF 4210736Sctornqvi#define HAVE_CPU_M32R2F 4310736Sctornqvi 4410736Sctornqvi#define CGEN_INSN_LSB0_P 0 4510736Sctornqvi 467561Sehelin/* Minimum size of any insn (in bytes). */ 477876Sihse#define CGEN_MIN_INSN_SIZE 2 487876Sihse 497876Sihse/* Maximum size of any insn (in bytes). */ 5013194Siignatyev#define CGEN_MAX_INSN_SIZE 4 5113194Siignatyev 5213194Siignatyev#define CGEN_INT_INSN_P 1 5313194Siignatyev 5412934Sctornqvi/* Maximum number of syntax elements in an instruction. */ 5512408Skvn#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 15 567440Szmajo 577440Szmajo/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. 587440Szmajo e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands 5911707Stpivovarova we can't hash on everything up to the space. */ 6011707Stpivovarova#define CGEN_MNEMONIC_OPERANDS 6111707Stpivovarova 6211707Stpivovarova/* Maximum number of fields in an instruction. */ 6311707Stpivovarova#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 7 6411795Skvn 6511707Stpivovarova/* Enums. */ 6611707Stpivovarova 6711707Stpivovarova/* Enum declaration for insn format enums. */ 6811707Stpivovarovatypedef enum insn_op1 { 6910532Svlivanov OP1_0, OP1_1, OP1_2, OP1_3 7012934Sctornqvi , OP1_4, OP1_5, OP1_6, OP1_7 717440Szmajo , OP1_8, OP1_9, OP1_10, OP1_11 727440Szmajo , OP1_12, OP1_13, OP1_14, OP1_15 737088Szmajo} INSN_OP1; 747440Szmajo 757441Sthartmann/* Enum declaration for op2 enums. */ 767440Szmajotypedef enum insn_op2 { 777440Szmajo OP2_0, OP2_1, OP2_2, OP2_3 787196Skvn , OP2_4, OP2_5, OP2_6, OP2_7 797440Szmajo , OP2_8, OP2_9, OP2_10, OP2_11 807440Szmajo , OP2_12, OP2_13, OP2_14, OP2_15 817088Szmajo} INSN_OP2; 827440Szmajo 837440Szmajo/* Enum declaration for . */ 849811Stwistitypedef enum gr_names { 8511707Stpivovarova H_GR_FP = 13, H_GR_LR = 14, H_GR_SP = 15, H_GR_R0 = 0 8610532Svlivanov , H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3, H_GR_R4 = 4 8710532Svlivanov , H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7, H_GR_R8 = 8 8810532Svlivanov , H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11, H_GR_R12 = 12 8912934Sctornqvi , H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15 907440Szmajo} GR_NAMES; 917440Szmajo 927440Szmajo/* Enum declaration for . */ 937440Szmajotypedef enum cr_names { 9410003Szmajo H_CR_PSW = 0, H_CR_CBR = 1, H_CR_SPI = 2, H_CR_SPU = 3 957440Szmajo , H_CR_BPC = 6, H_CR_BBPSW = 8, H_CR_BBPC = 14, H_CR_EVB = 5 967440Szmajo , H_CR_CR0 = 0, H_CR_CR1 = 1, H_CR_CR2 = 2, H_CR_CR3 = 3 977440Szmajo , H_CR_CR4 = 4, H_CR_CR5 = 5, H_CR_CR6 = 6, H_CR_CR7 = 7 987440Szmajo , H_CR_CR8 = 8, H_CR_CR9 = 9, H_CR_CR10 = 10, H_CR_CR11 = 11 997440Szmajo , H_CR_CR12 = 12, H_CR_CR13 = 13, H_CR_CR14 = 14, H_CR_CR15 = 15 1007440Szmajo} CR_NAMES; 1017440Szmajo 10210347Szmajo/* Attributes. */ 1037440Szmajo 1047440Szmajo/* Enum declaration for machine type selection. */ 10511707Stpivovarovatypedef enum mach_attr { 10611707Stpivovarova MACH_BASE, MACH_M32R, MACH_M32RX, MACH_M32R2 10711707Stpivovarova , MACH_MAX 10811707Stpivovarova} MACH_ATTR; 1097088Szmajo 11012934Sctornqvi/* Enum declaration for instruction set selection. */ 1117932Sppunegovtypedef enum isa_attr { 1126733Smikael ISA_M32R, ISA_MAX 11312357Slmesnik} ISA_ATTR; 11412357Slmesnik 11512934Sctornqvi/* Enum declaration for parallel execution pipeline selection. */ 11612934Sctornqvitypedef enum pipe_attr { 11712934Sctornqvi PIPE_NONE, PIPE_O, PIPE_S, PIPE_OS 11812934Sctornqvi , PIPE_O_OS 11912357Slmesnik} PIPE_ATTR; 12012934Sctornqvi 12110721Sdfazunen/* Number of architecture variants. */ 12210721Sdfazunen#define MAX_ISAS 1 12312934Sctornqvi#define MAX_MACHS ((int) MACH_MAX) 1247564Sbrutisso 1257564Sbrutisso/* Ifield support. */ 12610721Sdfazunen 12711221Skzhaldyb/* Ifield attribute indices. */ 12810903Smchernov 12910721Sdfazunen/* Enum declaration for cgen_ifld attrs. */ 13010721Sdfazunentypedef enum cgen_ifld_attr { 1317564Sbrutisso CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED 1326733Smikael , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_RELOC, CGEN_IFLD_END_BOOLS 13312934Sctornqvi , CGEN_IFLD_START_NBOOLS = 31, CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS 1347628Sbrutisso} CGEN_IFLD_ATTR; 1357628Sbrutisso 13612934Sctornqvi/* Number of non-boolean elements in cgen_ifld_attr. */ 13713022Sehelin#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) 13813022Sehelin 13913022Sehelin/* cgen_ifld attribute accessor macros. */ 14013022Sehelin#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) 1417630Sbrutisso#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_VIRTUAL)) != 0) 14212934Sctornqvi#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) 14312207Sehelin#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_ABS_ADDR)) != 0) 14412207Sehelin#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RESERVED)) != 0) 14512207Sehelin#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGN_OPT)) != 0) 14612207Sehelin#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGNED)) != 0) 14712207Sehelin#define CGEN_ATTR_CGEN_IFLD_RELOC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RELOC)) != 0) 14812934Sctornqvi 1496877Sctornqvi/* Enum declaration for m32r ifield types. */ 15012048Sctornqvitypedef enum ifield_type { 15112048Sctornqvi M32R_F_NIL, M32R_F_ANYOF, M32R_F_OP1, M32R_F_OP2 15212048Sctornqvi , M32R_F_COND, M32R_F_R1, M32R_F_R2, M32R_F_SIMM8 15312048Sctornqvi , M32R_F_SIMM16, M32R_F_SHIFT_OP2, M32R_F_UIMM3, M32R_F_UIMM4 15412048Sctornqvi , M32R_F_UIMM5, M32R_F_UIMM8, M32R_F_UIMM16, M32R_F_UIMM24 15512048Sctornqvi , M32R_F_HI16, M32R_F_DISP8, M32R_F_DISP16, M32R_F_DISP24 15612048Sctornqvi , M32R_F_OP23, M32R_F_OP3, M32R_F_ACC, M32R_F_ACCS 1579086Sgtriantafill , M32R_F_ACCD, M32R_F_BITS67, M32R_F_BIT4, M32R_F_BIT14 15812908Sstuefe , M32R_F_IMM1, M32R_F_MAX 15912048Sctornqvi} IFIELD_TYPE; 16012048Sctornqvi 16112048Sctornqvi#define MAX_IFLD ((int) M32R_F_MAX) 1626877Sctornqvi 1636877Sctornqvi/* Hardware attribute indices. */ 16412048Sctornqvi 16512048Sctornqvi/* Enum declaration for cgen_hw attrs. */ 16612048Sctornqvitypedef enum cgen_hw_attr { 16712048Sctornqvi CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE 16812048Sctornqvi , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS 16912048Sctornqvi} CGEN_HW_ATTR; 17012180Scoleenp 17112048Sctornqvi/* Number of non-boolean elements in cgen_hw_attr. */ 17212048Sctornqvi#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) 17312048Sctornqvi 17412048Sctornqvi/* cgen_hw attribute accessor macros. */ 17510710Sddmitriev#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) 17610710Sddmitriev#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_VIRTUAL)) != 0) 17710710Sddmitriev#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_CACHE_ADDR)) != 0) 17810710Sddmitriev#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PC)) != 0) 17910710Sddmitriev#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PROFILE)) != 0) 18010710Sddmitriev 18110710Sddmitriev/* Enum declaration for m32r hardware types. */ 18210710Sddmitrievtypedef enum cgen_hw_type { 18310710Sddmitriev HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR 1846877Sctornqvi , HW_H_IADDR, HW_H_PC, HW_H_HI16, HW_H_SLO16 1856877Sctornqvi , HW_H_ULO16, HW_H_GR, HW_H_CR, HW_H_ACCUM 18612048Sctornqvi , HW_H_ACCUMS, HW_H_COND, HW_H_PSW, HW_H_BPSW 1877054Scoleenp , HW_H_BBPSW, HW_H_LOCK, HW_MAX 18812048Sctornqvi} CGEN_HW_TYPE; 18912048Sctornqvi 1908353Sctornqvi#define MAX_HW ((int) HW_MAX) 1917569Sfzhinkin 1926733Smikael/* Operand attribute indices. */ 19312932Smseledtsov 19412932Smseledtsov/* Enum declaration for cgen_operand attrs. */ 19512932Smseledtsovtypedef enum cgen_operand_attr { 19612932Smseledtsov CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT 19712932Smseledtsov , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY 19812934Sctornqvi , CGEN_OPERAND_RELOC, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH 1999958Smlarsson , CGEN_OPERAND_END_NBOOLS 2009958Smlarsson} CGEN_OPERAND_ATTR; 2016733Smikael 20212934Sctornqvi/* Number of non-boolean elements in cgen_operand_attr. */ 20313194Siignatyev#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) 20412934Sctornqvi 20512934Sctornqvi/* cgen_operand attribute accessor macros. */ 20612934Sctornqvi#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) 20712934Sctornqvi#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_VIRTUAL)) != 0) 20812934Sctornqvi#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) 20912934Sctornqvi#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) 21012934Sctornqvi#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) 21112934Sctornqvi#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGNED)) != 0) 21212934Sctornqvi#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_NEGATIVE)) != 0) 21312934Sctornqvi#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELAX)) != 0) 21412357Slmesnik#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) 21512934Sctornqvi#define CGEN_ATTR_CGEN_OPERAND_RELOC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELOC)) != 0) 21611564Sctornqvi 21711564Sctornqvi/* Enum declaration for m32r operand types. */ 21812048Sctornqvitypedef enum cgen_operand_type { 21912048Sctornqvi M32R_OPERAND_PC, M32R_OPERAND_SR, M32R_OPERAND_DR, M32R_OPERAND_SRC1 22012934Sctornqvi , M32R_OPERAND_SRC2, M32R_OPERAND_SCR, M32R_OPERAND_DCR, M32R_OPERAND_SIMM8 22112934Sctornqvi , M32R_OPERAND_SIMM16, M32R_OPERAND_UIMM3, M32R_OPERAND_UIMM4, M32R_OPERAND_UIMM5 22212934Sctornqvi , M32R_OPERAND_UIMM8, M32R_OPERAND_UIMM16, M32R_OPERAND_IMM1, M32R_OPERAND_ACCD 22312357Slmesnik , M32R_OPERAND_ACCS, M32R_OPERAND_ACC, M32R_OPERAND_HASH, M32R_OPERAND_HI16 22412934Sctornqvi , M32R_OPERAND_SLO16, M32R_OPERAND_ULO16, M32R_OPERAND_UIMM24, M32R_OPERAND_DISP8 22511564Sctornqvi , M32R_OPERAND_DISP16, M32R_OPERAND_DISP24, M32R_OPERAND_CONDBIT, M32R_OPERAND_ACCUM 22612934Sctornqvi , M32R_OPERAND_MAX 22712357Slmesnik} CGEN_OPERAND_TYPE; 22812934Sctornqvi 22912048Sctornqvi/* Number of operands types. */ 23012048Sctornqvi#define MAX_OPERANDS 28 23112934Sctornqvi 23212934Sctornqvi/* Maximum number of operands referenced by any insn. */ 23312934Sctornqvi#define MAX_OPERAND_INSTANCES 11 23412934Sctornqvi 2357283Svlivanov/* Insn attribute indices. */ 23611862Sctornqvi 23711862Sctornqvi/* Enum declaration for cgen_insn attrs. */ 23811862Sctornqvitypedef enum cgen_insn_attr { 23911862Sctornqvi CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI 24012947Sctornqvi , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED 241 , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_FILL_SLOT, CGEN_INSN_SPECIAL 242 , CGEN_INSN_SPECIAL_M32R, CGEN_INSN_SPECIAL_FLOAT, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31 243 , CGEN_INSN_MACH, CGEN_INSN_PIPE, CGEN_INSN_END_NBOOLS 244} CGEN_INSN_ATTR; 245 246/* Number of non-boolean elements in cgen_insn_attr. */ 247#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) 248 249/* cgen_insn attribute accessor macros. */ 250#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) 251#define CGEN_ATTR_CGEN_INSN_PIPE_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_PIPE-CGEN_INSN_START_NBOOLS-1].nonbitset) 252#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_ALIAS)) != 0) 253#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VIRTUAL)) != 0) 254#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_UNCOND_CTI)) != 0) 255#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_COND_CTI)) != 0) 256#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SKIP_CTI)) != 0) 257#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_DELAY_SLOT)) != 0) 258#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXABLE)) != 0) 259#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXED)) != 0) 260#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NO_DIS)) != 0) 261#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_PBB)) != 0) 262#define CGEN_ATTR_CGEN_INSN_FILL_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_FILL_SLOT)) != 0) 263#define CGEN_ATTR_CGEN_INSN_SPECIAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SPECIAL)) != 0) 264#define CGEN_ATTR_CGEN_INSN_SPECIAL_M32R_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SPECIAL_M32R)) != 0) 265#define CGEN_ATTR_CGEN_INSN_SPECIAL_FLOAT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SPECIAL_FLOAT)) != 0) 266 267/* cgen.h uses things we just defined. */ 268#include "opcode/cgen.h" 269 270extern const struct cgen_ifld m32r_cgen_ifld_table[]; 271 272/* Attributes. */ 273extern const CGEN_ATTR_TABLE m32r_cgen_hardware_attr_table[]; 274extern const CGEN_ATTR_TABLE m32r_cgen_ifield_attr_table[]; 275extern const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[]; 276extern const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[]; 277 278/* Hardware decls. */ 279 280extern CGEN_KEYWORD m32r_cgen_opval_gr_names; 281extern CGEN_KEYWORD m32r_cgen_opval_cr_names; 282extern CGEN_KEYWORD m32r_cgen_opval_h_accums; 283 284extern const CGEN_HW_ENTRY m32r_cgen_hw_table[]; 285 286 287 288 #ifdef __cplusplus 289 } 290 #endif 291 292#endif /* M32R_CPU_H */ 293