1/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */ 2/* CPU data for fr30. 3 4THIS FILE IS MACHINE GENERATED WITH CGEN. 5 6Copyright (C) 1996-2022 Free Software Foundation, Inc. 7 8This file is part of the GNU Binutils and/or GDB, the GNU debugger. 9 10 This file is free software; you can redistribute it and/or modify 11 it under the terms of the GNU General Public License as published by 12 the Free Software Foundation; either version 3, or (at your option) 13 any later version. 14 15 It is distributed in the hope that it will be useful, but WITHOUT 16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 18 License for more details. 19 20 You should have received a copy of the GNU General Public License along 21 with this program; if not, write to the Free Software Foundation, Inc., 22 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. 23 24*/ 25 26#include "sysdep.h" 27#include <stdio.h> 28#include <stdarg.h> 29#include <stdlib.h> 30#include "ansidecl.h" 31#include "bfd.h" 32#include "symcat.h" 33#include "fr30-desc.h" 34#include "fr30-opc.h" 35#include "opintl.h" 36#include "libiberty.h" 37#include "xregex.h" 38 39/* Attributes. */ 40 41static const CGEN_ATTR_ENTRY bool_attr[] = 42{ 43 { "#f", 0 }, 44 { "#t", 1 }, 45 { 0, 0 } 46}; 47 48static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED = 49{ 50 { "base", MACH_BASE }, 51 { "fr30", MACH_FR30 }, 52 { "max", MACH_MAX }, 53 { 0, 0 } 54}; 55 56static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED = 57{ 58 { "fr30", ISA_FR30 }, 59 { "max", ISA_MAX }, 60 { 0, 0 } 61}; 62 63const CGEN_ATTR_TABLE fr30_cgen_ifield_attr_table[] = 64{ 65 { "MACH", & MACH_attr[0], & MACH_attr[0] }, 66 { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, 67 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, 68 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, 69 { "RESERVED", &bool_attr[0], &bool_attr[0] }, 70 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, 71 { "SIGNED", &bool_attr[0], &bool_attr[0] }, 72 { 0, 0, 0 } 73}; 74 75const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[] = 76{ 77 { "MACH", & MACH_attr[0], & MACH_attr[0] }, 78 { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, 79 { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] }, 80 { "PC", &bool_attr[0], &bool_attr[0] }, 81 { "PROFILE", &bool_attr[0], &bool_attr[0] }, 82 { 0, 0, 0 } 83}; 84 85const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[] = 86{ 87 { "MACH", & MACH_attr[0], & MACH_attr[0] }, 88 { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, 89 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, 90 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, 91 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, 92 { "SIGNED", &bool_attr[0], &bool_attr[0] }, 93 { "NEGATIVE", &bool_attr[0], &bool_attr[0] }, 94 { "RELAX", &bool_attr[0], &bool_attr[0] }, 95 { "SEM-ONLY", &bool_attr[0], &bool_attr[0] }, 96 { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] }, 97 { 0, 0, 0 } 98}; 99 100const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[] = 101{ 102 { "MACH", & MACH_attr[0], & MACH_attr[0] }, 103 { "ALIAS", &bool_attr[0], &bool_attr[0] }, 104 { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, 105 { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] }, 106 { "COND-CTI", &bool_attr[0], &bool_attr[0] }, 107 { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, 108 { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, 109 { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, 110 { "RELAXED", &bool_attr[0], &bool_attr[0] }, 111 { "NO-DIS", &bool_attr[0], &bool_attr[0] }, 112 { "PBB", &bool_attr[0], &bool_attr[0] }, 113 { "NOT-IN-DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, 114 { 0, 0, 0 } 115}; 116 117/* Instruction set variants. */ 118 119static const CGEN_ISA fr30_cgen_isa_table[] = { 120 { "fr30", 16, 16, 16, 48 }, 121 { 0, 0, 0, 0, 0 } 122}; 123 124/* Machine variants. */ 125 126static const CGEN_MACH fr30_cgen_mach_table[] = { 127 { "fr30", "fr30", MACH_FR30, 0 }, 128 { 0, 0, 0, 0 } 129}; 130 131static CGEN_KEYWORD_ENTRY fr30_cgen_opval_gr_names_entries[] = 132{ 133 { "r0", 0, {0, {{{0, 0}}}}, 0, 0 }, 134 { "r1", 1, {0, {{{0, 0}}}}, 0, 0 }, 135 { "r2", 2, {0, {{{0, 0}}}}, 0, 0 }, 136 { "r3", 3, {0, {{{0, 0}}}}, 0, 0 }, 137 { "r4", 4, {0, {{{0, 0}}}}, 0, 0 }, 138 { "r5", 5, {0, {{{0, 0}}}}, 0, 0 }, 139 { "r6", 6, {0, {{{0, 0}}}}, 0, 0 }, 140 { "r7", 7, {0, {{{0, 0}}}}, 0, 0 }, 141 { "r8", 8, {0, {{{0, 0}}}}, 0, 0 }, 142 { "r9", 9, {0, {{{0, 0}}}}, 0, 0 }, 143 { "r10", 10, {0, {{{0, 0}}}}, 0, 0 }, 144 { "r11", 11, {0, {{{0, 0}}}}, 0, 0 }, 145 { "r12", 12, {0, {{{0, 0}}}}, 0, 0 }, 146 { "r13", 13, {0, {{{0, 0}}}}, 0, 0 }, 147 { "r14", 14, {0, {{{0, 0}}}}, 0, 0 }, 148 { "r15", 15, {0, {{{0, 0}}}}, 0, 0 }, 149 { "ac", 13, {0, {{{0, 0}}}}, 0, 0 }, 150 { "fp", 14, {0, {{{0, 0}}}}, 0, 0 }, 151 { "sp", 15, {0, {{{0, 0}}}}, 0, 0 } 152}; 153 154CGEN_KEYWORD fr30_cgen_opval_gr_names = 155{ 156 & fr30_cgen_opval_gr_names_entries[0], 157 19, 158 0, 0, 0, 0, "" 159}; 160 161static CGEN_KEYWORD_ENTRY fr30_cgen_opval_cr_names_entries[] = 162{ 163 { "cr0", 0, {0, {{{0, 0}}}}, 0, 0 }, 164 { "cr1", 1, {0, {{{0, 0}}}}, 0, 0 }, 165 { "cr2", 2, {0, {{{0, 0}}}}, 0, 0 }, 166 { "cr3", 3, {0, {{{0, 0}}}}, 0, 0 }, 167 { "cr4", 4, {0, {{{0, 0}}}}, 0, 0 }, 168 { "cr5", 5, {0, {{{0, 0}}}}, 0, 0 }, 169 { "cr6", 6, {0, {{{0, 0}}}}, 0, 0 }, 170 { "cr7", 7, {0, {{{0, 0}}}}, 0, 0 }, 171 { "cr8", 8, {0, {{{0, 0}}}}, 0, 0 }, 172 { "cr9", 9, {0, {{{0, 0}}}}, 0, 0 }, 173 { "cr10", 10, {0, {{{0, 0}}}}, 0, 0 }, 174 { "cr11", 11, {0, {{{0, 0}}}}, 0, 0 }, 175 { "cr12", 12, {0, {{{0, 0}}}}, 0, 0 }, 176 { "cr13", 13, {0, {{{0, 0}}}}, 0, 0 }, 177 { "cr14", 14, {0, {{{0, 0}}}}, 0, 0 }, 178 { "cr15", 15, {0, {{{0, 0}}}}, 0, 0 } 179}; 180 181CGEN_KEYWORD fr30_cgen_opval_cr_names = 182{ 183 & fr30_cgen_opval_cr_names_entries[0], 184 16, 185 0, 0, 0, 0, "" 186}; 187 188static CGEN_KEYWORD_ENTRY fr30_cgen_opval_dr_names_entries[] = 189{ 190 { "tbr", 0, {0, {{{0, 0}}}}, 0, 0 }, 191 { "rp", 1, {0, {{{0, 0}}}}, 0, 0 }, 192 { "ssp", 2, {0, {{{0, 0}}}}, 0, 0 }, 193 { "usp", 3, {0, {{{0, 0}}}}, 0, 0 }, 194 { "mdh", 4, {0, {{{0, 0}}}}, 0, 0 }, 195 { "mdl", 5, {0, {{{0, 0}}}}, 0, 0 } 196}; 197 198CGEN_KEYWORD fr30_cgen_opval_dr_names = 199{ 200 & fr30_cgen_opval_dr_names_entries[0], 201 6, 202 0, 0, 0, 0, "" 203}; 204 205static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_ps_entries[] = 206{ 207 { "ps", 0, {0, {{{0, 0}}}}, 0, 0 } 208}; 209 210CGEN_KEYWORD fr30_cgen_opval_h_ps = 211{ 212 & fr30_cgen_opval_h_ps_entries[0], 213 1, 214 0, 0, 0, 0, "" 215}; 216 217static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r13_entries[] = 218{ 219 { "r13", 0, {0, {{{0, 0}}}}, 0, 0 } 220}; 221 222CGEN_KEYWORD fr30_cgen_opval_h_r13 = 223{ 224 & fr30_cgen_opval_h_r13_entries[0], 225 1, 226 0, 0, 0, 0, "" 227}; 228 229static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r14_entries[] = 230{ 231 { "r14", 0, {0, {{{0, 0}}}}, 0, 0 } 232}; 233 234CGEN_KEYWORD fr30_cgen_opval_h_r14 = 235{ 236 & fr30_cgen_opval_h_r14_entries[0], 237 1, 238 0, 0, 0, 0, "" 239}; 240 241static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r15_entries[] = 242{ 243 { "r15", 0, {0, {{{0, 0}}}}, 0, 0 } 244}; 245 246CGEN_KEYWORD fr30_cgen_opval_h_r15 = 247{ 248 & fr30_cgen_opval_h_r15_entries[0], 249 1, 250 0, 0, 0, 0, "" 251}; 252 253 254/* The hardware table. */ 255 256#define A(a) (1 << CGEN_HW_##a) 257 258const CGEN_HW_ENTRY fr30_cgen_hw_table[] = 259{ 260 { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 261 { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 262 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 263 { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 264 { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 265 { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } }, 266 { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, & fr30_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } }, 267 { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, & fr30_cgen_opval_cr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 268 { "h-dr", HW_H_DR, CGEN_ASM_KEYWORD, & fr30_cgen_opval_dr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 269 { "h-ps", HW_H_PS, CGEN_ASM_KEYWORD, & fr30_cgen_opval_h_ps, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 270 { "h-r13", HW_H_R13, CGEN_ASM_KEYWORD, & fr30_cgen_opval_h_r13, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 271 { "h-r14", HW_H_R14, CGEN_ASM_KEYWORD, & fr30_cgen_opval_h_r14, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 272 { "h-r15", HW_H_R15, CGEN_ASM_KEYWORD, & fr30_cgen_opval_h_r15, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 273 { "h-nbit", HW_H_NBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 274 { "h-zbit", HW_H_ZBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 275 { "h-vbit", HW_H_VBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 276 { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 277 { "h-ibit", HW_H_IBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 278 { "h-sbit", HW_H_SBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 279 { "h-tbit", HW_H_TBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 280 { "h-d0bit", HW_H_D0BIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 281 { "h-d1bit", HW_H_D1BIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 282 { "h-ccr", HW_H_CCR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 283 { "h-scr", HW_H_SCR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 284 { "h-ilm", HW_H_ILM, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 285 { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } } 286}; 287 288#undef A 289 290 291/* The instruction field table. */ 292 293#define A(a) (1 << CGEN_IFLD_##a) 294 295const CGEN_IFLD fr30_cgen_ifld_table[] = 296{ 297 { FR30_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 298 { FR30_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 299 { FR30_F_OP1, "f-op1", 0, 16, 0, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 300 { FR30_F_OP2, "f-op2", 0, 16, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 301 { FR30_F_OP3, "f-op3", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 302 { FR30_F_OP4, "f-op4", 0, 16, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 303 { FR30_F_OP5, "f-op5", 0, 16, 4, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 304 { FR30_F_CC, "f-cc", 0, 16, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 305 { FR30_F_CCC, "f-ccc", 16, 16, 0, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 306 { FR30_F_RJ, "f-Rj", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 307 { FR30_F_RI, "f-Ri", 0, 16, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 308 { FR30_F_RS1, "f-Rs1", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 309 { FR30_F_RS2, "f-Rs2", 0, 16, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 310 { FR30_F_RJC, "f-Rjc", 16, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 311 { FR30_F_RIC, "f-Ric", 16, 16, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 312 { FR30_F_CRJ, "f-CRj", 16, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 313 { FR30_F_CRI, "f-CRi", 16, 16, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 314 { FR30_F_U4, "f-u4", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 315 { FR30_F_U4C, "f-u4c", 0, 16, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 316 { FR30_F_I4, "f-i4", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 317 { FR30_F_M4, "f-m4", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 318 { FR30_F_U8, "f-u8", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 319 { FR30_F_I8, "f-i8", 0, 16, 4, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 320 { FR30_F_I20_4, "f-i20-4", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 321 { FR30_F_I20_16, "f-i20-16", 16, 16, 0, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 322 { FR30_F_I20, "f-i20", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, 323 { FR30_F_I32, "f-i32", 16, 32, 0, 32, { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } }, 324 { FR30_F_UDISP6, "f-udisp6", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 325 { FR30_F_DISP8, "f-disp8", 0, 16, 4, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 326 { FR30_F_DISP9, "f-disp9", 0, 16, 4, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 327 { FR30_F_DISP10, "f-disp10", 0, 16, 4, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 328 { FR30_F_S10, "f-s10", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 329 { FR30_F_U10, "f-u10", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 330 { FR30_F_REL9, "f-rel9", 0, 16, 8, 8, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, 331 { FR30_F_DIR8, "f-dir8", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 332 { FR30_F_DIR9, "f-dir9", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 333 { FR30_F_DIR10, "f-dir10", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 334 { FR30_F_REL12, "f-rel12", 0, 16, 5, 11, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, 335 { FR30_F_REGLIST_HI_ST, "f-reglist_hi_st", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 336 { FR30_F_REGLIST_LOW_ST, "f-reglist_low_st", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 337 { FR30_F_REGLIST_HI_LD, "f-reglist_hi_ld", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 338 { FR30_F_REGLIST_LOW_LD, "f-reglist_low_ld", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 339 { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } } 340}; 341 342#undef A 343 344 345 346/* multi ifield declarations */ 347 348const CGEN_MAYBE_MULTI_IFLD FR30_F_I20_MULTI_IFIELD []; 349 350 351/* multi ifield definitions */ 352 353const CGEN_MAYBE_MULTI_IFLD FR30_F_I20_MULTI_IFIELD [] = 354{ 355 { 0, { &fr30_cgen_ifld_table[FR30_F_I20_4] } }, 356 { 0, { &fr30_cgen_ifld_table[FR30_F_I20_16] } }, 357 { 0, { 0 } } 358}; 359 360/* The operand table. */ 361 362#define A(a) (1 << CGEN_OPERAND_##a) 363#define OPERAND(op) FR30_OPERAND_##op 364 365const CGEN_OPERAND fr30_cgen_operand_table[] = 366{ 367/* pc: program counter */ 368 { "pc", FR30_OPERAND_PC, HW_H_PC, 0, 0, 369 { 0, { &fr30_cgen_ifld_table[FR30_F_NIL] } }, 370 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, 371/* Ri: destination register */ 372 { "Ri", FR30_OPERAND_RI, HW_H_GR, 12, 4, 373 { 0, { &fr30_cgen_ifld_table[FR30_F_RI] } }, 374 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 375/* Rj: source register */ 376 { "Rj", FR30_OPERAND_RJ, HW_H_GR, 8, 4, 377 { 0, { &fr30_cgen_ifld_table[FR30_F_RJ] } }, 378 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 379/* Ric: target register coproc insn */ 380 { "Ric", FR30_OPERAND_RIC, HW_H_GR, 12, 4, 381 { 0, { &fr30_cgen_ifld_table[FR30_F_RIC] } }, 382 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 383/* Rjc: source register coproc insn */ 384 { "Rjc", FR30_OPERAND_RJC, HW_H_GR, 8, 4, 385 { 0, { &fr30_cgen_ifld_table[FR30_F_RJC] } }, 386 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 387/* CRi: coprocessor register */ 388 { "CRi", FR30_OPERAND_CRI, HW_H_CR, 12, 4, 389 { 0, { &fr30_cgen_ifld_table[FR30_F_CRI] } }, 390 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 391/* CRj: coprocessor register */ 392 { "CRj", FR30_OPERAND_CRJ, HW_H_CR, 8, 4, 393 { 0, { &fr30_cgen_ifld_table[FR30_F_CRJ] } }, 394 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 395/* Rs1: dedicated register */ 396 { "Rs1", FR30_OPERAND_RS1, HW_H_DR, 8, 4, 397 { 0, { &fr30_cgen_ifld_table[FR30_F_RS1] } }, 398 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 399/* Rs2: dedicated register */ 400 { "Rs2", FR30_OPERAND_RS2, HW_H_DR, 12, 4, 401 { 0, { &fr30_cgen_ifld_table[FR30_F_RS2] } }, 402 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 403/* R13: General Register 13 */ 404 { "R13", FR30_OPERAND_R13, HW_H_R13, 0, 0, 405 { 0, { 0 } }, 406 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 407/* R14: General Register 14 */ 408 { "R14", FR30_OPERAND_R14, HW_H_R14, 0, 0, 409 { 0, { 0 } }, 410 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 411/* R15: General Register 15 */ 412 { "R15", FR30_OPERAND_R15, HW_H_R15, 0, 0, 413 { 0, { 0 } }, 414 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 415/* ps: Program Status register */ 416 { "ps", FR30_OPERAND_PS, HW_H_PS, 0, 0, 417 { 0, { 0 } }, 418 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 419/* u4: 4 bit unsigned immediate */ 420 { "u4", FR30_OPERAND_U4, HW_H_UINT, 8, 4, 421 { 0, { &fr30_cgen_ifld_table[FR30_F_U4] } }, 422 { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, 423/* u4c: 4 bit unsigned immediate */ 424 { "u4c", FR30_OPERAND_U4C, HW_H_UINT, 12, 4, 425 { 0, { &fr30_cgen_ifld_table[FR30_F_U4C] } }, 426 { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, 427/* u8: 8 bit unsigned immediate */ 428 { "u8", FR30_OPERAND_U8, HW_H_UINT, 8, 8, 429 { 0, { &fr30_cgen_ifld_table[FR30_F_U8] } }, 430 { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, 431/* i8: 8 bit unsigned immediate */ 432 { "i8", FR30_OPERAND_I8, HW_H_UINT, 4, 8, 433 { 0, { &fr30_cgen_ifld_table[FR30_F_I8] } }, 434 { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, 435/* udisp6: 6 bit unsigned immediate */ 436 { "udisp6", FR30_OPERAND_UDISP6, HW_H_UINT, 8, 4, 437 { 0, { &fr30_cgen_ifld_table[FR30_F_UDISP6] } }, 438 { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, 439/* disp8: 8 bit signed immediate */ 440 { "disp8", FR30_OPERAND_DISP8, HW_H_SINT, 4, 8, 441 { 0, { &fr30_cgen_ifld_table[FR30_F_DISP8] } }, 442 { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, 443/* disp9: 9 bit signed immediate */ 444 { "disp9", FR30_OPERAND_DISP9, HW_H_SINT, 4, 8, 445 { 0, { &fr30_cgen_ifld_table[FR30_F_DISP9] } }, 446 { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, 447/* disp10: 10 bit signed immediate */ 448 { "disp10", FR30_OPERAND_DISP10, HW_H_SINT, 4, 8, 449 { 0, { &fr30_cgen_ifld_table[FR30_F_DISP10] } }, 450 { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, 451/* s10: 10 bit signed immediate */ 452 { "s10", FR30_OPERAND_S10, HW_H_SINT, 8, 8, 453 { 0, { &fr30_cgen_ifld_table[FR30_F_S10] } }, 454 { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, 455/* u10: 10 bit unsigned immediate */ 456 { "u10", FR30_OPERAND_U10, HW_H_UINT, 8, 8, 457 { 0, { &fr30_cgen_ifld_table[FR30_F_U10] } }, 458 { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, 459/* i32: 32 bit immediate */ 460 { "i32", FR30_OPERAND_I32, HW_H_UINT, 0, 32, 461 { 0, { &fr30_cgen_ifld_table[FR30_F_I32] } }, 462 { 0|A(HASH_PREFIX)|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } }, 463/* m4: 4 bit negative immediate */ 464 { "m4", FR30_OPERAND_M4, HW_H_SINT, 8, 4, 465 { 0, { &fr30_cgen_ifld_table[FR30_F_M4] } }, 466 { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, 467/* i20: 20 bit immediate */ 468 { "i20", FR30_OPERAND_I20, HW_H_UINT, 0, 20, 469 { 2, { &FR30_F_I20_MULTI_IFIELD[0] } }, 470 { 0|A(HASH_PREFIX)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, 471/* dir8: 8 bit direct address */ 472 { "dir8", FR30_OPERAND_DIR8, HW_H_UINT, 8, 8, 473 { 0, { &fr30_cgen_ifld_table[FR30_F_DIR8] } }, 474 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 475/* dir9: 9 bit direct address */ 476 { "dir9", FR30_OPERAND_DIR9, HW_H_UINT, 8, 8, 477 { 0, { &fr30_cgen_ifld_table[FR30_F_DIR9] } }, 478 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 479/* dir10: 10 bit direct address */ 480 { "dir10", FR30_OPERAND_DIR10, HW_H_UINT, 8, 8, 481 { 0, { &fr30_cgen_ifld_table[FR30_F_DIR10] } }, 482 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 483/* label9: 9 bit pc relative address */ 484 { "label9", FR30_OPERAND_LABEL9, HW_H_IADDR, 8, 8, 485 { 0, { &fr30_cgen_ifld_table[FR30_F_REL9] } }, 486 { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, 487/* label12: 12 bit pc relative address */ 488 { "label12", FR30_OPERAND_LABEL12, HW_H_IADDR, 5, 11, 489 { 0, { &fr30_cgen_ifld_table[FR30_F_REL12] } }, 490 { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, 491/* reglist_low_ld: 8 bit low register mask for ldm */ 492 { "reglist_low_ld", FR30_OPERAND_REGLIST_LOW_LD, HW_H_UINT, 8, 8, 493 { 0, { &fr30_cgen_ifld_table[FR30_F_REGLIST_LOW_LD] } }, 494 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 495/* reglist_hi_ld: 8 bit high register mask for ldm */ 496 { "reglist_hi_ld", FR30_OPERAND_REGLIST_HI_LD, HW_H_UINT, 8, 8, 497 { 0, { &fr30_cgen_ifld_table[FR30_F_REGLIST_HI_LD] } }, 498 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 499/* reglist_low_st: 8 bit low register mask for stm */ 500 { "reglist_low_st", FR30_OPERAND_REGLIST_LOW_ST, HW_H_UINT, 8, 8, 501 { 0, { &fr30_cgen_ifld_table[FR30_F_REGLIST_LOW_ST] } }, 502 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 503/* reglist_hi_st: 8 bit high register mask for stm */ 504 { "reglist_hi_st", FR30_OPERAND_REGLIST_HI_ST, HW_H_UINT, 8, 8, 505 { 0, { &fr30_cgen_ifld_table[FR30_F_REGLIST_HI_ST] } }, 506 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 507/* cc: condition codes */ 508 { "cc", FR30_OPERAND_CC, HW_H_UINT, 4, 4, 509 { 0, { &fr30_cgen_ifld_table[FR30_F_CC] } }, 510 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 511/* ccc: coprocessor calc */ 512 { "ccc", FR30_OPERAND_CCC, HW_H_UINT, 0, 8, 513 { 0, { &fr30_cgen_ifld_table[FR30_F_CCC] } }, 514 { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, 515/* nbit: negative bit */ 516 { "nbit", FR30_OPERAND_NBIT, HW_H_NBIT, 0, 0, 517 { 0, { 0 } }, 518 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, 519/* vbit: overflow bit */ 520 { "vbit", FR30_OPERAND_VBIT, HW_H_VBIT, 0, 0, 521 { 0, { 0 } }, 522 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, 523/* zbit: zero bit */ 524 { "zbit", FR30_OPERAND_ZBIT, HW_H_ZBIT, 0, 0, 525 { 0, { 0 } }, 526 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, 527/* cbit: carry bit */ 528 { "cbit", FR30_OPERAND_CBIT, HW_H_CBIT, 0, 0, 529 { 0, { 0 } }, 530 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, 531/* ibit: interrupt bit */ 532 { "ibit", FR30_OPERAND_IBIT, HW_H_IBIT, 0, 0, 533 { 0, { 0 } }, 534 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, 535/* sbit: stack bit */ 536 { "sbit", FR30_OPERAND_SBIT, HW_H_SBIT, 0, 0, 537 { 0, { 0 } }, 538 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, 539/* tbit: trace trap bit */ 540 { "tbit", FR30_OPERAND_TBIT, HW_H_TBIT, 0, 0, 541 { 0, { 0 } }, 542 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, 543/* d0bit: division 0 bit */ 544 { "d0bit", FR30_OPERAND_D0BIT, HW_H_D0BIT, 0, 0, 545 { 0, { 0 } }, 546 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, 547/* d1bit: division 1 bit */ 548 { "d1bit", FR30_OPERAND_D1BIT, HW_H_D1BIT, 0, 0, 549 { 0, { 0 } }, 550 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, 551/* ccr: condition code bits */ 552 { "ccr", FR30_OPERAND_CCR, HW_H_CCR, 0, 0, 553 { 0, { 0 } }, 554 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, 555/* scr: system condition bits */ 556 { "scr", FR30_OPERAND_SCR, HW_H_SCR, 0, 0, 557 { 0, { 0 } }, 558 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, 559/* ilm: interrupt level mask */ 560 { "ilm", FR30_OPERAND_ILM, HW_H_ILM, 0, 0, 561 { 0, { 0 } }, 562 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, 563/* sentinel */ 564 { 0, 0, 0, 0, 0, 565 { 0, { 0 } }, 566 { 0, { { { (1<<MACH_BASE), 0 } } } } } 567}; 568 569#undef A 570 571 572/* The instruction table. */ 573 574#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) 575#define A(a) (1 << CGEN_INSN_##a) 576 577static const CGEN_IBASE fr30_cgen_insn_table[MAX_INSNS] = 578{ 579 /* Special null first entry. 580 A `num' value of zero is thus invalid. 581 Also, the special `invalid' insn resides here. */ 582 { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 583/* add $Rj,$Ri */ 584 { 585 FR30_INSN_ADD, "add", "add", 16, 586 { 0, { { { (1<<MACH_BASE), 0 } } } } 587 }, 588/* add $u4,$Ri */ 589 { 590 FR30_INSN_ADDI, "addi", "add", 16, 591 { 0, { { { (1<<MACH_BASE), 0 } } } } 592 }, 593/* add2 $m4,$Ri */ 594 { 595 FR30_INSN_ADD2, "add2", "add2", 16, 596 { 0, { { { (1<<MACH_BASE), 0 } } } } 597 }, 598/* addc $Rj,$Ri */ 599 { 600 FR30_INSN_ADDC, "addc", "addc", 16, 601 { 0, { { { (1<<MACH_BASE), 0 } } } } 602 }, 603/* addn $Rj,$Ri */ 604 { 605 FR30_INSN_ADDN, "addn", "addn", 16, 606 { 0, { { { (1<<MACH_BASE), 0 } } } } 607 }, 608/* addn $u4,$Ri */ 609 { 610 FR30_INSN_ADDNI, "addni", "addn", 16, 611 { 0, { { { (1<<MACH_BASE), 0 } } } } 612 }, 613/* addn2 $m4,$Ri */ 614 { 615 FR30_INSN_ADDN2, "addn2", "addn2", 16, 616 { 0, { { { (1<<MACH_BASE), 0 } } } } 617 }, 618/* sub $Rj,$Ri */ 619 { 620 FR30_INSN_SUB, "sub", "sub", 16, 621 { 0, { { { (1<<MACH_BASE), 0 } } } } 622 }, 623/* subc $Rj,$Ri */ 624 { 625 FR30_INSN_SUBC, "subc", "subc", 16, 626 { 0, { { { (1<<MACH_BASE), 0 } } } } 627 }, 628/* subn $Rj,$Ri */ 629 { 630 FR30_INSN_SUBN, "subn", "subn", 16, 631 { 0, { { { (1<<MACH_BASE), 0 } } } } 632 }, 633/* cmp $Rj,$Ri */ 634 { 635 FR30_INSN_CMP, "cmp", "cmp", 16, 636 { 0, { { { (1<<MACH_BASE), 0 } } } } 637 }, 638/* cmp $u4,$Ri */ 639 { 640 FR30_INSN_CMPI, "cmpi", "cmp", 16, 641 { 0, { { { (1<<MACH_BASE), 0 } } } } 642 }, 643/* cmp2 $m4,$Ri */ 644 { 645 FR30_INSN_CMP2, "cmp2", "cmp2", 16, 646 { 0, { { { (1<<MACH_BASE), 0 } } } } 647 }, 648/* and $Rj,$Ri */ 649 { 650 FR30_INSN_AND, "and", "and", 16, 651 { 0, { { { (1<<MACH_BASE), 0 } } } } 652 }, 653/* or $Rj,$Ri */ 654 { 655 FR30_INSN_OR, "or", "or", 16, 656 { 0, { { { (1<<MACH_BASE), 0 } } } } 657 }, 658/* eor $Rj,$Ri */ 659 { 660 FR30_INSN_EOR, "eor", "eor", 16, 661 { 0, { { { (1<<MACH_BASE), 0 } } } } 662 }, 663/* and $Rj,@$Ri */ 664 { 665 FR30_INSN_ANDM, "andm", "and", 16, 666 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 667 }, 668/* andh $Rj,@$Ri */ 669 { 670 FR30_INSN_ANDH, "andh", "andh", 16, 671 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 672 }, 673/* andb $Rj,@$Ri */ 674 { 675 FR30_INSN_ANDB, "andb", "andb", 16, 676 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 677 }, 678/* or $Rj,@$Ri */ 679 { 680 FR30_INSN_ORM, "orm", "or", 16, 681 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 682 }, 683/* orh $Rj,@$Ri */ 684 { 685 FR30_INSN_ORH, "orh", "orh", 16, 686 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 687 }, 688/* orb $Rj,@$Ri */ 689 { 690 FR30_INSN_ORB, "orb", "orb", 16, 691 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 692 }, 693/* eor $Rj,@$Ri */ 694 { 695 FR30_INSN_EORM, "eorm", "eor", 16, 696 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 697 }, 698/* eorh $Rj,@$Ri */ 699 { 700 FR30_INSN_EORH, "eorh", "eorh", 16, 701 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 702 }, 703/* eorb $Rj,@$Ri */ 704 { 705 FR30_INSN_EORB, "eorb", "eorb", 16, 706 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 707 }, 708/* bandl $u4,@$Ri */ 709 { 710 FR30_INSN_BANDL, "bandl", "bandl", 16, 711 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 712 }, 713/* borl $u4,@$Ri */ 714 { 715 FR30_INSN_BORL, "borl", "borl", 16, 716 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 717 }, 718/* beorl $u4,@$Ri */ 719 { 720 FR30_INSN_BEORL, "beorl", "beorl", 16, 721 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 722 }, 723/* bandh $u4,@$Ri */ 724 { 725 FR30_INSN_BANDH, "bandh", "bandh", 16, 726 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 727 }, 728/* borh $u4,@$Ri */ 729 { 730 FR30_INSN_BORH, "borh", "borh", 16, 731 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 732 }, 733/* beorh $u4,@$Ri */ 734 { 735 FR30_INSN_BEORH, "beorh", "beorh", 16, 736 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 737 }, 738/* btstl $u4,@$Ri */ 739 { 740 FR30_INSN_BTSTL, "btstl", "btstl", 16, 741 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 742 }, 743/* btsth $u4,@$Ri */ 744 { 745 FR30_INSN_BTSTH, "btsth", "btsth", 16, 746 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 747 }, 748/* mul $Rj,$Ri */ 749 { 750 FR30_INSN_MUL, "mul", "mul", 16, 751 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 752 }, 753/* mulu $Rj,$Ri */ 754 { 755 FR30_INSN_MULU, "mulu", "mulu", 16, 756 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 757 }, 758/* mulh $Rj,$Ri */ 759 { 760 FR30_INSN_MULH, "mulh", "mulh", 16, 761 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 762 }, 763/* muluh $Rj,$Ri */ 764 { 765 FR30_INSN_MULUH, "muluh", "muluh", 16, 766 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 767 }, 768/* div0s $Ri */ 769 { 770 FR30_INSN_DIV0S, "div0s", "div0s", 16, 771 { 0, { { { (1<<MACH_BASE), 0 } } } } 772 }, 773/* div0u $Ri */ 774 { 775 FR30_INSN_DIV0U, "div0u", "div0u", 16, 776 { 0, { { { (1<<MACH_BASE), 0 } } } } 777 }, 778/* div1 $Ri */ 779 { 780 FR30_INSN_DIV1, "div1", "div1", 16, 781 { 0, { { { (1<<MACH_BASE), 0 } } } } 782 }, 783/* div2 $Ri */ 784 { 785 FR30_INSN_DIV2, "div2", "div2", 16, 786 { 0, { { { (1<<MACH_BASE), 0 } } } } 787 }, 788/* div3 */ 789 { 790 FR30_INSN_DIV3, "div3", "div3", 16, 791 { 0, { { { (1<<MACH_BASE), 0 } } } } 792 }, 793/* div4s */ 794 { 795 FR30_INSN_DIV4S, "div4s", "div4s", 16, 796 { 0, { { { (1<<MACH_BASE), 0 } } } } 797 }, 798/* lsl $Rj,$Ri */ 799 { 800 FR30_INSN_LSL, "lsl", "lsl", 16, 801 { 0, { { { (1<<MACH_BASE), 0 } } } } 802 }, 803/* lsl $u4,$Ri */ 804 { 805 FR30_INSN_LSLI, "lsli", "lsl", 16, 806 { 0, { { { (1<<MACH_BASE), 0 } } } } 807 }, 808/* lsl2 $u4,$Ri */ 809 { 810 FR30_INSN_LSL2, "lsl2", "lsl2", 16, 811 { 0, { { { (1<<MACH_BASE), 0 } } } } 812 }, 813/* lsr $Rj,$Ri */ 814 { 815 FR30_INSN_LSR, "lsr", "lsr", 16, 816 { 0, { { { (1<<MACH_BASE), 0 } } } } 817 }, 818/* lsr $u4,$Ri */ 819 { 820 FR30_INSN_LSRI, "lsri", "lsr", 16, 821 { 0, { { { (1<<MACH_BASE), 0 } } } } 822 }, 823/* lsr2 $u4,$Ri */ 824 { 825 FR30_INSN_LSR2, "lsr2", "lsr2", 16, 826 { 0, { { { (1<<MACH_BASE), 0 } } } } 827 }, 828/* asr $Rj,$Ri */ 829 { 830 FR30_INSN_ASR, "asr", "asr", 16, 831 { 0, { { { (1<<MACH_BASE), 0 } } } } 832 }, 833/* asr $u4,$Ri */ 834 { 835 FR30_INSN_ASRI, "asri", "asr", 16, 836 { 0, { { { (1<<MACH_BASE), 0 } } } } 837 }, 838/* asr2 $u4,$Ri */ 839 { 840 FR30_INSN_ASR2, "asr2", "asr2", 16, 841 { 0, { { { (1<<MACH_BASE), 0 } } } } 842 }, 843/* ldi:8 $i8,$Ri */ 844 { 845 FR30_INSN_LDI8, "ldi8", "ldi:8", 16, 846 { 0, { { { (1<<MACH_BASE), 0 } } } } 847 }, 848/* ldi:20 $i20,$Ri */ 849 { 850 FR30_INSN_LDI20, "ldi20", "ldi:20", 32, 851 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 852 }, 853/* ldi:32 $i32,$Ri */ 854 { 855 FR30_INSN_LDI32, "ldi32", "ldi:32", 48, 856 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 857 }, 858/* ld @$Rj,$Ri */ 859 { 860 FR30_INSN_LD, "ld", "ld", 16, 861 { 0, { { { (1<<MACH_BASE), 0 } } } } 862 }, 863/* lduh @$Rj,$Ri */ 864 { 865 FR30_INSN_LDUH, "lduh", "lduh", 16, 866 { 0, { { { (1<<MACH_BASE), 0 } } } } 867 }, 868/* ldub @$Rj,$Ri */ 869 { 870 FR30_INSN_LDUB, "ldub", "ldub", 16, 871 { 0, { { { (1<<MACH_BASE), 0 } } } } 872 }, 873/* ld @($R13,$Rj),$Ri */ 874 { 875 FR30_INSN_LDR13, "ldr13", "ld", 16, 876 { 0, { { { (1<<MACH_BASE), 0 } } } } 877 }, 878/* lduh @($R13,$Rj),$Ri */ 879 { 880 FR30_INSN_LDR13UH, "ldr13uh", "lduh", 16, 881 { 0, { { { (1<<MACH_BASE), 0 } } } } 882 }, 883/* ldub @($R13,$Rj),$Ri */ 884 { 885 FR30_INSN_LDR13UB, "ldr13ub", "ldub", 16, 886 { 0, { { { (1<<MACH_BASE), 0 } } } } 887 }, 888/* ld @($R14,$disp10),$Ri */ 889 { 890 FR30_INSN_LDR14, "ldr14", "ld", 16, 891 { 0, { { { (1<<MACH_BASE), 0 } } } } 892 }, 893/* lduh @($R14,$disp9),$Ri */ 894 { 895 FR30_INSN_LDR14UH, "ldr14uh", "lduh", 16, 896 { 0, { { { (1<<MACH_BASE), 0 } } } } 897 }, 898/* ldub @($R14,$disp8),$Ri */ 899 { 900 FR30_INSN_LDR14UB, "ldr14ub", "ldub", 16, 901 { 0, { { { (1<<MACH_BASE), 0 } } } } 902 }, 903/* ld @($R15,$udisp6),$Ri */ 904 { 905 FR30_INSN_LDR15, "ldr15", "ld", 16, 906 { 0, { { { (1<<MACH_BASE), 0 } } } } 907 }, 908/* ld @$R15+,$Ri */ 909 { 910 FR30_INSN_LDR15GR, "ldr15gr", "ld", 16, 911 { 0, { { { (1<<MACH_BASE), 0 } } } } 912 }, 913/* ld @$R15+,$Rs2 */ 914 { 915 FR30_INSN_LDR15DR, "ldr15dr", "ld", 16, 916 { 0, { { { (1<<MACH_BASE), 0 } } } } 917 }, 918/* ld @$R15+,$ps */ 919 { 920 FR30_INSN_LDR15PS, "ldr15ps", "ld", 16, 921 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 922 }, 923/* st $Ri,@$Rj */ 924 { 925 FR30_INSN_ST, "st", "st", 16, 926 { 0, { { { (1<<MACH_BASE), 0 } } } } 927 }, 928/* sth $Ri,@$Rj */ 929 { 930 FR30_INSN_STH, "sth", "sth", 16, 931 { 0, { { { (1<<MACH_BASE), 0 } } } } 932 }, 933/* stb $Ri,@$Rj */ 934 { 935 FR30_INSN_STB, "stb", "stb", 16, 936 { 0, { { { (1<<MACH_BASE), 0 } } } } 937 }, 938/* st $Ri,@($R13,$Rj) */ 939 { 940 FR30_INSN_STR13, "str13", "st", 16, 941 { 0, { { { (1<<MACH_BASE), 0 } } } } 942 }, 943/* sth $Ri,@($R13,$Rj) */ 944 { 945 FR30_INSN_STR13H, "str13h", "sth", 16, 946 { 0, { { { (1<<MACH_BASE), 0 } } } } 947 }, 948/* stb $Ri,@($R13,$Rj) */ 949 { 950 FR30_INSN_STR13B, "str13b", "stb", 16, 951 { 0, { { { (1<<MACH_BASE), 0 } } } } 952 }, 953/* st $Ri,@($R14,$disp10) */ 954 { 955 FR30_INSN_STR14, "str14", "st", 16, 956 { 0, { { { (1<<MACH_BASE), 0 } } } } 957 }, 958/* sth $Ri,@($R14,$disp9) */ 959 { 960 FR30_INSN_STR14H, "str14h", "sth", 16, 961 { 0, { { { (1<<MACH_BASE), 0 } } } } 962 }, 963/* stb $Ri,@($R14,$disp8) */ 964 { 965 FR30_INSN_STR14B, "str14b", "stb", 16, 966 { 0, { { { (1<<MACH_BASE), 0 } } } } 967 }, 968/* st $Ri,@($R15,$udisp6) */ 969 { 970 FR30_INSN_STR15, "str15", "st", 16, 971 { 0, { { { (1<<MACH_BASE), 0 } } } } 972 }, 973/* st $Ri,@-$R15 */ 974 { 975 FR30_INSN_STR15GR, "str15gr", "st", 16, 976 { 0, { { { (1<<MACH_BASE), 0 } } } } 977 }, 978/* st $Rs2,@-$R15 */ 979 { 980 FR30_INSN_STR15DR, "str15dr", "st", 16, 981 { 0, { { { (1<<MACH_BASE), 0 } } } } 982 }, 983/* st $ps,@-$R15 */ 984 { 985 FR30_INSN_STR15PS, "str15ps", "st", 16, 986 { 0, { { { (1<<MACH_BASE), 0 } } } } 987 }, 988/* mov $Rj,$Ri */ 989 { 990 FR30_INSN_MOV, "mov", "mov", 16, 991 { 0, { { { (1<<MACH_BASE), 0 } } } } 992 }, 993/* mov $Rs1,$Ri */ 994 { 995 FR30_INSN_MOVDR, "movdr", "mov", 16, 996 { 0, { { { (1<<MACH_BASE), 0 } } } } 997 }, 998/* mov $ps,$Ri */ 999 { 1000 FR30_INSN_MOVPS, "movps", "mov", 16, 1001 { 0, { { { (1<<MACH_BASE), 0 } } } } 1002 }, 1003/* mov $Ri,$Rs1 */ 1004 { 1005 FR30_INSN_MOV2DR, "mov2dr", "mov", 16, 1006 { 0, { { { (1<<MACH_BASE), 0 } } } } 1007 }, 1008/* mov $Ri,$ps */ 1009 { 1010 FR30_INSN_MOV2PS, "mov2ps", "mov", 16, 1011 { 0, { { { (1<<MACH_BASE), 0 } } } } 1012 }, 1013/* jmp @$Ri */ 1014 { 1015 FR30_INSN_JMP, "jmp", "jmp", 16, 1016 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } 1017 }, 1018/* jmp:d @$Ri */ 1019 { 1020 FR30_INSN_JMPD, "jmpd", "jmp:d", 16, 1021 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 1022 }, 1023/* call @$Ri */ 1024 { 1025 FR30_INSN_CALLR, "callr", "call", 16, 1026 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } 1027 }, 1028/* call:d @$Ri */ 1029 { 1030 FR30_INSN_CALLRD, "callrd", "call:d", 16, 1031 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 1032 }, 1033/* call $label12 */ 1034 { 1035 FR30_INSN_CALL, "call", "call", 16, 1036 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } 1037 }, 1038/* call:d $label12 */ 1039 { 1040 FR30_INSN_CALLD, "calld", "call:d", 16, 1041 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 1042 }, 1043/* ret */ 1044 { 1045 FR30_INSN_RET, "ret", "ret", 16, 1046 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } 1047 }, 1048/* ret:d */ 1049 { 1050 FR30_INSN_RET_D, "ret:d", "ret:d", 16, 1051 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 1052 }, 1053/* int $u8 */ 1054 { 1055 FR30_INSN_INT, "int", "int", 16, 1056 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } 1057 }, 1058/* inte */ 1059 { 1060 FR30_INSN_INTE, "inte", "inte", 16, 1061 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } 1062 }, 1063/* reti */ 1064 { 1065 FR30_INSN_RETI, "reti", "reti", 16, 1066 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } 1067 }, 1068/* bra:d $label9 */ 1069 { 1070 FR30_INSN_BRAD, "brad", "bra:d", 16, 1071 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 1072 }, 1073/* bra $label9 */ 1074 { 1075 FR30_INSN_BRA, "bra", "bra", 16, 1076 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } 1077 }, 1078/* bno:d $label9 */ 1079 { 1080 FR30_INSN_BNOD, "bnod", "bno:d", 16, 1081 { 0|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 1082 }, 1083/* bno $label9 */ 1084 { 1085 FR30_INSN_BNO, "bno", "bno", 16, 1086 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 1087 }, 1088/* beq:d $label9 */ 1089 { 1090 FR30_INSN_BEQD, "beqd", "beq:d", 16, 1091 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 1092 }, 1093/* beq $label9 */ 1094 { 1095 FR30_INSN_BEQ, "beq", "beq", 16, 1096 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } 1097 }, 1098/* bne:d $label9 */ 1099 { 1100 FR30_INSN_BNED, "bned", "bne:d", 16, 1101 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 1102 }, 1103/* bne $label9 */ 1104 { 1105 FR30_INSN_BNE, "bne", "bne", 16, 1106 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } 1107 }, 1108/* bc:d $label9 */ 1109 { 1110 FR30_INSN_BCD, "bcd", "bc:d", 16, 1111 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 1112 }, 1113/* bc $label9 */ 1114 { 1115 FR30_INSN_BC, "bc", "bc", 16, 1116 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } 1117 }, 1118/* bnc:d $label9 */ 1119 { 1120 FR30_INSN_BNCD, "bncd", "bnc:d", 16, 1121 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 1122 }, 1123/* bnc $label9 */ 1124 { 1125 FR30_INSN_BNC, "bnc", "bnc", 16, 1126 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } 1127 }, 1128/* bn:d $label9 */ 1129 { 1130 FR30_INSN_BND, "bnd", "bn:d", 16, 1131 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 1132 }, 1133/* bn $label9 */ 1134 { 1135 FR30_INSN_BN, "bn", "bn", 16, 1136 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } 1137 }, 1138/* bp:d $label9 */ 1139 { 1140 FR30_INSN_BPD, "bpd", "bp:d", 16, 1141 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 1142 }, 1143/* bp $label9 */ 1144 { 1145 FR30_INSN_BP, "bp", "bp", 16, 1146 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } 1147 }, 1148/* bv:d $label9 */ 1149 { 1150 FR30_INSN_BVD, "bvd", "bv:d", 16, 1151 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 1152 }, 1153/* bv $label9 */ 1154 { 1155 FR30_INSN_BV, "bv", "bv", 16, 1156 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } 1157 }, 1158/* bnv:d $label9 */ 1159 { 1160 FR30_INSN_BNVD, "bnvd", "bnv:d", 16, 1161 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 1162 }, 1163/* bnv $label9 */ 1164 { 1165 FR30_INSN_BNV, "bnv", "bnv", 16, 1166 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } 1167 }, 1168/* blt:d $label9 */ 1169 { 1170 FR30_INSN_BLTD, "bltd", "blt:d", 16, 1171 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 1172 }, 1173/* blt $label9 */ 1174 { 1175 FR30_INSN_BLT, "blt", "blt", 16, 1176 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } 1177 }, 1178/* bge:d $label9 */ 1179 { 1180 FR30_INSN_BGED, "bged", "bge:d", 16, 1181 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 1182 }, 1183/* bge $label9 */ 1184 { 1185 FR30_INSN_BGE, "bge", "bge", 16, 1186 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } 1187 }, 1188/* ble:d $label9 */ 1189 { 1190 FR30_INSN_BLED, "bled", "ble:d", 16, 1191 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 1192 }, 1193/* ble $label9 */ 1194 { 1195 FR30_INSN_BLE, "ble", "ble", 16, 1196 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } 1197 }, 1198/* bgt:d $label9 */ 1199 { 1200 FR30_INSN_BGTD, "bgtd", "bgt:d", 16, 1201 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 1202 }, 1203/* bgt $label9 */ 1204 { 1205 FR30_INSN_BGT, "bgt", "bgt", 16, 1206 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } 1207 }, 1208/* bls:d $label9 */ 1209 { 1210 FR30_INSN_BLSD, "blsd", "bls:d", 16, 1211 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 1212 }, 1213/* bls $label9 */ 1214 { 1215 FR30_INSN_BLS, "bls", "bls", 16, 1216 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } 1217 }, 1218/* bhi:d $label9 */ 1219 { 1220 FR30_INSN_BHID, "bhid", "bhi:d", 16, 1221 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 1222 }, 1223/* bhi $label9 */ 1224 { 1225 FR30_INSN_BHI, "bhi", "bhi", 16, 1226 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } 1227 }, 1228/* dmov $R13,@$dir10 */ 1229 { 1230 FR30_INSN_DMOVR13, "dmovr13", "dmov", 16, 1231 { 0, { { { (1<<MACH_BASE), 0 } } } } 1232 }, 1233/* dmovh $R13,@$dir9 */ 1234 { 1235 FR30_INSN_DMOVR13H, "dmovr13h", "dmovh", 16, 1236 { 0, { { { (1<<MACH_BASE), 0 } } } } 1237 }, 1238/* dmovb $R13,@$dir8 */ 1239 { 1240 FR30_INSN_DMOVR13B, "dmovr13b", "dmovb", 16, 1241 { 0, { { { (1<<MACH_BASE), 0 } } } } 1242 }, 1243/* dmov @$R13+,@$dir10 */ 1244 { 1245 FR30_INSN_DMOVR13PI, "dmovr13pi", "dmov", 16, 1246 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 1247 }, 1248/* dmovh @$R13+,@$dir9 */ 1249 { 1250 FR30_INSN_DMOVR13PIH, "dmovr13pih", "dmovh", 16, 1251 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 1252 }, 1253/* dmovb @$R13+,@$dir8 */ 1254 { 1255 FR30_INSN_DMOVR13PIB, "dmovr13pib", "dmovb", 16, 1256 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 1257 }, 1258/* dmov @$R15+,@$dir10 */ 1259 { 1260 FR30_INSN_DMOVR15PI, "dmovr15pi", "dmov", 16, 1261 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 1262 }, 1263/* dmov @$dir10,$R13 */ 1264 { 1265 FR30_INSN_DMOV2R13, "dmov2r13", "dmov", 16, 1266 { 0, { { { (1<<MACH_BASE), 0 } } } } 1267 }, 1268/* dmovh @$dir9,$R13 */ 1269 { 1270 FR30_INSN_DMOV2R13H, "dmov2r13h", "dmovh", 16, 1271 { 0, { { { (1<<MACH_BASE), 0 } } } } 1272 }, 1273/* dmovb @$dir8,$R13 */ 1274 { 1275 FR30_INSN_DMOV2R13B, "dmov2r13b", "dmovb", 16, 1276 { 0, { { { (1<<MACH_BASE), 0 } } } } 1277 }, 1278/* dmov @$dir10,@$R13+ */ 1279 { 1280 FR30_INSN_DMOV2R13PI, "dmov2r13pi", "dmov", 16, 1281 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 1282 }, 1283/* dmovh @$dir9,@$R13+ */ 1284 { 1285 FR30_INSN_DMOV2R13PIH, "dmov2r13pih", "dmovh", 16, 1286 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 1287 }, 1288/* dmovb @$dir8,@$R13+ */ 1289 { 1290 FR30_INSN_DMOV2R13PIB, "dmov2r13pib", "dmovb", 16, 1291 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 1292 }, 1293/* dmov @$dir10,@-$R15 */ 1294 { 1295 FR30_INSN_DMOV2R15PD, "dmov2r15pd", "dmov", 16, 1296 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 1297 }, 1298/* ldres @$Ri+,$u4 */ 1299 { 1300 FR30_INSN_LDRES, "ldres", "ldres", 16, 1301 { 0, { { { (1<<MACH_BASE), 0 } } } } 1302 }, 1303/* stres $u4,@$Ri+ */ 1304 { 1305 FR30_INSN_STRES, "stres", "stres", 16, 1306 { 0, { { { (1<<MACH_BASE), 0 } } } } 1307 }, 1308/* copop $u4c,$ccc,$CRj,$CRi */ 1309 { 1310 FR30_INSN_COPOP, "copop", "copop", 32, 1311 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 1312 }, 1313/* copld $u4c,$ccc,$Rjc,$CRi */ 1314 { 1315 FR30_INSN_COPLD, "copld", "copld", 32, 1316 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 1317 }, 1318/* copst $u4c,$ccc,$CRj,$Ric */ 1319 { 1320 FR30_INSN_COPST, "copst", "copst", 32, 1321 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 1322 }, 1323/* copsv $u4c,$ccc,$CRj,$Ric */ 1324 { 1325 FR30_INSN_COPSV, "copsv", "copsv", 32, 1326 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 1327 }, 1328/* nop */ 1329 { 1330 FR30_INSN_NOP, "nop", "nop", 16, 1331 { 0, { { { (1<<MACH_BASE), 0 } } } } 1332 }, 1333/* andccr $u8 */ 1334 { 1335 FR30_INSN_ANDCCR, "andccr", "andccr", 16, 1336 { 0, { { { (1<<MACH_BASE), 0 } } } } 1337 }, 1338/* orccr $u8 */ 1339 { 1340 FR30_INSN_ORCCR, "orccr", "orccr", 16, 1341 { 0, { { { (1<<MACH_BASE), 0 } } } } 1342 }, 1343/* stilm $u8 */ 1344 { 1345 FR30_INSN_STILM, "stilm", "stilm", 16, 1346 { 0, { { { (1<<MACH_BASE), 0 } } } } 1347 }, 1348/* addsp $s10 */ 1349 { 1350 FR30_INSN_ADDSP, "addsp", "addsp", 16, 1351 { 0, { { { (1<<MACH_BASE), 0 } } } } 1352 }, 1353/* extsb $Ri */ 1354 { 1355 FR30_INSN_EXTSB, "extsb", "extsb", 16, 1356 { 0, { { { (1<<MACH_BASE), 0 } } } } 1357 }, 1358/* extub $Ri */ 1359 { 1360 FR30_INSN_EXTUB, "extub", "extub", 16, 1361 { 0, { { { (1<<MACH_BASE), 0 } } } } 1362 }, 1363/* extsh $Ri */ 1364 { 1365 FR30_INSN_EXTSH, "extsh", "extsh", 16, 1366 { 0, { { { (1<<MACH_BASE), 0 } } } } 1367 }, 1368/* extuh $Ri */ 1369 { 1370 FR30_INSN_EXTUH, "extuh", "extuh", 16, 1371 { 0, { { { (1<<MACH_BASE), 0 } } } } 1372 }, 1373/* ldm0 ($reglist_low_ld) */ 1374 { 1375 FR30_INSN_LDM0, "ldm0", "ldm0", 16, 1376 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 1377 }, 1378/* ldm1 ($reglist_hi_ld) */ 1379 { 1380 FR30_INSN_LDM1, "ldm1", "ldm1", 16, 1381 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 1382 }, 1383/* stm0 ($reglist_low_st) */ 1384 { 1385 FR30_INSN_STM0, "stm0", "stm0", 16, 1386 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 1387 }, 1388/* stm1 ($reglist_hi_st) */ 1389 { 1390 FR30_INSN_STM1, "stm1", "stm1", 16, 1391 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 1392 }, 1393/* enter $u10 */ 1394 { 1395 FR30_INSN_ENTER, "enter", "enter", 16, 1396 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 1397 }, 1398/* leave */ 1399 { 1400 FR30_INSN_LEAVE, "leave", "leave", 16, 1401 { 0, { { { (1<<MACH_BASE), 0 } } } } 1402 }, 1403/* xchb @$Rj,$Ri */ 1404 { 1405 FR30_INSN_XCHB, "xchb", "xchb", 16, 1406 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 1407 }, 1408}; 1409 1410#undef OP 1411#undef A 1412 1413/* Initialize anything needed to be done once, before any cpu_open call. */ 1414 1415static void 1416init_tables (void) 1417{ 1418} 1419 1420#ifndef opcodes_error_handler 1421#define opcodes_error_handler(...) \ 1422 fprintf (stderr, __VA_ARGS__); fputc ('\n', stderr) 1423#endif 1424 1425static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *); 1426static void build_hw_table (CGEN_CPU_TABLE *); 1427static void build_ifield_table (CGEN_CPU_TABLE *); 1428static void build_operand_table (CGEN_CPU_TABLE *); 1429static void build_insn_table (CGEN_CPU_TABLE *); 1430static void fr30_cgen_rebuild_tables (CGEN_CPU_TABLE *); 1431 1432/* Subroutine of fr30_cgen_cpu_open to look up a mach via its bfd name. */ 1433 1434static const CGEN_MACH * 1435lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name) 1436{ 1437 while (table->name) 1438 { 1439 if (strcmp (name, table->bfd_name) == 0) 1440 return table; 1441 ++table; 1442 } 1443 return NULL; 1444} 1445 1446/* Subroutine of fr30_cgen_cpu_open to build the hardware table. */ 1447 1448static void 1449build_hw_table (CGEN_CPU_TABLE *cd) 1450{ 1451 int i; 1452 int machs = cd->machs; 1453 const CGEN_HW_ENTRY *init = & fr30_cgen_hw_table[0]; 1454 /* MAX_HW is only an upper bound on the number of selected entries. 1455 However each entry is indexed by it's enum so there can be holes in 1456 the table. */ 1457 const CGEN_HW_ENTRY **selected = 1458 (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *)); 1459 1460 cd->hw_table.init_entries = init; 1461 cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY); 1462 memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *)); 1463 /* ??? For now we just use machs to determine which ones we want. */ 1464 for (i = 0; init[i].name != NULL; ++i) 1465 if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH) 1466 & machs) 1467 selected[init[i].type] = &init[i]; 1468 cd->hw_table.entries = selected; 1469 cd->hw_table.num_entries = MAX_HW; 1470} 1471 1472/* Subroutine of fr30_cgen_cpu_open to build the hardware table. */ 1473 1474static void 1475build_ifield_table (CGEN_CPU_TABLE *cd) 1476{ 1477 cd->ifld_table = & fr30_cgen_ifld_table[0]; 1478} 1479 1480/* Subroutine of fr30_cgen_cpu_open to build the hardware table. */ 1481 1482static void 1483build_operand_table (CGEN_CPU_TABLE *cd) 1484{ 1485 int i; 1486 int machs = cd->machs; 1487 const CGEN_OPERAND *init = & fr30_cgen_operand_table[0]; 1488 /* MAX_OPERANDS is only an upper bound on the number of selected entries. 1489 However each entry is indexed by it's enum so there can be holes in 1490 the table. */ 1491 const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected)); 1492 1493 cd->operand_table.init_entries = init; 1494 cd->operand_table.entry_size = sizeof (CGEN_OPERAND); 1495 memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *)); 1496 /* ??? For now we just use mach to determine which ones we want. */ 1497 for (i = 0; init[i].name != NULL; ++i) 1498 if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH) 1499 & machs) 1500 selected[init[i].type] = &init[i]; 1501 cd->operand_table.entries = selected; 1502 cd->operand_table.num_entries = MAX_OPERANDS; 1503} 1504 1505/* Subroutine of fr30_cgen_cpu_open to build the hardware table. 1506 ??? This could leave out insns not supported by the specified mach/isa, 1507 but that would cause errors like "foo only supported by bar" to become 1508 "unknown insn", so for now we include all insns and require the app to 1509 do the checking later. 1510 ??? On the other hand, parsing of such insns may require their hardware or 1511 operand elements to be in the table [which they mightn't be]. */ 1512 1513static void 1514build_insn_table (CGEN_CPU_TABLE *cd) 1515{ 1516 int i; 1517 const CGEN_IBASE *ib = & fr30_cgen_insn_table[0]; 1518 CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); 1519 1520 memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); 1521 for (i = 0; i < MAX_INSNS; ++i) 1522 insns[i].base = &ib[i]; 1523 cd->insn_table.init_entries = insns; 1524 cd->insn_table.entry_size = sizeof (CGEN_IBASE); 1525 cd->insn_table.num_init_entries = MAX_INSNS; 1526} 1527 1528/* Subroutine of fr30_cgen_cpu_open to rebuild the tables. */ 1529 1530static void 1531fr30_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) 1532{ 1533 int i; 1534 CGEN_BITSET *isas = cd->isas; 1535 unsigned int machs = cd->machs; 1536 1537 cd->int_insn_p = CGEN_INT_INSN_P; 1538 1539 /* Data derived from the isa spec. */ 1540#define UNSET (CGEN_SIZE_UNKNOWN + 1) 1541 cd->default_insn_bitsize = UNSET; 1542 cd->base_insn_bitsize = UNSET; 1543 cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ 1544 cd->max_insn_bitsize = 0; 1545 for (i = 0; i < MAX_ISAS; ++i) 1546 if (cgen_bitset_contains (isas, i)) 1547 { 1548 const CGEN_ISA *isa = & fr30_cgen_isa_table[i]; 1549 1550 /* Default insn sizes of all selected isas must be 1551 equal or we set the result to 0, meaning "unknown". */ 1552 if (cd->default_insn_bitsize == UNSET) 1553 cd->default_insn_bitsize = isa->default_insn_bitsize; 1554 else if (isa->default_insn_bitsize == cd->default_insn_bitsize) 1555 ; /* This is ok. */ 1556 else 1557 cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; 1558 1559 /* Base insn sizes of all selected isas must be equal 1560 or we set the result to 0, meaning "unknown". */ 1561 if (cd->base_insn_bitsize == UNSET) 1562 cd->base_insn_bitsize = isa->base_insn_bitsize; 1563 else if (isa->base_insn_bitsize == cd->base_insn_bitsize) 1564 ; /* This is ok. */ 1565 else 1566 cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; 1567 1568 /* Set min,max insn sizes. */ 1569 if (isa->min_insn_bitsize < cd->min_insn_bitsize) 1570 cd->min_insn_bitsize = isa->min_insn_bitsize; 1571 if (isa->max_insn_bitsize > cd->max_insn_bitsize) 1572 cd->max_insn_bitsize = isa->max_insn_bitsize; 1573 } 1574 1575 /* Data derived from the mach spec. */ 1576 for (i = 0; i < MAX_MACHS; ++i) 1577 if (((1 << i) & machs) != 0) 1578 { 1579 const CGEN_MACH *mach = & fr30_cgen_mach_table[i]; 1580 1581 if (mach->insn_chunk_bitsize != 0) 1582 { 1583 if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize) 1584 { 1585 opcodes_error_handler 1586 (/* xgettext:c-format */ 1587 _("internal error: fr30_cgen_rebuild_tables: " 1588 "conflicting insn-chunk-bitsize values: `%d' vs. `%d'"), 1589 cd->insn_chunk_bitsize, mach->insn_chunk_bitsize); 1590 abort (); 1591 } 1592 1593 cd->insn_chunk_bitsize = mach->insn_chunk_bitsize; 1594 } 1595 } 1596 1597 /* Determine which hw elements are used by MACH. */ 1598 build_hw_table (cd); 1599 1600 /* Build the ifield table. */ 1601 build_ifield_table (cd); 1602 1603 /* Determine which operands are used by MACH/ISA. */ 1604 build_operand_table (cd); 1605 1606 /* Build the instruction table. */ 1607 build_insn_table (cd); 1608} 1609 1610/* Initialize a cpu table and return a descriptor. 1611 It's much like opening a file, and must be the first function called. 1612 The arguments are a set of (type/value) pairs, terminated with 1613 CGEN_CPU_OPEN_END. 1614 1615 Currently supported values: 1616 CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr 1617 CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr 1618 CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name 1619 CGEN_CPU_OPEN_ENDIAN: specify endian choice 1620 CGEN_CPU_OPEN_INSN_ENDIAN: specify instruction endian choice 1621 CGEN_CPU_OPEN_END: terminates arguments 1622 1623 ??? Simultaneous multiple isas might not make sense, but it's not (yet) 1624 precluded. */ 1625 1626CGEN_CPU_DESC 1627fr30_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) 1628{ 1629 CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); 1630 static int init_p; 1631 CGEN_BITSET *isas = 0; /* 0 = "unspecified" */ 1632 unsigned int machs = 0; /* 0 = "unspecified" */ 1633 enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; 1634 enum cgen_endian insn_endian = CGEN_ENDIAN_UNKNOWN; 1635 va_list ap; 1636 1637 if (! init_p) 1638 { 1639 init_tables (); 1640 init_p = 1; 1641 } 1642 1643 memset (cd, 0, sizeof (*cd)); 1644 1645 va_start (ap, arg_type); 1646 while (arg_type != CGEN_CPU_OPEN_END) 1647 { 1648 switch (arg_type) 1649 { 1650 case CGEN_CPU_OPEN_ISAS : 1651 isas = va_arg (ap, CGEN_BITSET *); 1652 break; 1653 case CGEN_CPU_OPEN_MACHS : 1654 machs = va_arg (ap, unsigned int); 1655 break; 1656 case CGEN_CPU_OPEN_BFDMACH : 1657 { 1658 const char *name = va_arg (ap, const char *); 1659 const CGEN_MACH *mach = 1660 lookup_mach_via_bfd_name (fr30_cgen_mach_table, name); 1661 1662 if (mach != NULL) 1663 machs |= 1 << mach->num; 1664 break; 1665 } 1666 case CGEN_CPU_OPEN_ENDIAN : 1667 endian = va_arg (ap, enum cgen_endian); 1668 break; 1669 case CGEN_CPU_OPEN_INSN_ENDIAN : 1670 insn_endian = va_arg (ap, enum cgen_endian); 1671 break; 1672 default : 1673 opcodes_error_handler 1674 (/* xgettext:c-format */ 1675 _("internal error: fr30_cgen_cpu_open: " 1676 "unsupported argument `%d'"), 1677 arg_type); 1678 abort (); /* ??? return NULL? */ 1679 } 1680 arg_type = va_arg (ap, enum cgen_cpu_open_arg); 1681 } 1682 va_end (ap); 1683 1684 /* Mach unspecified means "all". */ 1685 if (machs == 0) 1686 machs = (1 << MAX_MACHS) - 1; 1687 /* Base mach is always selected. */ 1688 machs |= 1; 1689 if (endian == CGEN_ENDIAN_UNKNOWN) 1690 { 1691 /* ??? If target has only one, could have a default. */ 1692 opcodes_error_handler 1693 (/* xgettext:c-format */ 1694 _("internal error: fr30_cgen_cpu_open: no endianness specified")); 1695 abort (); 1696 } 1697 1698 cd->isas = cgen_bitset_copy (isas); 1699 cd->machs = machs; 1700 cd->endian = endian; 1701 cd->insn_endian 1702 = (insn_endian == CGEN_ENDIAN_UNKNOWN ? endian : insn_endian); 1703 1704 /* Table (re)builder. */ 1705 cd->rebuild_tables = fr30_cgen_rebuild_tables; 1706 fr30_cgen_rebuild_tables (cd); 1707 1708 /* Default to not allowing signed overflow. */ 1709 cd->signed_overflow_ok_p = 0; 1710 1711 return (CGEN_CPU_DESC) cd; 1712} 1713 1714/* Cover fn to fr30_cgen_cpu_open to handle the simple case of 1 isa, 1 mach. 1715 MACH_NAME is the bfd name of the mach. */ 1716 1717CGEN_CPU_DESC 1718fr30_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian) 1719{ 1720 return fr30_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, 1721 CGEN_CPU_OPEN_ENDIAN, endian, 1722 CGEN_CPU_OPEN_END); 1723} 1724 1725/* Close a cpu table. 1726 ??? This can live in a machine independent file, but there's currently 1727 no place to put this file (there's no libcgen). libopcodes is the wrong 1728 place as some simulator ports use this but they don't use libopcodes. */ 1729 1730void 1731fr30_cgen_cpu_close (CGEN_CPU_DESC cd) 1732{ 1733 unsigned int i; 1734 const CGEN_INSN *insns; 1735 1736 if (cd->macro_insn_table.init_entries) 1737 { 1738 insns = cd->macro_insn_table.init_entries; 1739 for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns) 1740 if (CGEN_INSN_RX ((insns))) 1741 regfree (CGEN_INSN_RX (insns)); 1742 } 1743 1744 if (cd->insn_table.init_entries) 1745 { 1746 insns = cd->insn_table.init_entries; 1747 for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns) 1748 if (CGEN_INSN_RX (insns)) 1749 regfree (CGEN_INSN_RX (insns)); 1750 } 1751 1752 free ((CGEN_INSN *) cd->macro_insn_table.init_entries); 1753 free ((CGEN_INSN *) cd->insn_table.init_entries); 1754 free ((CGEN_HW_ENTRY *) cd->hw_table.entries); 1755 free ((CGEN_HW_ENTRY *) cd->operand_table.entries); 1756 free (cd); 1757} 1758 1759