archures.texi revision 1.5
1@section Architectures 2BFD keeps one atom in a BFD describing the 3architecture of the data attached to the BFD: a pointer to a 4@code{bfd_arch_info_type}. 5 6Pointers to structures can be requested independently of a BFD 7so that an architecture's information can be interrogated 8without access to an open BFD. 9 10The architecture information is provided by each architecture package. 11The set of default architectures is selected by the macro 12@code{SELECT_ARCHITECTURES}. This is normally set up in the 13@file{config/@var{target}.mt} file of your choice. If the name is not 14defined, then all the architectures supported are included. 15 16When BFD starts up, all the architectures are called with an 17initialize method. It is up to the architecture back end to 18insert as many items into the list of architectures as it wants to; 19generally this would be one for each machine and one for the 20default case (an item with a machine field of 0). 21 22BFD's idea of an architecture is implemented in @file{archures.c}. 23 24@subsection bfd_architecture 25 26 27@strong{Description}@* 28This enum gives the object file's CPU architecture, in a 29global sense---i.e., what processor family does it belong to? 30Another field indicates which processor within 31the family is in use. The machine gives a number which 32distinguishes different versions of the architecture, 33containing, for example, 2 and 3 for Intel i960 KA and i960 KB, 34and 68020 and 68030 for Motorola 68020 and 68030. 35@example 36enum bfd_architecture 37@{ 38 bfd_arch_unknown, /* File arch not known. */ 39 bfd_arch_obscure, /* Arch known, not one of these. */ 40 bfd_arch_m68k, /* Motorola 68xxx */ 41#define bfd_mach_m68000 1 42#define bfd_mach_m68008 2 43#define bfd_mach_m68010 3 44#define bfd_mach_m68020 4 45#define bfd_mach_m68030 5 46#define bfd_mach_m68040 6 47#define bfd_mach_m68060 7 48#define bfd_mach_cpu32 8 49#define bfd_mach_fido 9 50#define bfd_mach_mcf_isa_a_nodiv 10 51#define bfd_mach_mcf_isa_a 11 52#define bfd_mach_mcf_isa_a_mac 12 53#define bfd_mach_mcf_isa_a_emac 13 54#define bfd_mach_mcf_isa_aplus 14 55#define bfd_mach_mcf_isa_aplus_mac 15 56#define bfd_mach_mcf_isa_aplus_emac 16 57#define bfd_mach_mcf_isa_b_nousp 17 58#define bfd_mach_mcf_isa_b_nousp_mac 18 59#define bfd_mach_mcf_isa_b_nousp_emac 19 60#define bfd_mach_mcf_isa_b 20 61#define bfd_mach_mcf_isa_b_mac 21 62#define bfd_mach_mcf_isa_b_emac 22 63#define bfd_mach_mcf_isa_b_float 23 64#define bfd_mach_mcf_isa_b_float_mac 24 65#define bfd_mach_mcf_isa_b_float_emac 25 66#define bfd_mach_mcf_isa_c 26 67#define bfd_mach_mcf_isa_c_mac 27 68#define bfd_mach_mcf_isa_c_emac 28 69#define bfd_mach_mcf_isa_c_nodiv 29 70#define bfd_mach_mcf_isa_c_nodiv_mac 30 71#define bfd_mach_mcf_isa_c_nodiv_emac 31 72 bfd_arch_vax, /* DEC Vax */ 73 bfd_arch_i960, /* Intel 960 */ 74 /* The order of the following is important. 75 lower number indicates a machine type that 76 only accepts a subset of the instructions 77 available to machines with higher numbers. 78 The exception is the "ca", which is 79 incompatible with all other machines except 80 "core". */ 81 82#define bfd_mach_i960_core 1 83#define bfd_mach_i960_ka_sa 2 84#define bfd_mach_i960_kb_sb 3 85#define bfd_mach_i960_mc 4 86#define bfd_mach_i960_xa 5 87#define bfd_mach_i960_ca 6 88#define bfd_mach_i960_jx 7 89#define bfd_mach_i960_hx 8 90 91 bfd_arch_or1k, /* OpenRISC 1000 */ 92#define bfd_mach_or1k 1 93#define bfd_mach_or1knd 2 94 95 bfd_arch_sparc, /* SPARC */ 96#define bfd_mach_sparc 1 97/* The difference between v8plus and v9 is that v9 is a true 64 bit env. */ 98#define bfd_mach_sparc_sparclet 2 99#define bfd_mach_sparc_sparclite 3 100#define bfd_mach_sparc_v8plus 4 101#define bfd_mach_sparc_v8plusa 5 /* with ultrasparc add'ns. */ 102#define bfd_mach_sparc_sparclite_le 6 103#define bfd_mach_sparc_v9 7 104#define bfd_mach_sparc_v9a 8 /* with ultrasparc add'ns. */ 105#define bfd_mach_sparc_v8plusb 9 /* with cheetah add'ns. */ 106#define bfd_mach_sparc_v9b 10 /* with cheetah add'ns. */ 107#define bfd_mach_sparc_v8plusc 11 /* with UA2005 and T1 add'ns. */ 108#define bfd_mach_sparc_v9c 12 /* with UA2005 and T1 add'ns. */ 109#define bfd_mach_sparc_v8plusd 13 /* with UA2007 and T3 add'ns. */ 110#define bfd_mach_sparc_v9d 14 /* with UA2007 and T3 add'ns. */ 111#define bfd_mach_sparc_v8pluse 15 /* with OSA2001 and T4 add'ns (no IMA). */ 112#define bfd_mach_sparc_v9e 16 /* with OSA2001 and T4 add'ns (no IMA). */ 113#define bfd_mach_sparc_v8plusv 17 /* with OSA2011 and T4 and IMA and FJMAU add'ns. */ 114#define bfd_mach_sparc_v9v 18 /* with OSA2011 and T4 and IMA and FJMAU add'ns. */ 115#define bfd_mach_sparc_v8plusm 19 /* with OSA2015 and M7 add'ns. */ 116#define bfd_mach_sparc_v9m 20 /* with OSA2015 and M7 add'ns. */ 117/* Nonzero if MACH has the v9 instruction set. */ 118#define bfd_mach_sparc_v9_p(mach) \ 119 ((mach) >= bfd_mach_sparc_v8plus && (mach) <= bfd_mach_sparc_v9m \ 120 && (mach) != bfd_mach_sparc_sparclite_le) 121/* Nonzero if MACH is a 64 bit sparc architecture. */ 122#define bfd_mach_sparc_64bit_p(mach) \ 123 ((mach) >= bfd_mach_sparc_v9 \ 124 && (mach) != bfd_mach_sparc_v8plusb \ 125 && (mach) != bfd_mach_sparc_v8plusc \ 126 && (mach) != bfd_mach_sparc_v8plusd \ 127 && (mach) != bfd_mach_sparc_v8pluse \ 128 && (mach) != bfd_mach_sparc_v8plusv \ 129 && (mach) != bfd_mach_sparc_v8plusm) 130 bfd_arch_spu, /* PowerPC SPU */ 131#define bfd_mach_spu 256 132 bfd_arch_mips, /* MIPS Rxxxx */ 133#define bfd_mach_mips3000 3000 134#define bfd_mach_mips3900 3900 135#define bfd_mach_mips4000 4000 136#define bfd_mach_mips4010 4010 137#define bfd_mach_mips4100 4100 138#define bfd_mach_mips4111 4111 139#define bfd_mach_mips4120 4120 140#define bfd_mach_mips4300 4300 141#define bfd_mach_mips4400 4400 142#define bfd_mach_mips4600 4600 143#define bfd_mach_mips4650 4650 144#define bfd_mach_mips5000 5000 145#define bfd_mach_mips5400 5400 146#define bfd_mach_mips5500 5500 147#define bfd_mach_mips5900 5900 148#define bfd_mach_mips6000 6000 149#define bfd_mach_mips7000 7000 150#define bfd_mach_mips8000 8000 151#define bfd_mach_mips9000 9000 152#define bfd_mach_mips10000 10000 153#define bfd_mach_mips12000 12000 154#define bfd_mach_mips14000 14000 155#define bfd_mach_mips16000 16000 156#define bfd_mach_mips16 16 157#define bfd_mach_mips5 5 158#define bfd_mach_mips_loongson_2e 3001 159#define bfd_mach_mips_loongson_2f 3002 160#define bfd_mach_mips_loongson_3a 3003 161#define bfd_mach_mips_sb1 12310201 /* octal 'SB', 01 */ 162#define bfd_mach_mips_octeon 6501 163#define bfd_mach_mips_octeonp 6601 164#define bfd_mach_mips_octeon2 6502 165#define bfd_mach_mips_octeon3 6503 166#define bfd_mach_mips_xlr 887682 /* decimal 'XLR' */ 167#define bfd_mach_mipsisa32 32 168#define bfd_mach_mipsisa32r2 33 169#define bfd_mach_mipsisa32r3 34 170#define bfd_mach_mipsisa32r5 36 171#define bfd_mach_mipsisa32r6 37 172#define bfd_mach_mipsisa64 64 173#define bfd_mach_mipsisa64r2 65 174#define bfd_mach_mipsisa64r3 66 175#define bfd_mach_mipsisa64r5 68 176#define bfd_mach_mipsisa64r6 69 177#define bfd_mach_mips_micromips 96 178 bfd_arch_i386, /* Intel 386 */ 179#define bfd_mach_i386_intel_syntax (1 << 0) 180#define bfd_mach_i386_i8086 (1 << 1) 181#define bfd_mach_i386_i386 (1 << 2) 182#define bfd_mach_x86_64 (1 << 3) 183#define bfd_mach_x64_32 (1 << 4) 184#define bfd_mach_i386_i386_intel_syntax (bfd_mach_i386_i386 | bfd_mach_i386_intel_syntax) 185#define bfd_mach_x86_64_intel_syntax (bfd_mach_x86_64 | bfd_mach_i386_intel_syntax) 186#define bfd_mach_x64_32_intel_syntax (bfd_mach_x64_32 | bfd_mach_i386_intel_syntax) 187 bfd_arch_l1om, /* Intel L1OM */ 188#define bfd_mach_l1om (1 << 5) 189#define bfd_mach_l1om_intel_syntax (bfd_mach_l1om | bfd_mach_i386_intel_syntax) 190 bfd_arch_k1om, /* Intel K1OM */ 191#define bfd_mach_k1om (1 << 6) 192#define bfd_mach_k1om_intel_syntax (bfd_mach_k1om | bfd_mach_i386_intel_syntax) 193#define bfd_mach_i386_nacl (1 << 7) 194#define bfd_mach_i386_i386_nacl (bfd_mach_i386_i386 | bfd_mach_i386_nacl) 195#define bfd_mach_x86_64_nacl (bfd_mach_x86_64 | bfd_mach_i386_nacl) 196#define bfd_mach_x64_32_nacl (bfd_mach_x64_32 | bfd_mach_i386_nacl) 197 bfd_arch_iamcu, /* Intel MCU */ 198#define bfd_mach_iamcu (1 << 8) 199#define bfd_mach_i386_iamcu (bfd_mach_i386_i386 | bfd_mach_iamcu) 200#define bfd_mach_i386_iamcu_intel_syntax (bfd_mach_i386_iamcu | bfd_mach_i386_intel_syntax) 201 bfd_arch_we32k, /* AT&T WE32xxx */ 202 bfd_arch_tahoe, /* CCI/Harris Tahoe */ 203 bfd_arch_i860, /* Intel 860 */ 204 bfd_arch_i370, /* IBM 360/370 Mainframes */ 205 bfd_arch_romp, /* IBM ROMP PC/RT */ 206 bfd_arch_convex, /* Convex */ 207 bfd_arch_m88k, /* Motorola 88xxx */ 208 bfd_arch_m98k, /* Motorola 98xxx */ 209 bfd_arch_pyramid, /* Pyramid Technology */ 210 bfd_arch_h8300, /* Renesas H8/300 (formerly Hitachi H8/300) */ 211#define bfd_mach_h8300 1 212#define bfd_mach_h8300h 2 213#define bfd_mach_h8300s 3 214#define bfd_mach_h8300hn 4 215#define bfd_mach_h8300sn 5 216#define bfd_mach_h8300sx 6 217#define bfd_mach_h8300sxn 7 218 bfd_arch_pdp11, /* DEC PDP-11 */ 219 bfd_arch_plugin, 220 bfd_arch_powerpc, /* PowerPC */ 221#define bfd_mach_ppc 32 222#define bfd_mach_ppc64 64 223#define bfd_mach_ppc_403 403 224#define bfd_mach_ppc_403gc 4030 225#define bfd_mach_ppc_405 405 226#define bfd_mach_ppc_505 505 227#define bfd_mach_ppc_601 601 228#define bfd_mach_ppc_602 602 229#define bfd_mach_ppc_603 603 230#define bfd_mach_ppc_ec603e 6031 231#define bfd_mach_ppc_604 604 232#define bfd_mach_ppc_620 620 233#define bfd_mach_ppc_630 630 234#define bfd_mach_ppc_750 750 235#define bfd_mach_ppc_860 860 236#define bfd_mach_ppc_a35 35 237#define bfd_mach_ppc_rs64ii 642 238#define bfd_mach_ppc_rs64iii 643 239#define bfd_mach_ppc_7400 7400 240#define bfd_mach_ppc_e500 500 241#define bfd_mach_ppc_e500mc 5001 242#define bfd_mach_ppc_e500mc64 5005 243#define bfd_mach_ppc_e5500 5006 244#define bfd_mach_ppc_e6500 5007 245#define bfd_mach_ppc_titan 83 246#define bfd_mach_ppc_vle 84 247 bfd_arch_rs6000, /* IBM RS/6000 */ 248#define bfd_mach_rs6k 6000 249#define bfd_mach_rs6k_rs1 6001 250#define bfd_mach_rs6k_rsc 6003 251#define bfd_mach_rs6k_rs2 6002 252 bfd_arch_hppa, /* HP PA RISC */ 253#define bfd_mach_hppa10 10 254#define bfd_mach_hppa11 11 255#define bfd_mach_hppa20 20 256#define bfd_mach_hppa20w 25 257 bfd_arch_d10v, /* Mitsubishi D10V */ 258#define bfd_mach_d10v 1 259#define bfd_mach_d10v_ts2 2 260#define bfd_mach_d10v_ts3 3 261 bfd_arch_d30v, /* Mitsubishi D30V */ 262 bfd_arch_dlx, /* DLX */ 263 bfd_arch_m68hc11, /* Motorola 68HC11 */ 264 bfd_arch_m68hc12, /* Motorola 68HC12 */ 265#define bfd_mach_m6812_default 0 266#define bfd_mach_m6812 1 267#define bfd_mach_m6812s 2 268 bfd_arch_m9s12x, /* Freescale S12X */ 269 bfd_arch_m9s12xg, /* Freescale XGATE */ 270 bfd_arch_z8k, /* Zilog Z8000 */ 271#define bfd_mach_z8001 1 272#define bfd_mach_z8002 2 273 bfd_arch_h8500, /* Renesas H8/500 (formerly Hitachi H8/500) */ 274 bfd_arch_sh, /* Renesas / SuperH SH (formerly Hitachi SH) */ 275#define bfd_mach_sh 1 276#define bfd_mach_sh2 0x20 277#define bfd_mach_sh_dsp 0x2d 278#define bfd_mach_sh2a 0x2a 279#define bfd_mach_sh2a_nofpu 0x2b 280#define bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu 0x2a1 281#define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2 282#define bfd_mach_sh2a_or_sh4 0x2a3 283#define bfd_mach_sh2a_or_sh3e 0x2a4 284#define bfd_mach_sh2e 0x2e 285#define bfd_mach_sh3 0x30 286#define bfd_mach_sh3_nommu 0x31 287#define bfd_mach_sh3_dsp 0x3d 288#define bfd_mach_sh3e 0x3e 289#define bfd_mach_sh4 0x40 290#define bfd_mach_sh4_nofpu 0x41 291#define bfd_mach_sh4_nommu_nofpu 0x42 292#define bfd_mach_sh4a 0x4a 293#define bfd_mach_sh4a_nofpu 0x4b 294#define bfd_mach_sh4al_dsp 0x4d 295#define bfd_mach_sh5 0x50 296 bfd_arch_alpha, /* Dec Alpha */ 297#define bfd_mach_alpha_ev4 0x10 298#define bfd_mach_alpha_ev5 0x20 299#define bfd_mach_alpha_ev6 0x30 300 bfd_arch_arm, /* Advanced Risc Machines ARM. */ 301#define bfd_mach_arm_unknown 0 302#define bfd_mach_arm_2 1 303#define bfd_mach_arm_2a 2 304#define bfd_mach_arm_3 3 305#define bfd_mach_arm_3M 4 306#define bfd_mach_arm_4 5 307#define bfd_mach_arm_4T 6 308#define bfd_mach_arm_5 7 309#define bfd_mach_arm_5T 8 310#define bfd_mach_arm_5TE 9 311#define bfd_mach_arm_XScale 10 312#define bfd_mach_arm_ep9312 11 313#define bfd_mach_arm_iWMMXt 12 314#define bfd_mach_arm_iWMMXt2 13 315 bfd_arch_nds32, /* Andes NDS32 */ 316#define bfd_mach_n1 1 317#define bfd_mach_n1h 2 318#define bfd_mach_n1h_v2 3 319#define bfd_mach_n1h_v3 4 320#define bfd_mach_n1h_v3m 5 321 bfd_arch_ns32k, /* National Semiconductors ns32000 */ 322 bfd_arch_w65, /* WDC 65816 */ 323 bfd_arch_tic30, /* Texas Instruments TMS320C30 */ 324 bfd_arch_tic4x, /* Texas Instruments TMS320C3X/4X */ 325#define bfd_mach_tic3x 30 326#define bfd_mach_tic4x 40 327 bfd_arch_tic54x, /* Texas Instruments TMS320C54X */ 328 bfd_arch_tic6x, /* Texas Instruments TMS320C6X */ 329 bfd_arch_tic80, /* TI TMS320c80 (MVP) */ 330 bfd_arch_v850, /* NEC V850 */ 331 bfd_arch_v850_rh850,/* NEC V850 (using RH850 ABI) */ 332#define bfd_mach_v850 1 333#define bfd_mach_v850e 'E' 334#define bfd_mach_v850e1 '1' 335#define bfd_mach_v850e2 0x4532 336#define bfd_mach_v850e2v3 0x45325633 337#define bfd_mach_v850e3v5 0x45335635 /* ('E'|'3'|'V'|'5') */ 338 bfd_arch_arc, /* ARC Cores */ 339#define bfd_mach_arc_a4 0 340#define bfd_mach_arc_a5 1 341#define bfd_mach_arc_arc600 2 342#define bfd_mach_arc_arc601 4 343#define bfd_mach_arc_arc700 3 344#define bfd_mach_arc_arcv2 5 345 bfd_arch_m32c, /* Renesas M16C/M32C. */ 346#define bfd_mach_m16c 0x75 347#define bfd_mach_m32c 0x78 348 bfd_arch_m32r, /* Renesas M32R (formerly Mitsubishi M32R/D) */ 349#define bfd_mach_m32r 1 /* For backwards compatibility. */ 350#define bfd_mach_m32rx 'x' 351#define bfd_mach_m32r2 '2' 352 bfd_arch_mn10200, /* Matsushita MN10200 */ 353 bfd_arch_mn10300, /* Matsushita MN10300 */ 354#define bfd_mach_mn10300 300 355#define bfd_mach_am33 330 356#define bfd_mach_am33_2 332 357 bfd_arch_fr30, 358#define bfd_mach_fr30 0x46523330 359 bfd_arch_frv, 360#define bfd_mach_frv 1 361#define bfd_mach_frvsimple 2 362#define bfd_mach_fr300 300 363#define bfd_mach_fr400 400 364#define bfd_mach_fr450 450 365#define bfd_mach_frvtomcat 499 /* fr500 prototype */ 366#define bfd_mach_fr500 500 367#define bfd_mach_fr550 550 368 bfd_arch_moxie, /* The moxie processor */ 369#define bfd_mach_moxie 1 370 bfd_arch_ft32, /* The ft32 processor */ 371#define bfd_mach_ft32 1 372 bfd_arch_mcore, 373 bfd_arch_mep, 374#define bfd_mach_mep 1 375#define bfd_mach_mep_h1 0x6831 376#define bfd_mach_mep_c5 0x6335 377 bfd_arch_metag, 378#define bfd_mach_metag 1 379 bfd_arch_ia64, /* HP/Intel ia64 */ 380#define bfd_mach_ia64_elf64 64 381#define bfd_mach_ia64_elf32 32 382 bfd_arch_ip2k, /* Ubicom IP2K microcontrollers. */ 383#define bfd_mach_ip2022 1 384#define bfd_mach_ip2022ext 2 385 bfd_arch_iq2000, /* Vitesse IQ2000. */ 386#define bfd_mach_iq2000 1 387#define bfd_mach_iq10 2 388 bfd_arch_epiphany, /* Adapteva EPIPHANY */ 389#define bfd_mach_epiphany16 1 390#define bfd_mach_epiphany32 2 391 bfd_arch_mt, 392#define bfd_mach_ms1 1 393#define bfd_mach_mrisc2 2 394#define bfd_mach_ms2 3 395 bfd_arch_pj, 396 bfd_arch_avr, /* Atmel AVR microcontrollers. */ 397#define bfd_mach_avr1 1 398#define bfd_mach_avr2 2 399#define bfd_mach_avr25 25 400#define bfd_mach_avr3 3 401#define bfd_mach_avr31 31 402#define bfd_mach_avr35 35 403#define bfd_mach_avr4 4 404#define bfd_mach_avr5 5 405#define bfd_mach_avr51 51 406#define bfd_mach_avr6 6 407#define bfd_mach_avrtiny 100 408#define bfd_mach_avrxmega1 101 409#define bfd_mach_avrxmega2 102 410#define bfd_mach_avrxmega3 103 411#define bfd_mach_avrxmega4 104 412#define bfd_mach_avrxmega5 105 413#define bfd_mach_avrxmega6 106 414#define bfd_mach_avrxmega7 107 415 bfd_arch_bfin, /* ADI Blackfin */ 416#define bfd_mach_bfin 1 417 bfd_arch_cr16, /* National Semiconductor CompactRISC (ie CR16). */ 418#define bfd_mach_cr16 1 419 bfd_arch_cr16c, /* National Semiconductor CompactRISC. */ 420#define bfd_mach_cr16c 1 421 bfd_arch_crx, /* National Semiconductor CRX. */ 422#define bfd_mach_crx 1 423 bfd_arch_cris, /* Axis CRIS */ 424#define bfd_mach_cris_v0_v10 255 425#define bfd_mach_cris_v32 32 426#define bfd_mach_cris_v10_v32 1032 427 bfd_arch_rl78, 428#define bfd_mach_rl78 0x75 429 bfd_arch_rx, /* Renesas RX. */ 430#define bfd_mach_rx 0x75 431 bfd_arch_s390, /* IBM s390 */ 432#define bfd_mach_s390_31 31 433#define bfd_mach_s390_64 64 434 bfd_arch_score, /* Sunplus score */ 435#define bfd_mach_score3 3 436#define bfd_mach_score7 7 437 bfd_arch_mmix, /* Donald Knuth's educational processor. */ 438 bfd_arch_xstormy16, 439#define bfd_mach_xstormy16 1 440 bfd_arch_msp430, /* Texas Instruments MSP430 architecture. */ 441#define bfd_mach_msp11 11 442#define bfd_mach_msp110 110 443#define bfd_mach_msp12 12 444#define bfd_mach_msp13 13 445#define bfd_mach_msp14 14 446#define bfd_mach_msp15 15 447#define bfd_mach_msp16 16 448#define bfd_mach_msp20 20 449#define bfd_mach_msp21 21 450#define bfd_mach_msp22 22 451#define bfd_mach_msp23 23 452#define bfd_mach_msp24 24 453#define bfd_mach_msp26 26 454#define bfd_mach_msp31 31 455#define bfd_mach_msp32 32 456#define bfd_mach_msp33 33 457#define bfd_mach_msp41 41 458#define bfd_mach_msp42 42 459#define bfd_mach_msp43 43 460#define bfd_mach_msp44 44 461#define bfd_mach_msp430x 45 462#define bfd_mach_msp46 46 463#define bfd_mach_msp47 47 464#define bfd_mach_msp54 54 465 bfd_arch_xc16x, /* Infineon's XC16X Series. */ 466#define bfd_mach_xc16x 1 467#define bfd_mach_xc16xl 2 468#define bfd_mach_xc16xs 3 469 bfd_arch_xgate, /* Freescale XGATE */ 470#define bfd_mach_xgate 1 471 bfd_arch_xtensa, /* Tensilica's Xtensa cores. */ 472#define bfd_mach_xtensa 1 473 bfd_arch_z80, 474#define bfd_mach_z80strict 1 /* No undocumented opcodes. */ 475#define bfd_mach_z80 3 /* With ixl, ixh, iyl, and iyh. */ 476#define bfd_mach_z80full 7 /* All undocumented instructions. */ 477#define bfd_mach_r800 11 /* R800: successor with multiplication. */ 478 bfd_arch_lm32, /* Lattice Mico32 */ 479#define bfd_mach_lm32 1 480 bfd_arch_microblaze,/* Xilinx MicroBlaze. */ 481 bfd_arch_tilepro, /* Tilera TILEPro */ 482 bfd_arch_tilegx, /* Tilera TILE-Gx */ 483#define bfd_mach_tilepro 1 484#define bfd_mach_tilegx 1 485#define bfd_mach_tilegx32 2 486 bfd_arch_aarch64, /* AArch64 */ 487#define bfd_mach_aarch64 0 488#define bfd_mach_aarch64_ilp32 32 489 bfd_arch_nios2, /* Nios II */ 490#define bfd_mach_nios2 0 491#define bfd_mach_nios2r1 1 492#define bfd_mach_nios2r2 2 493 bfd_arch_visium, /* Visium */ 494#define bfd_mach_visium 1 495 bfd_arch_last 496 @}; 497@end example 498 499@subsection bfd_arch_info 500 501 502@strong{Description}@* 503This structure contains information on architectures for use 504within BFD. 505@example 506 507typedef struct bfd_arch_info 508@{ 509 int bits_per_word; 510 int bits_per_address; 511 int bits_per_byte; 512 enum bfd_architecture arch; 513 unsigned long mach; 514 const char *arch_name; 515 const char *printable_name; 516 unsigned int section_align_power; 517 /* TRUE if this is the default machine for the architecture. 518 The default arch should be the first entry for an arch so that 519 all the entries for that arch can be accessed via @code{next}. */ 520 bfd_boolean the_default; 521 const struct bfd_arch_info * (*compatible) 522 (const struct bfd_arch_info *a, const struct bfd_arch_info *b); 523 524 bfd_boolean (*scan) (const struct bfd_arch_info *, const char *); 525 526 /* Allocate via bfd_malloc and return a fill buffer of size COUNT. If 527 IS_BIGENDIAN is TRUE, the order of bytes is big endian. If CODE is 528 TRUE, the buffer contains code. */ 529 void *(*fill) (bfd_size_type count, bfd_boolean is_bigendian, 530 bfd_boolean code); 531 532 const struct bfd_arch_info *next; 533@} 534bfd_arch_info_type; 535 536@end example 537 538@findex bfd_printable_name 539@subsubsection @code{bfd_printable_name} 540@strong{Synopsis} 541@example 542const char *bfd_printable_name (bfd *abfd); 543@end example 544@strong{Description}@* 545Return a printable string representing the architecture and machine 546from the pointer to the architecture info structure. 547 548@findex bfd_scan_arch 549@subsubsection @code{bfd_scan_arch} 550@strong{Synopsis} 551@example 552const bfd_arch_info_type *bfd_scan_arch (const char *string); 553@end example 554@strong{Description}@* 555Figure out if BFD supports any cpu which could be described with 556the name @var{string}. Return a pointer to an @code{arch_info} 557structure if a machine is found, otherwise NULL. 558 559@findex bfd_arch_list 560@subsubsection @code{bfd_arch_list} 561@strong{Synopsis} 562@example 563const char **bfd_arch_list (void); 564@end example 565@strong{Description}@* 566Return a freshly malloced NULL-terminated vector of the names 567of all the valid BFD architectures. Do not modify the names. 568 569@findex bfd_arch_get_compatible 570@subsubsection @code{bfd_arch_get_compatible} 571@strong{Synopsis} 572@example 573const bfd_arch_info_type *bfd_arch_get_compatible 574 (const bfd *abfd, const bfd *bbfd, bfd_boolean accept_unknowns); 575@end example 576@strong{Description}@* 577Determine whether two BFDs' architectures and machine types 578are compatible. Calculates the lowest common denominator 579between the two architectures and machine types implied by 580the BFDs and returns a pointer to an @code{arch_info} structure 581describing the compatible machine. 582 583@findex bfd_default_arch_struct 584@subsubsection @code{bfd_default_arch_struct} 585@strong{Description}@* 586The @code{bfd_default_arch_struct} is an item of 587@code{bfd_arch_info_type} which has been initialized to a fairly 588generic state. A BFD starts life by pointing to this 589structure, until the correct back end has determined the real 590architecture of the file. 591@example 592extern const bfd_arch_info_type bfd_default_arch_struct; 593@end example 594 595@findex bfd_set_arch_info 596@subsubsection @code{bfd_set_arch_info} 597@strong{Synopsis} 598@example 599void bfd_set_arch_info (bfd *abfd, const bfd_arch_info_type *arg); 600@end example 601@strong{Description}@* 602Set the architecture info of @var{abfd} to @var{arg}. 603 604@findex bfd_default_set_arch_mach 605@subsubsection @code{bfd_default_set_arch_mach} 606@strong{Synopsis} 607@example 608bfd_boolean bfd_default_set_arch_mach 609 (bfd *abfd, enum bfd_architecture arch, unsigned long mach); 610@end example 611@strong{Description}@* 612Set the architecture and machine type in BFD @var{abfd} 613to @var{arch} and @var{mach}. Find the correct 614pointer to a structure and insert it into the @code{arch_info} 615pointer. 616 617@findex bfd_get_arch 618@subsubsection @code{bfd_get_arch} 619@strong{Synopsis} 620@example 621enum bfd_architecture bfd_get_arch (bfd *abfd); 622@end example 623@strong{Description}@* 624Return the enumerated type which describes the BFD @var{abfd}'s 625architecture. 626 627@findex bfd_get_mach 628@subsubsection @code{bfd_get_mach} 629@strong{Synopsis} 630@example 631unsigned long bfd_get_mach (bfd *abfd); 632@end example 633@strong{Description}@* 634Return the long type which describes the BFD @var{abfd}'s 635machine. 636 637@findex bfd_arch_bits_per_byte 638@subsubsection @code{bfd_arch_bits_per_byte} 639@strong{Synopsis} 640@example 641unsigned int bfd_arch_bits_per_byte (bfd *abfd); 642@end example 643@strong{Description}@* 644Return the number of bits in one of the BFD @var{abfd}'s 645architecture's bytes. 646 647@findex bfd_arch_bits_per_address 648@subsubsection @code{bfd_arch_bits_per_address} 649@strong{Synopsis} 650@example 651unsigned int bfd_arch_bits_per_address (bfd *abfd); 652@end example 653@strong{Description}@* 654Return the number of bits in one of the BFD @var{abfd}'s 655architecture's addresses. 656 657@findex bfd_default_compatible 658@subsubsection @code{bfd_default_compatible} 659@strong{Synopsis} 660@example 661const bfd_arch_info_type *bfd_default_compatible 662 (const bfd_arch_info_type *a, const bfd_arch_info_type *b); 663@end example 664@strong{Description}@* 665The default function for testing for compatibility. 666 667@findex bfd_default_scan 668@subsubsection @code{bfd_default_scan} 669@strong{Synopsis} 670@example 671bfd_boolean bfd_default_scan 672 (const struct bfd_arch_info *info, const char *string); 673@end example 674@strong{Description}@* 675The default function for working out whether this is an 676architecture hit and a machine hit. 677 678@findex bfd_get_arch_info 679@subsubsection @code{bfd_get_arch_info} 680@strong{Synopsis} 681@example 682const bfd_arch_info_type *bfd_get_arch_info (bfd *abfd); 683@end example 684@strong{Description}@* 685Return the architecture info struct in @var{abfd}. 686 687@findex bfd_lookup_arch 688@subsubsection @code{bfd_lookup_arch} 689@strong{Synopsis} 690@example 691const bfd_arch_info_type *bfd_lookup_arch 692 (enum bfd_architecture arch, unsigned long machine); 693@end example 694@strong{Description}@* 695Look for the architecture info structure which matches the 696arguments @var{arch} and @var{machine}. A machine of 0 matches the 697machine/architecture structure which marks itself as the 698default. 699 700@findex bfd_printable_arch_mach 701@subsubsection @code{bfd_printable_arch_mach} 702@strong{Synopsis} 703@example 704const char *bfd_printable_arch_mach 705 (enum bfd_architecture arch, unsigned long machine); 706@end example 707@strong{Description}@* 708Return a printable string representing the architecture and 709machine type. 710 711This routine is depreciated. 712 713@findex bfd_octets_per_byte 714@subsubsection @code{bfd_octets_per_byte} 715@strong{Synopsis} 716@example 717unsigned int bfd_octets_per_byte (bfd *abfd); 718@end example 719@strong{Description}@* 720Return the number of octets (8-bit quantities) per target byte 721(minimum addressable unit). In most cases, this will be one, but some 722DSP targets have 16, 32, or even 48 bits per byte. 723 724@findex bfd_arch_mach_octets_per_byte 725@subsubsection @code{bfd_arch_mach_octets_per_byte} 726@strong{Synopsis} 727@example 728unsigned int bfd_arch_mach_octets_per_byte 729 (enum bfd_architecture arch, unsigned long machine); 730@end example 731@strong{Description}@* 732See bfd_octets_per_byte. 733 734This routine is provided for those cases where a bfd * is not 735available 736 737@findex bfd_arch_default_fill 738@subsubsection @code{bfd_arch_default_fill} 739@strong{Synopsis} 740@example 741void *bfd_arch_default_fill (bfd_size_type count, 742 bfd_boolean is_bigendian, 743 bfd_boolean code); 744@end example 745@strong{Description}@* 746Allocate via bfd_malloc and return a fill buffer of size COUNT. 747If IS_BIGENDIAN is TRUE, the order of bytes is big endian. If 748CODE is TRUE, the buffer contains code. 749 750