1 2//===------------ MIRVRegNamerUtils.h - MIR VReg Renaming Utilities -------===// 3// 4// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 5// See https://llvm.org/LICENSE.txt for license information. 6// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7// 8//===----------------------------------------------------------------------===// 9// 10// The purpose of these utilities is to abstract out parts of the MIRCanon pass 11// that are responsible for renaming virtual registers with the purpose of 12// sharing code with a MIRVRegNamer pass that could be the analog of the 13// opt -instnamer pass. 14// 15//===----------------------------------------------------------------------===// 16 17#ifndef LLVM_LIB_CODEGEN_MIRVREGNAMERUTILS_H 18#define LLVM_LIB_CODEGEN_MIRVREGNAMERUTILS_H 19 20#include "llvm/CodeGen/Register.h" 21#include <map> 22#include <vector> 23#include <string> 24 25namespace llvm { 26 27class MachineBasicBlock; 28class MachineInstr; 29class MachineRegisterInfo; 30class StringRef; 31 32/// VRegRenamer - This class is used for renaming vregs in a machine basic 33/// block according to semantics of the instruction. 34class VRegRenamer { 35 class NamedVReg { 36 Register Reg; 37 std::string Name; 38 39 public: 40 NamedVReg(Register Reg, std::string Name = "") : Reg(Reg), Name(Name) {} 41 NamedVReg(std::string Name = "") : Reg(~0U), Name(Name) {} 42 43 const std::string &getName() const { return Name; } 44 45 Register getReg() const { return Reg; } 46 }; 47 48 MachineRegisterInfo &MRI; 49 50 unsigned CurrentBBNumber = 0; 51 52 /// Given an Instruction, construct a hash of the operands 53 /// of the instructions along with the opcode. 54 /// When dealing with virtual registers, just hash the opcode of 55 /// the instruction defining that vreg. 56 /// Handle immediates, registers (physical and virtual) explicitly, 57 /// and return a common value for the other cases. 58 /// Instruction will be named in the following scheme 59 /// bb<block_no>_hash_<collission_count>. 60 std::string getInstructionOpcodeHash(MachineInstr &MI); 61 62 /// For all the VRegs that are candidates for renaming, 63 /// return a mapping from old vregs to new vregs with names. 64 std::map<unsigned, unsigned> 65 getVRegRenameMap(const std::vector<NamedVReg> &VRegs); 66 67 /// Perform replacing of registers based on the <old,new> vreg map. 68 bool doVRegRenaming(const std::map<unsigned, unsigned> &VRegRenameMap); 69 70 /// createVirtualRegister - Given an existing vreg, create a named vreg to 71 /// take its place. The name is determined by calling 72 /// getInstructionOpcodeHash. 73 unsigned createVirtualRegister(unsigned VReg); 74 75 /// Create a vreg with name and return it. 76 unsigned createVirtualRegisterWithLowerName(unsigned VReg, StringRef Name); 77 78 /// Linearly traverse the MachineBasicBlock and rename each instruction's 79 /// vreg definition based on the semantics of the instruction. 80 /// Names are as follows bb<BBNum>_hash_[0-9]+ 81 bool renameInstsInMBB(MachineBasicBlock *MBB); 82 83public: 84 VRegRenamer() = delete; 85 VRegRenamer(MachineRegisterInfo &MRI) : MRI(MRI) {} 86 87 /// Same as the above, but sets a BBNum depending on BB traversal that 88 /// will be used as prefix for the vreg names. 89 bool renameVRegs(MachineBasicBlock *MBB, unsigned BBNum) { 90 CurrentBBNumber = BBNum; 91 return renameInstsInMBB(MBB); 92 } 93}; 94 95} // namespace llvm 96 97#endif 98