159243Sobrien#include "mips_arch.h"
259243Sobrien
359243Sobrien.text
459243Sobrien
559243Sobrien.set	noat
659243Sobrien.set	noreorder
759243Sobrien.align	5
859243Sobrien.globl	sha1_block_data_order
959243Sobrien.ent	sha1_block_data_order
1059243Sobriensha1_block_data_order:
1159243Sobrien	.frame	$29,16*8,$31
1259243Sobrien	.mask	0xc0ff0000,-8
1359243Sobrien	.set	noreorder
1459243Sobrien	dsubu $29,16*8
1559243Sobrien	sd	$31,(16-1)*8($29)
1659243Sobrien	sd	$30,(16-2)*8($29)
1759243Sobrien	sd	$23,(16-3)*8($29)
1859243Sobrien	sd	$22,(16-4)*8($29)
1959243Sobrien	sd	$21,(16-5)*8($29)
2059243Sobrien	sd	$20,(16-6)*8($29)
2159243Sobrien	sd	$19,(16-7)*8($29)
2259243Sobrien	sd	$18,(16-8)*8($29)
2359243Sobrien	sd	$17,(16-9)*8($29)
2459243Sobrien	sd	$16,(16-10)*8($29)
2559243Sobrien	dsll $6,6
2659243Sobrien	daddu $6,$5
2759243Sobrien	sd	$6,0($29)
2859243Sobrien	lw	$1,0($4)
2959243Sobrien	lw	$2,4($4)
3059243Sobrien	lw	$3,8($4)
3159243Sobrien	lw	$7,12($4)
3259243Sobrien	b	.Loop
3359243Sobrien	lw	$24,16($4)
3459243Sobrien.align	4
3559243Sobrien.Loop:
3659243Sobrien	.set	reorder
3759243Sobrien#if defined(_MIPS_ARCH_MIPS32R6) || defined(_MIPS_ARCH_MIPS64R6)
3859243Sobrien	lui	$31,0x5a82
3959243Sobrien	lw	$8,($5)
4059243Sobrien	ori	$31,0x7999	# K_00_19
4159243Sobrien#else
4259243Sobrien	lwl	$8,3($5)
4359243Sobrien	lui	$31,0x5a82
4459243Sobrien	lwr	$8,0($5)
4559243Sobrien	ori	$31,0x7999	# K_00_19
4659243Sobrien#endif
4759243Sobrien#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
4859243Sobrien	wsbh	$8,$8	# byte swap(0)
4959243Sobrien	rotr	$8,$8,16
5059243Sobrien#else
5159243Sobrien	srl	$25,$8,24	# byte swap(0)
5259243Sobrien	srl	$6,$8,8
5359243Sobrien	andi	$30,$8,0xFF00
5459243Sobrien	sll	$8,$8,24
5559243Sobrien	andi	$6,0xFF00
5659243Sobrien	sll	$30,$30,8
5759243Sobrien	or	$8,$25
5859243Sobrien	or	$6,$30
5959243Sobrien	or	$8,$6
6059243Sobrien#endif
6159243Sobrien#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
6259243Sobrien	addu	$24,$31		# 0
6359243Sobrien	xor	$25,$3,$7
6459243Sobrien	rotr	$6,$1,27
6559243Sobrien	and	$25,$2
6659243Sobrien	addu	$24,$6
6759243Sobrien#if defined(_MIPS_ARCH_MIPS32R6) || defined(_MIPS_ARCH_MIPS64R6)
6859243Sobrien	 lw	$9,1*4($5)
6959243Sobrien#else
7059243Sobrien	 lwl	$9,1*4+3($5)
7159243Sobrien	 lwr	$9,1*4+0($5)
7259243Sobrien#endif
7359243Sobrien	xor	$25,$7
7459243Sobrien	addu	$24,$8
7559243Sobrien	rotr	$2,$2,2
7659243Sobrien	addu	$24,$25
7759243Sobrien#else
7859243Sobrien	 lwl	$9,1*4+3($5)
7959243Sobrien	sll	$25,$1,5	# 0
8059243Sobrien	addu	$24,$31
8159243Sobrien	 lwr	$9,1*4+0($5)
8259243Sobrien	srl	$6,$1,27
8359243Sobrien	addu	$24,$25
8459243Sobrien	xor	$25,$3,$7
8559243Sobrien	addu	$24,$6
8659243Sobrien	sll	$30,$2,30
8759243Sobrien	and	$25,$2
8859243Sobrien	srl	$2,$2,2
8959243Sobrien	xor	$25,$7
9059243Sobrien	addu	$24,$8
9159243Sobrien	or	$2,$30
9259243Sobrien	addu	$24,$25
9359243Sobrien#endif
9459243Sobrien#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
9559243Sobrien	wsbh	$9,$9	# byte swap(1)
9659243Sobrien	rotr	$9,$9,16
9759243Sobrien#else
9859243Sobrien	srl	$25,$9,24	# byte swap(1)
9959243Sobrien	srl	$6,$9,8
10059243Sobrien	andi	$30,$9,0xFF00
10159243Sobrien	sll	$9,$9,24
10259243Sobrien	andi	$6,0xFF00
10359243Sobrien	sll	$30,$30,8
10459243Sobrien	or	$9,$25
10559243Sobrien	or	$6,$30
10659243Sobrien	or	$9,$6
10759243Sobrien#endif
10859243Sobrien#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
10959243Sobrien	addu	$7,$31		# 1
11059243Sobrien	xor	$25,$2,$3
11159243Sobrien	rotr	$6,$24,27
11259243Sobrien	and	$25,$1
11359243Sobrien	addu	$7,$6
11459243Sobrien#if defined(_MIPS_ARCH_MIPS32R6) || defined(_MIPS_ARCH_MIPS64R6)
11559243Sobrien	 lw	$10,2*4($5)
11659243Sobrien#else
11759243Sobrien	 lwl	$10,2*4+3($5)
11859243Sobrien	 lwr	$10,2*4+0($5)
11959243Sobrien#endif
12059243Sobrien	xor	$25,$3
12159243Sobrien	addu	$7,$9
12259243Sobrien	rotr	$1,$1,2
12359243Sobrien	addu	$7,$25
12459243Sobrien#else
12559243Sobrien	 lwl	$10,2*4+3($5)
12659243Sobrien	sll	$25,$24,5	# 1
12759243Sobrien	addu	$7,$31
12859243Sobrien	 lwr	$10,2*4+0($5)
12959243Sobrien	srl	$6,$24,27
13059243Sobrien	addu	$7,$25
13159243Sobrien	xor	$25,$2,$3
13259243Sobrien	addu	$7,$6
13359243Sobrien	sll	$30,$1,30
13459243Sobrien	and	$25,$1
13559243Sobrien	srl	$1,$1,2
13659243Sobrien	xor	$25,$3
13759243Sobrien	addu	$7,$9
13859243Sobrien	or	$1,$30
13959243Sobrien	addu	$7,$25
14059243Sobrien#endif
14159243Sobrien#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
14259243Sobrien	wsbh	$10,$10	# byte swap(2)
14359243Sobrien	rotr	$10,$10,16
14459243Sobrien#else
14559243Sobrien	srl	$25,$10,24	# byte swap(2)
14659243Sobrien	srl	$6,$10,8
14759243Sobrien	andi	$30,$10,0xFF00
14859243Sobrien	sll	$10,$10,24
14959243Sobrien	andi	$6,0xFF00
15059243Sobrien	sll	$30,$30,8
15159243Sobrien	or	$10,$25
15259243Sobrien	or	$6,$30
15359243Sobrien	or	$10,$6
15459243Sobrien#endif
15559243Sobrien#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
15659243Sobrien	addu	$3,$31		# 2
15759243Sobrien	xor	$25,$1,$2
15859243Sobrien	rotr	$6,$7,27
15959243Sobrien	and	$25,$24
16059243Sobrien	addu	$3,$6
16159243Sobrien#if defined(_MIPS_ARCH_MIPS32R6) || defined(_MIPS_ARCH_MIPS64R6)
16259243Sobrien	 lw	$11,3*4($5)
16359243Sobrien#else
16459243Sobrien	 lwl	$11,3*4+3($5)
16559243Sobrien	 lwr	$11,3*4+0($5)
16659243Sobrien#endif
16759243Sobrien	xor	$25,$2
16859243Sobrien	addu	$3,$10
16959243Sobrien	rotr	$24,$24,2
17059243Sobrien	addu	$3,$25
17159243Sobrien#else
17259243Sobrien	 lwl	$11,3*4+3($5)
17359243Sobrien	sll	$25,$7,5	# 2
17459243Sobrien	addu	$3,$31
17559243Sobrien	 lwr	$11,3*4+0($5)
17659243Sobrien	srl	$6,$7,27
17759243Sobrien	addu	$3,$25
17859243Sobrien	xor	$25,$1,$2
17959243Sobrien	addu	$3,$6
18059243Sobrien	sll	$30,$24,30
18159243Sobrien	and	$25,$24
18259243Sobrien	srl	$24,$24,2
18359243Sobrien	xor	$25,$2
18459243Sobrien	addu	$3,$10
18559243Sobrien	or	$24,$30
18659243Sobrien	addu	$3,$25
18759243Sobrien#endif
18859243Sobrien#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
18959243Sobrien	wsbh	$11,$11	# byte swap(3)
19059243Sobrien	rotr	$11,$11,16
19159243Sobrien#else
19259243Sobrien	srl	$25,$11,24	# byte swap(3)
19359243Sobrien	srl	$6,$11,8
19459243Sobrien	andi	$30,$11,0xFF00
19559243Sobrien	sll	$11,$11,24
19659243Sobrien	andi	$6,0xFF00
19759243Sobrien	sll	$30,$30,8
19859243Sobrien	or	$11,$25
19959243Sobrien	or	$6,$30
20059243Sobrien	or	$11,$6
20159243Sobrien#endif
20259243Sobrien#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
20359243Sobrien	addu	$2,$31		# 3
20459243Sobrien	xor	$25,$24,$1
20559243Sobrien	rotr	$6,$3,27
20659243Sobrien	and	$25,$7
20759243Sobrien	addu	$2,$6
20859243Sobrien#if defined(_MIPS_ARCH_MIPS32R6) || defined(_MIPS_ARCH_MIPS64R6)
20959243Sobrien	 lw	$12,4*4($5)
21059243Sobrien#else
21159243Sobrien	 lwl	$12,4*4+3($5)
21259243Sobrien	 lwr	$12,4*4+0($5)
21359243Sobrien#endif
21459243Sobrien	xor	$25,$1
21559243Sobrien	addu	$2,$11
21659243Sobrien	rotr	$7,$7,2
21759243Sobrien	addu	$2,$25
21859243Sobrien#else
21959243Sobrien	 lwl	$12,4*4+3($5)
22059243Sobrien	sll	$25,$3,5	# 3
22159243Sobrien	addu	$2,$31
22259243Sobrien	 lwr	$12,4*4+0($5)
22359243Sobrien	srl	$6,$3,27
22459243Sobrien	addu	$2,$25
22559243Sobrien	xor	$25,$24,$1
22659243Sobrien	addu	$2,$6
22759243Sobrien	sll	$30,$7,30
22859243Sobrien	and	$25,$7
22959243Sobrien	srl	$7,$7,2
23059243Sobrien	xor	$25,$1
23159243Sobrien	addu	$2,$11
23259243Sobrien	or	$7,$30
23359243Sobrien	addu	$2,$25
23459243Sobrien#endif
23559243Sobrien#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
23659243Sobrien	wsbh	$12,$12	# byte swap(4)
23759243Sobrien	rotr	$12,$12,16
23859243Sobrien#else
23959243Sobrien	srl	$25,$12,24	# byte swap(4)
24059243Sobrien	srl	$6,$12,8
24159243Sobrien	andi	$30,$12,0xFF00
24259243Sobrien	sll	$12,$12,24
24359243Sobrien	andi	$6,0xFF00
24459243Sobrien	sll	$30,$30,8
24559243Sobrien	or	$12,$25
24659243Sobrien	or	$6,$30
24759243Sobrien	or	$12,$6
24859243Sobrien#endif
24959243Sobrien#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
25059243Sobrien	addu	$1,$31		# 4
25159243Sobrien	xor	$25,$7,$24
25259243Sobrien	rotr	$6,$2,27
25359243Sobrien	and	$25,$3
25459243Sobrien	addu	$1,$6
25559243Sobrien#if defined(_MIPS_ARCH_MIPS32R6) || defined(_MIPS_ARCH_MIPS64R6)
25659243Sobrien	 lw	$13,5*4($5)
25759243Sobrien#else
25859243Sobrien	 lwl	$13,5*4+3($5)
25959243Sobrien	 lwr	$13,5*4+0($5)
26059243Sobrien#endif
26159243Sobrien	xor	$25,$24
26259243Sobrien	addu	$1,$12
26359243Sobrien	rotr	$3,$3,2
26459243Sobrien	addu	$1,$25
26559243Sobrien#else
26659243Sobrien	 lwl	$13,5*4+3($5)
26759243Sobrien	sll	$25,$2,5	# 4
26859243Sobrien	addu	$1,$31
26959243Sobrien	 lwr	$13,5*4+0($5)
27059243Sobrien	srl	$6,$2,27
27159243Sobrien	addu	$1,$25
27259243Sobrien	xor	$25,$7,$24
27359243Sobrien	addu	$1,$6
27459243Sobrien	sll	$30,$3,30
27559243Sobrien	and	$25,$3
27659243Sobrien	srl	$3,$3,2
27759243Sobrien	xor	$25,$24
27859243Sobrien	addu	$1,$12
27959243Sobrien	or	$3,$30
28059243Sobrien	addu	$1,$25
28159243Sobrien#endif
28259243Sobrien#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
28359243Sobrien	wsbh	$13,$13	# byte swap(5)
28459243Sobrien	rotr	$13,$13,16
28559243Sobrien#else
28659243Sobrien	srl	$25,$13,24	# byte swap(5)
28759243Sobrien	srl	$6,$13,8
28859243Sobrien	andi	$30,$13,0xFF00
28959243Sobrien	sll	$13,$13,24
29059243Sobrien	andi	$6,0xFF00
29159243Sobrien	sll	$30,$30,8
29259243Sobrien	or	$13,$25
29359243Sobrien	or	$6,$30
29459243Sobrien	or	$13,$6
29559243Sobrien#endif
29659243Sobrien#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
29759243Sobrien	addu	$24,$31		# 5
29859243Sobrien	xor	$25,$3,$7
29959243Sobrien	rotr	$6,$1,27
30059243Sobrien	and	$25,$2
30159243Sobrien	addu	$24,$6
30259243Sobrien#if defined(_MIPS_ARCH_MIPS32R6) || defined(_MIPS_ARCH_MIPS64R6)
30359243Sobrien	 lw	$14,6*4($5)
30459243Sobrien#else
30559243Sobrien	 lwl	$14,6*4+3($5)
30659243Sobrien	 lwr	$14,6*4+0($5)
30759243Sobrien#endif
30859243Sobrien	xor	$25,$7
30959243Sobrien	addu	$24,$13
31059243Sobrien	rotr	$2,$2,2
31159243Sobrien	addu	$24,$25
31259243Sobrien#else
31359243Sobrien	 lwl	$14,6*4+3($5)
31459243Sobrien	sll	$25,$1,5	# 5
31559243Sobrien	addu	$24,$31
31659243Sobrien	 lwr	$14,6*4+0($5)
31759243Sobrien	srl	$6,$1,27
31859243Sobrien	addu	$24,$25
31959243Sobrien	xor	$25,$3,$7
32059243Sobrien	addu	$24,$6
32159243Sobrien	sll	$30,$2,30
32259243Sobrien	and	$25,$2
32359243Sobrien	srl	$2,$2,2
32459243Sobrien	xor	$25,$7
32559243Sobrien	addu	$24,$13
32659243Sobrien	or	$2,$30
32759243Sobrien	addu	$24,$25
32859243Sobrien#endif
32959243Sobrien#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
33059243Sobrien	wsbh	$14,$14	# byte swap(6)
33159243Sobrien	rotr	$14,$14,16
33259243Sobrien#else
33359243Sobrien	srl	$25,$14,24	# byte swap(6)
33459243Sobrien	srl	$6,$14,8
33559243Sobrien	andi	$30,$14,0xFF00
33659243Sobrien	sll	$14,$14,24
33759243Sobrien	andi	$6,0xFF00
33859243Sobrien	sll	$30,$30,8
33959243Sobrien	or	$14,$25
34059243Sobrien	or	$6,$30
34159243Sobrien	or	$14,$6
34259243Sobrien#endif
34359243Sobrien#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
34459243Sobrien	addu	$7,$31		# 6
34559243Sobrien	xor	$25,$2,$3
34659243Sobrien	rotr	$6,$24,27
34759243Sobrien	and	$25,$1
34859243Sobrien	addu	$7,$6
34959243Sobrien#if defined(_MIPS_ARCH_MIPS32R6) || defined(_MIPS_ARCH_MIPS64R6)
35059243Sobrien	 lw	$15,7*4($5)
35159243Sobrien#else
35259243Sobrien	 lwl	$15,7*4+3($5)
35359243Sobrien	 lwr	$15,7*4+0($5)
35459243Sobrien#endif
35559243Sobrien	xor	$25,$3
35659243Sobrien	addu	$7,$14
35759243Sobrien	rotr	$1,$1,2
35859243Sobrien	addu	$7,$25
35959243Sobrien#else
36059243Sobrien	 lwl	$15,7*4+3($5)
36159243Sobrien	sll	$25,$24,5	# 6
36259243Sobrien	addu	$7,$31
36359243Sobrien	 lwr	$15,7*4+0($5)
36459243Sobrien	srl	$6,$24,27
36559243Sobrien	addu	$7,$25
36659243Sobrien	xor	$25,$2,$3
36759243Sobrien	addu	$7,$6
36859243Sobrien	sll	$30,$1,30
36959243Sobrien	and	$25,$1
37059243Sobrien	srl	$1,$1,2
37159243Sobrien	xor	$25,$3
37259243Sobrien	addu	$7,$14
37359243Sobrien	or	$1,$30
37459243Sobrien	addu	$7,$25
37559243Sobrien#endif
37659243Sobrien#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
37759243Sobrien	wsbh	$15,$15	# byte swap(7)
37859243Sobrien	rotr	$15,$15,16
37959243Sobrien#else
38059243Sobrien	srl	$25,$15,24	# byte swap(7)
38159243Sobrien	srl	$6,$15,8
38259243Sobrien	andi	$30,$15,0xFF00
38359243Sobrien	sll	$15,$15,24
38459243Sobrien	andi	$6,0xFF00
38559243Sobrien	sll	$30,$30,8
38659243Sobrien	or	$15,$25
38759243Sobrien	or	$6,$30
38859243Sobrien	or	$15,$6
38959243Sobrien#endif
39059243Sobrien#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
39159243Sobrien	addu	$3,$31		# 7
39259243Sobrien	xor	$25,$1,$2
39359243Sobrien	rotr	$6,$7,27
39459243Sobrien	and	$25,$24
39559243Sobrien	addu	$3,$6
39659243Sobrien#if defined(_MIPS_ARCH_MIPS32R6) || defined(_MIPS_ARCH_MIPS64R6)
39759243Sobrien	 lw	$16,8*4($5)
39859243Sobrien#else
39959243Sobrien	 lwl	$16,8*4+3($5)
40059243Sobrien	 lwr	$16,8*4+0($5)
40159243Sobrien#endif
40259243Sobrien	xor	$25,$2
40359243Sobrien	addu	$3,$15
40459243Sobrien	rotr	$24,$24,2
40559243Sobrien	addu	$3,$25
40659243Sobrien#else
40759243Sobrien	 lwl	$16,8*4+3($5)
40859243Sobrien	sll	$25,$7,5	# 7
40959243Sobrien	addu	$3,$31
41059243Sobrien	 lwr	$16,8*4+0($5)
41159243Sobrien	srl	$6,$7,27
41259243Sobrien	addu	$3,$25
41359243Sobrien	xor	$25,$1,$2
41459243Sobrien	addu	$3,$6
41559243Sobrien	sll	$30,$24,30
41659243Sobrien	and	$25,$24
41759243Sobrien	srl	$24,$24,2
41859243Sobrien	xor	$25,$2
41959243Sobrien	addu	$3,$15
42059243Sobrien	or	$24,$30
42159243Sobrien	addu	$3,$25
42259243Sobrien#endif
42359243Sobrien#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
42459243Sobrien	wsbh	$16,$16	# byte swap(8)
42559243Sobrien	rotr	$16,$16,16
42659243Sobrien#else
42759243Sobrien	srl	$25,$16,24	# byte swap(8)
42859243Sobrien	srl	$6,$16,8
42959243Sobrien	andi	$30,$16,0xFF00
43059243Sobrien	sll	$16,$16,24
43159243Sobrien	andi	$6,0xFF00
43259243Sobrien	sll	$30,$30,8
43359243Sobrien	or	$16,$25
43459243Sobrien	or	$6,$30
43559243Sobrien	or	$16,$6
43659243Sobrien#endif
43759243Sobrien#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
43859243Sobrien	addu	$2,$31		# 8
43959243Sobrien	xor	$25,$24,$1
44059243Sobrien	rotr	$6,$3,27
44159243Sobrien	and	$25,$7
44259243Sobrien	addu	$2,$6
44359243Sobrien#if defined(_MIPS_ARCH_MIPS32R6) || defined(_MIPS_ARCH_MIPS64R6)
44459243Sobrien	 lw	$17,9*4($5)
44559243Sobrien#else
44659243Sobrien	 lwl	$17,9*4+3($5)
44759243Sobrien	 lwr	$17,9*4+0($5)
44859243Sobrien#endif
44959243Sobrien	xor	$25,$1
45059243Sobrien	addu	$2,$16
45159243Sobrien	rotr	$7,$7,2
45259243Sobrien	addu	$2,$25
45359243Sobrien#else
45459243Sobrien	 lwl	$17,9*4+3($5)
45559243Sobrien	sll	$25,$3,5	# 8
45659243Sobrien	addu	$2,$31
45759243Sobrien	 lwr	$17,9*4+0($5)
45859243Sobrien	srl	$6,$3,27
45959243Sobrien	addu	$2,$25
46059243Sobrien	xor	$25,$24,$1
46159243Sobrien	addu	$2,$6
46259243Sobrien	sll	$30,$7,30
46359243Sobrien	and	$25,$7
46459243Sobrien	srl	$7,$7,2
46559243Sobrien	xor	$25,$1
46659243Sobrien	addu	$2,$16
46759243Sobrien	or	$7,$30
46859243Sobrien	addu	$2,$25
46959243Sobrien#endif
47059243Sobrien#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
47159243Sobrien	wsbh	$17,$17	# byte swap(9)
47259243Sobrien	rotr	$17,$17,16
47359243Sobrien#else
47459243Sobrien	srl	$25,$17,24	# byte swap(9)
47559243Sobrien	srl	$6,$17,8
47659243Sobrien	andi	$30,$17,0xFF00
47759243Sobrien	sll	$17,$17,24
47859243Sobrien	andi	$6,0xFF00
47959243Sobrien	sll	$30,$30,8
48059243Sobrien	or	$17,$25
48159243Sobrien	or	$6,$30
48259243Sobrien	or	$17,$6
48359243Sobrien#endif
48459243Sobrien#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
48559243Sobrien	addu	$1,$31		# 9
48659243Sobrien	xor	$25,$7,$24
48759243Sobrien	rotr	$6,$2,27
48859243Sobrien	and	$25,$3
48959243Sobrien	addu	$1,$6
49059243Sobrien#if defined(_MIPS_ARCH_MIPS32R6) || defined(_MIPS_ARCH_MIPS64R6)
49159243Sobrien	 lw	$18,10*4($5)
49259243Sobrien#else
49359243Sobrien	 lwl	$18,10*4+3($5)
49459243Sobrien	 lwr	$18,10*4+0($5)
49559243Sobrien#endif
49659243Sobrien	xor	$25,$24
49759243Sobrien	addu	$1,$17
49859243Sobrien	rotr	$3,$3,2
49959243Sobrien	addu	$1,$25
50059243Sobrien#else
50159243Sobrien	 lwl	$18,10*4+3($5)
50259243Sobrien	sll	$25,$2,5	# 9
50359243Sobrien	addu	$1,$31
50459243Sobrien	 lwr	$18,10*4+0($5)
50559243Sobrien	srl	$6,$2,27
50659243Sobrien	addu	$1,$25
50759243Sobrien	xor	$25,$7,$24
50859243Sobrien	addu	$1,$6
50959243Sobrien	sll	$30,$3,30
51059243Sobrien	and	$25,$3
51159243Sobrien	srl	$3,$3,2
51259243Sobrien	xor	$25,$24
51359243Sobrien	addu	$1,$17
51459243Sobrien	or	$3,$30
51559243Sobrien	addu	$1,$25
51659243Sobrien#endif
51759243Sobrien#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
51859243Sobrien	wsbh	$18,$18	# byte swap(10)
51959243Sobrien	rotr	$18,$18,16
52059243Sobrien#else
52159243Sobrien	srl	$25,$18,24	# byte swap(10)
52259243Sobrien	srl	$6,$18,8
52359243Sobrien	andi	$30,$18,0xFF00
52459243Sobrien	sll	$18,$18,24
52559243Sobrien	andi	$6,0xFF00
52659243Sobrien	sll	$30,$30,8
52759243Sobrien	or	$18,$25
52859243Sobrien	or	$6,$30
52959243Sobrien	or	$18,$6
53059243Sobrien#endif
53159243Sobrien#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
53259243Sobrien	addu	$24,$31		# 10
53359243Sobrien	xor	$25,$3,$7
53459243Sobrien	rotr	$6,$1,27
53559243Sobrien	and	$25,$2
53659243Sobrien	addu	$24,$6
53759243Sobrien#if defined(_MIPS_ARCH_MIPS32R6) || defined(_MIPS_ARCH_MIPS64R6)
53859243Sobrien	 lw	$19,11*4($5)
53959243Sobrien#else
54059243Sobrien	 lwl	$19,11*4+3($5)
54159243Sobrien	 lwr	$19,11*4+0($5)
54259243Sobrien#endif
54359243Sobrien	xor	$25,$7
54459243Sobrien	addu	$24,$18
54559243Sobrien	rotr	$2,$2,2
54659243Sobrien	addu	$24,$25
54759243Sobrien#else
54859243Sobrien	 lwl	$19,11*4+3($5)
54959243Sobrien	sll	$25,$1,5	# 10
55059243Sobrien	addu	$24,$31
55159243Sobrien	 lwr	$19,11*4+0($5)
55259243Sobrien	srl	$6,$1,27
55359243Sobrien	addu	$24,$25
55459243Sobrien	xor	$25,$3,$7
55559243Sobrien	addu	$24,$6
55659243Sobrien	sll	$30,$2,30
55759243Sobrien	and	$25,$2
55859243Sobrien	srl	$2,$2,2
55959243Sobrien	xor	$25,$7
56059243Sobrien	addu	$24,$18
56159243Sobrien	or	$2,$30
56259243Sobrien	addu	$24,$25
56359243Sobrien#endif
56459243Sobrien#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
56559243Sobrien	wsbh	$19,$19	# byte swap(11)
56659243Sobrien	rotr	$19,$19,16
56759243Sobrien#else
56859243Sobrien	srl	$25,$19,24	# byte swap(11)
56959243Sobrien	srl	$6,$19,8
57059243Sobrien	andi	$30,$19,0xFF00
57159243Sobrien	sll	$19,$19,24
57259243Sobrien	andi	$6,0xFF00
57359243Sobrien	sll	$30,$30,8
57459243Sobrien	or	$19,$25
57559243Sobrien	or	$6,$30
57659243Sobrien	or	$19,$6
57759243Sobrien#endif
57859243Sobrien#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
57959243Sobrien	addu	$7,$31		# 11
58059243Sobrien	xor	$25,$2,$3
58159243Sobrien	rotr	$6,$24,27
58259243Sobrien	and	$25,$1
58359243Sobrien	addu	$7,$6
58459243Sobrien#if defined(_MIPS_ARCH_MIPS32R6) || defined(_MIPS_ARCH_MIPS64R6)
58559243Sobrien	 lw	$20,12*4($5)
58659243Sobrien#else
58759243Sobrien	 lwl	$20,12*4+3($5)
58859243Sobrien	 lwr	$20,12*4+0($5)
58959243Sobrien#endif
59059243Sobrien	xor	$25,$3
59159243Sobrien	addu	$7,$19
59259243Sobrien	rotr	$1,$1,2
59359243Sobrien	addu	$7,$25
59459243Sobrien#else
595	 lwl	$20,12*4+3($5)
596	sll	$25,$24,5	# 11
597	addu	$7,$31
598	 lwr	$20,12*4+0($5)
599	srl	$6,$24,27
600	addu	$7,$25
601	xor	$25,$2,$3
602	addu	$7,$6
603	sll	$30,$1,30
604	and	$25,$1
605	srl	$1,$1,2
606	xor	$25,$3
607	addu	$7,$19
608	or	$1,$30
609	addu	$7,$25
610#endif
611#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
612	wsbh	$20,$20	# byte swap(12)
613	rotr	$20,$20,16
614#else
615	srl	$25,$20,24	# byte swap(12)
616	srl	$6,$20,8
617	andi	$30,$20,0xFF00
618	sll	$20,$20,24
619	andi	$6,0xFF00
620	sll	$30,$30,8
621	or	$20,$25
622	or	$6,$30
623	or	$20,$6
624#endif
625#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
626	addu	$3,$31		# 12
627	xor	$25,$1,$2
628	rotr	$6,$7,27
629	and	$25,$24
630	addu	$3,$6
631#if defined(_MIPS_ARCH_MIPS32R6) || defined(_MIPS_ARCH_MIPS64R6)
632	 lw	$21,13*4($5)
633#else
634	 lwl	$21,13*4+3($5)
635	 lwr	$21,13*4+0($5)
636#endif
637	xor	$25,$2
638	addu	$3,$20
639	rotr	$24,$24,2
640	addu	$3,$25
641#else
642	 lwl	$21,13*4+3($5)
643	sll	$25,$7,5	# 12
644	addu	$3,$31
645	 lwr	$21,13*4+0($5)
646	srl	$6,$7,27
647	addu	$3,$25
648	xor	$25,$1,$2
649	addu	$3,$6
650	sll	$30,$24,30
651	and	$25,$24
652	srl	$24,$24,2
653	xor	$25,$2
654	addu	$3,$20
655	or	$24,$30
656	addu	$3,$25
657#endif
658#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
659	wsbh	$21,$21	# byte swap(13)
660	rotr	$21,$21,16
661#else
662	srl	$25,$21,24	# byte swap(13)
663	srl	$6,$21,8
664	andi	$30,$21,0xFF00
665	sll	$21,$21,24
666	andi	$6,0xFF00
667	sll	$30,$30,8
668	or	$21,$25
669	or	$6,$30
670	or	$21,$6
671#endif
672#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
673	addu	$2,$31		# 13
674	xor	$25,$24,$1
675	rotr	$6,$3,27
676	and	$25,$7
677	addu	$2,$6
678#if defined(_MIPS_ARCH_MIPS32R6) || defined(_MIPS_ARCH_MIPS64R6)
679	 lw	$22,14*4($5)
680#else
681	 lwl	$22,14*4+3($5)
682	 lwr	$22,14*4+0($5)
683#endif
684	xor	$25,$1
685	addu	$2,$21
686	rotr	$7,$7,2
687	addu	$2,$25
688#else
689	 lwl	$22,14*4+3($5)
690	sll	$25,$3,5	# 13
691	addu	$2,$31
692	 lwr	$22,14*4+0($5)
693	srl	$6,$3,27
694	addu	$2,$25
695	xor	$25,$24,$1
696	addu	$2,$6
697	sll	$30,$7,30
698	and	$25,$7
699	srl	$7,$7,2
700	xor	$25,$1
701	addu	$2,$21
702	or	$7,$30
703	addu	$2,$25
704#endif
705#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
706	wsbh	$22,$22	# byte swap(14)
707	rotr	$22,$22,16
708#else
709	srl	$25,$22,24	# byte swap(14)
710	srl	$6,$22,8
711	andi	$30,$22,0xFF00
712	sll	$22,$22,24
713	andi	$6,0xFF00
714	sll	$30,$30,8
715	or	$22,$25
716	or	$6,$30
717	or	$22,$6
718#endif
719#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
720	addu	$1,$31		# 14
721	xor	$25,$7,$24
722	rotr	$6,$2,27
723	and	$25,$3
724	addu	$1,$6
725#if defined(_MIPS_ARCH_MIPS32R6) || defined(_MIPS_ARCH_MIPS64R6)
726	 lw	$23,15*4($5)
727#else
728	 lwl	$23,15*4+3($5)
729	 lwr	$23,15*4+0($5)
730#endif
731	xor	$25,$24
732	addu	$1,$22
733	rotr	$3,$3,2
734	addu	$1,$25
735#else
736	 lwl	$23,15*4+3($5)
737	sll	$25,$2,5	# 14
738	addu	$1,$31
739	 lwr	$23,15*4+0($5)
740	srl	$6,$2,27
741	addu	$1,$25
742	xor	$25,$7,$24
743	addu	$1,$6
744	sll	$30,$3,30
745	and	$25,$3
746	srl	$3,$3,2
747	xor	$25,$24
748	addu	$1,$22
749	or	$3,$30
750	addu	$1,$25
751#endif
752#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
753	wsbh	$23,$23	# byte swap(15)
754	rotr	$23,$23,16
755#else
756	srl	$25,$23,24	# byte swap(15)
757	srl	$6,$23,8
758	andi	$30,$23,0xFF00
759	sll	$23,$23,24
760	andi	$6,0xFF00
761	sll	$30,$30,8
762	or	$23,$25
763	or	$23,$6
764	or	$23,$30
765#endif
766#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
767	addu	$24,$31		# 15
768	 xor	$8,$10
769	xor	$25,$3,$7
770	rotr	$6,$1,27
771	 xor	$8,$16
772	and	$25,$2
773	addu	$24,$6
774	 xor	$8,$21
775	xor	$25,$7
776	addu	$24,$23
777	 rotr	$8,$8,31
778	rotr	$2,$2,2
779	addu	$24,$25
780#else
781	 xor	$8,$10
782	sll	$25,$1,5	# 15
783	addu	$24,$31
784	srl	$6,$1,27
785	addu	$24,$25
786	 xor	$8,$16
787	xor	$25,$3,$7
788	addu	$24,$6
789	 xor	$8,$21
790	sll	$30,$2,30
791	and	$25,$2
792	 srl	$6,$8,31
793	 addu	$8,$8
794	srl	$2,$2,2
795	xor	$25,$7
796	 or	$8,$6
797	addu	$24,$23
798	or	$2,$30
799	addu	$24,$25
800#endif
801#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
802	addu	$7,$31		# 16
803	 xor	$9,$11
804	xor	$25,$2,$3
805	rotr	$6,$24,27
806	 xor	$9,$17
807	and	$25,$1
808	addu	$7,$6
809	 xor	$9,$22
810	xor	$25,$3
811	addu	$7,$8
812	 rotr	$9,$9,31
813	rotr	$1,$1,2
814	addu	$7,$25
815#else
816	 xor	$9,$11
817	sll	$25,$24,5	# 16
818	addu	$7,$31
819	srl	$6,$24,27
820	addu	$7,$25
821	 xor	$9,$17
822	xor	$25,$2,$3
823	addu	$7,$6
824	 xor	$9,$22
825	sll	$30,$1,30
826	and	$25,$1
827	 srl	$6,$9,31
828	 addu	$9,$9
829	srl	$1,$1,2
830	xor	$25,$3
831	 or	$9,$6
832	addu	$7,$8
833	or	$1,$30
834	addu	$7,$25
835#endif
836#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
837	addu	$3,$31		# 17
838	 xor	$10,$12
839	xor	$25,$1,$2
840	rotr	$6,$7,27
841	 xor	$10,$18
842	and	$25,$24
843	addu	$3,$6
844	 xor	$10,$23
845	xor	$25,$2
846	addu	$3,$9
847	 rotr	$10,$10,31
848	rotr	$24,$24,2
849	addu	$3,$25
850#else
851	 xor	$10,$12
852	sll	$25,$7,5	# 17
853	addu	$3,$31
854	srl	$6,$7,27
855	addu	$3,$25
856	 xor	$10,$18
857	xor	$25,$1,$2
858	addu	$3,$6
859	 xor	$10,$23
860	sll	$30,$24,30
861	and	$25,$24
862	 srl	$6,$10,31
863	 addu	$10,$10
864	srl	$24,$24,2
865	xor	$25,$2
866	 or	$10,$6
867	addu	$3,$9
868	or	$24,$30
869	addu	$3,$25
870#endif
871#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
872	addu	$2,$31		# 18
873	 xor	$11,$13
874	xor	$25,$24,$1
875	rotr	$6,$3,27
876	 xor	$11,$19
877	and	$25,$7
878	addu	$2,$6
879	 xor	$11,$8
880	xor	$25,$1
881	addu	$2,$10
882	 rotr	$11,$11,31
883	rotr	$7,$7,2
884	addu	$2,$25
885#else
886	 xor	$11,$13
887	sll	$25,$3,5	# 18
888	addu	$2,$31
889	srl	$6,$3,27
890	addu	$2,$25
891	 xor	$11,$19
892	xor	$25,$24,$1
893	addu	$2,$6
894	 xor	$11,$8
895	sll	$30,$7,30
896	and	$25,$7
897	 srl	$6,$11,31
898	 addu	$11,$11
899	srl	$7,$7,2
900	xor	$25,$1
901	 or	$11,$6
902	addu	$2,$10
903	or	$7,$30
904	addu	$2,$25
905#endif
906#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
907	addu	$1,$31		# 19
908	 xor	$12,$14
909	xor	$25,$7,$24
910	rotr	$6,$2,27
911	 xor	$12,$20
912	and	$25,$3
913	addu	$1,$6
914	 xor	$12,$9
915	xor	$25,$24
916	addu	$1,$11
917	 rotr	$12,$12,31
918	rotr	$3,$3,2
919	addu	$1,$25
920#else
921	 xor	$12,$14
922	sll	$25,$2,5	# 19
923	addu	$1,$31
924	srl	$6,$2,27
925	addu	$1,$25
926	 xor	$12,$20
927	xor	$25,$7,$24
928	addu	$1,$6
929	 xor	$12,$9
930	sll	$30,$3,30
931	and	$25,$3
932	 srl	$6,$12,31
933	 addu	$12,$12
934	srl	$3,$3,2
935	xor	$25,$24
936	 or	$12,$6
937	addu	$1,$11
938	or	$3,$30
939	addu	$1,$25
940#endif
941	lui	$31,0x6ed9
942	ori	$31,0xeba1	# K_20_39
943#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
944	 xor	$13,$15
945	addu	$24,$31		# 20
946	rotr	$6,$1,27
947	 xor	$13,$21
948	xor	$25,$3,$7
949	addu	$24,$6
950	 xor	$13,$10
951	xor	$25,$2
952	addu	$24,$12
953	 rotr	$13,$13,31
954	rotr	$2,$2,2
955	addu	$24,$25
956#else
957	 xor	$13,$15
958	sll	$25,$1,5	# 20
959	addu	$24,$31
960	srl	$6,$1,27
961	addu	$24,$25
962	 xor	$13,$21
963	xor	$25,$3,$7
964	addu	$24,$6
965	 xor	$13,$10
966	sll	$30,$2,30
967	xor	$25,$2
968	 srl	$6,$13,31
969	 addu	$13,$13
970	srl	$2,$2,2
971	addu	$24,$12
972	 or	$13,$6
973	or	$2,$30
974	addu	$24,$25
975#endif
976#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
977	 xor	$14,$16
978	addu	$7,$31		# 21
979	rotr	$6,$24,27
980	 xor	$14,$22
981	xor	$25,$2,$3
982	addu	$7,$6
983	 xor	$14,$11
984	xor	$25,$1
985	addu	$7,$13
986	 rotr	$14,$14,31
987	rotr	$1,$1,2
988	addu	$7,$25
989#else
990	 xor	$14,$16
991	sll	$25,$24,5	# 21
992	addu	$7,$31
993	srl	$6,$24,27
994	addu	$7,$25
995	 xor	$14,$22
996	xor	$25,$2,$3
997	addu	$7,$6
998	 xor	$14,$11
999	sll	$30,$1,30
1000	xor	$25,$1
1001	 srl	$6,$14,31
1002	 addu	$14,$14
1003	srl	$1,$1,2
1004	addu	$7,$13
1005	 or	$14,$6
1006	or	$1,$30
1007	addu	$7,$25
1008#endif
1009#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
1010	 xor	$15,$17
1011	addu	$3,$31		# 22
1012	rotr	$6,$7,27
1013	 xor	$15,$23
1014	xor	$25,$1,$2
1015	addu	$3,$6
1016	 xor	$15,$12
1017	xor	$25,$24
1018	addu	$3,$14
1019	 rotr	$15,$15,31
1020	rotr	$24,$24,2
1021	addu	$3,$25
1022#else
1023	 xor	$15,$17
1024	sll	$25,$7,5	# 22
1025	addu	$3,$31
1026	srl	$6,$7,27
1027	addu	$3,$25
1028	 xor	$15,$23
1029	xor	$25,$1,$2
1030	addu	$3,$6
1031	 xor	$15,$12
1032	sll	$30,$24,30
1033	xor	$25,$24
1034	 srl	$6,$15,31
1035	 addu	$15,$15
1036	srl	$24,$24,2
1037	addu	$3,$14
1038	 or	$15,$6
1039	or	$24,$30
1040	addu	$3,$25
1041#endif
1042#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
1043	 xor	$16,$18
1044	addu	$2,$31		# 23
1045	rotr	$6,$3,27
1046	 xor	$16,$8
1047	xor	$25,$24,$1
1048	addu	$2,$6
1049	 xor	$16,$13
1050	xor	$25,$7
1051	addu	$2,$15
1052	 rotr	$16,$16,31
1053	rotr	$7,$7,2
1054	addu	$2,$25
1055#else
1056	 xor	$16,$18
1057	sll	$25,$3,5	# 23
1058	addu	$2,$31
1059	srl	$6,$3,27
1060	addu	$2,$25
1061	 xor	$16,$8
1062	xor	$25,$24,$1
1063	addu	$2,$6
1064	 xor	$16,$13
1065	sll	$30,$7,30
1066	xor	$25,$7
1067	 srl	$6,$16,31
1068	 addu	$16,$16
1069	srl	$7,$7,2
1070	addu	$2,$15
1071	 or	$16,$6
1072	or	$7,$30
1073	addu	$2,$25
1074#endif
1075#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
1076	 xor	$17,$19
1077	addu	$1,$31		# 24
1078	rotr	$6,$2,27
1079	 xor	$17,$9
1080	xor	$25,$7,$24
1081	addu	$1,$6
1082	 xor	$17,$14
1083	xor	$25,$3
1084	addu	$1,$16
1085	 rotr	$17,$17,31
1086	rotr	$3,$3,2
1087	addu	$1,$25
1088#else
1089	 xor	$17,$19
1090	sll	$25,$2,5	# 24
1091	addu	$1,$31
1092	srl	$6,$2,27
1093	addu	$1,$25
1094	 xor	$17,$9
1095	xor	$25,$7,$24
1096	addu	$1,$6
1097	 xor	$17,$14
1098	sll	$30,$3,30
1099	xor	$25,$3
1100	 srl	$6,$17,31
1101	 addu	$17,$17
1102	srl	$3,$3,2
1103	addu	$1,$16
1104	 or	$17,$6
1105	or	$3,$30
1106	addu	$1,$25
1107#endif
1108#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
1109	 xor	$18,$20
1110	addu	$24,$31		# 25
1111	rotr	$6,$1,27
1112	 xor	$18,$10
1113	xor	$25,$3,$7
1114	addu	$24,$6
1115	 xor	$18,$15
1116	xor	$25,$2
1117	addu	$24,$17
1118	 rotr	$18,$18,31
1119	rotr	$2,$2,2
1120	addu	$24,$25
1121#else
1122	 xor	$18,$20
1123	sll	$25,$1,5	# 25
1124	addu	$24,$31
1125	srl	$6,$1,27
1126	addu	$24,$25
1127	 xor	$18,$10
1128	xor	$25,$3,$7
1129	addu	$24,$6
1130	 xor	$18,$15
1131	sll	$30,$2,30
1132	xor	$25,$2
1133	 srl	$6,$18,31
1134	 addu	$18,$18
1135	srl	$2,$2,2
1136	addu	$24,$17
1137	 or	$18,$6
1138	or	$2,$30
1139	addu	$24,$25
1140#endif
1141#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
1142	 xor	$19,$21
1143	addu	$7,$31		# 26
1144	rotr	$6,$24,27
1145	 xor	$19,$11
1146	xor	$25,$2,$3
1147	addu	$7,$6
1148	 xor	$19,$16
1149	xor	$25,$1
1150	addu	$7,$18
1151	 rotr	$19,$19,31
1152	rotr	$1,$1,2
1153	addu	$7,$25
1154#else
1155	 xor	$19,$21
1156	sll	$25,$24,5	# 26
1157	addu	$7,$31
1158	srl	$6,$24,27
1159	addu	$7,$25
1160	 xor	$19,$11
1161	xor	$25,$2,$3
1162	addu	$7,$6
1163	 xor	$19,$16
1164	sll	$30,$1,30
1165	xor	$25,$1
1166	 srl	$6,$19,31
1167	 addu	$19,$19
1168	srl	$1,$1,2
1169	addu	$7,$18
1170	 or	$19,$6
1171	or	$1,$30
1172	addu	$7,$25
1173#endif
1174#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
1175	 xor	$20,$22
1176	addu	$3,$31		# 27
1177	rotr	$6,$7,27
1178	 xor	$20,$12
1179	xor	$25,$1,$2
1180	addu	$3,$6
1181	 xor	$20,$17
1182	xor	$25,$24
1183	addu	$3,$19
1184	 rotr	$20,$20,31
1185	rotr	$24,$24,2
1186	addu	$3,$25
1187#else
1188	 xor	$20,$22
1189	sll	$25,$7,5	# 27
1190	addu	$3,$31
1191	srl	$6,$7,27
1192	addu	$3,$25
1193	 xor	$20,$12
1194	xor	$25,$1,$2
1195	addu	$3,$6
1196	 xor	$20,$17
1197	sll	$30,$24,30
1198	xor	$25,$24
1199	 srl	$6,$20,31
1200	 addu	$20,$20
1201	srl	$24,$24,2
1202	addu	$3,$19
1203	 or	$20,$6
1204	or	$24,$30
1205	addu	$3,$25
1206#endif
1207#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
1208	 xor	$21,$23
1209	addu	$2,$31		# 28
1210	rotr	$6,$3,27
1211	 xor	$21,$13
1212	xor	$25,$24,$1
1213	addu	$2,$6
1214	 xor	$21,$18
1215	xor	$25,$7
1216	addu	$2,$20
1217	 rotr	$21,$21,31
1218	rotr	$7,$7,2
1219	addu	$2,$25
1220#else
1221	 xor	$21,$23
1222	sll	$25,$3,5	# 28
1223	addu	$2,$31
1224	srl	$6,$3,27
1225	addu	$2,$25
1226	 xor	$21,$13
1227	xor	$25,$24,$1
1228	addu	$2,$6
1229	 xor	$21,$18
1230	sll	$30,$7,30
1231	xor	$25,$7
1232	 srl	$6,$21,31
1233	 addu	$21,$21
1234	srl	$7,$7,2
1235	addu	$2,$20
1236	 or	$21,$6
1237	or	$7,$30
1238	addu	$2,$25
1239#endif
1240#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
1241	 xor	$22,$8
1242	addu	$1,$31		# 29
1243	rotr	$6,$2,27
1244	 xor	$22,$14
1245	xor	$25,$7,$24
1246	addu	$1,$6
1247	 xor	$22,$19
1248	xor	$25,$3
1249	addu	$1,$21
1250	 rotr	$22,$22,31
1251	rotr	$3,$3,2
1252	addu	$1,$25
1253#else
1254	 xor	$22,$8
1255	sll	$25,$2,5	# 29
1256	addu	$1,$31
1257	srl	$6,$2,27
1258	addu	$1,$25
1259	 xor	$22,$14
1260	xor	$25,$7,$24
1261	addu	$1,$6
1262	 xor	$22,$19
1263	sll	$30,$3,30
1264	xor	$25,$3
1265	 srl	$6,$22,31
1266	 addu	$22,$22
1267	srl	$3,$3,2
1268	addu	$1,$21
1269	 or	$22,$6
1270	or	$3,$30
1271	addu	$1,$25
1272#endif
1273#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
1274	 xor	$23,$9
1275	addu	$24,$31		# 30
1276	rotr	$6,$1,27
1277	 xor	$23,$15
1278	xor	$25,$3,$7
1279	addu	$24,$6
1280	 xor	$23,$20
1281	xor	$25,$2
1282	addu	$24,$22
1283	 rotr	$23,$23,31
1284	rotr	$2,$2,2
1285	addu	$24,$25
1286#else
1287	 xor	$23,$9
1288	sll	$25,$1,5	# 30
1289	addu	$24,$31
1290	srl	$6,$1,27
1291	addu	$24,$25
1292	 xor	$23,$15
1293	xor	$25,$3,$7
1294	addu	$24,$6
1295	 xor	$23,$20
1296	sll	$30,$2,30
1297	xor	$25,$2
1298	 srl	$6,$23,31
1299	 addu	$23,$23
1300	srl	$2,$2,2
1301	addu	$24,$22
1302	 or	$23,$6
1303	or	$2,$30
1304	addu	$24,$25
1305#endif
1306#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
1307	 xor	$8,$10
1308	addu	$7,$31		# 31
1309	rotr	$6,$24,27
1310	 xor	$8,$16
1311	xor	$25,$2,$3
1312	addu	$7,$6
1313	 xor	$8,$21
1314	xor	$25,$1
1315	addu	$7,$23
1316	 rotr	$8,$8,31
1317	rotr	$1,$1,2
1318	addu	$7,$25
1319#else
1320	 xor	$8,$10
1321	sll	$25,$24,5	# 31
1322	addu	$7,$31
1323	srl	$6,$24,27
1324	addu	$7,$25
1325	 xor	$8,$16
1326	xor	$25,$2,$3
1327	addu	$7,$6
1328	 xor	$8,$21
1329	sll	$30,$1,30
1330	xor	$25,$1
1331	 srl	$6,$8,31
1332	 addu	$8,$8
1333	srl	$1,$1,2
1334	addu	$7,$23
1335	 or	$8,$6
1336	or	$1,$30
1337	addu	$7,$25
1338#endif
1339#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
1340	 xor	$9,$11
1341	addu	$3,$31		# 32
1342	rotr	$6,$7,27
1343	 xor	$9,$17
1344	xor	$25,$1,$2
1345	addu	$3,$6
1346	 xor	$9,$22
1347	xor	$25,$24
1348	addu	$3,$8
1349	 rotr	$9,$9,31
1350	rotr	$24,$24,2
1351	addu	$3,$25
1352#else
1353	 xor	$9,$11
1354	sll	$25,$7,5	# 32
1355	addu	$3,$31
1356	srl	$6,$7,27
1357	addu	$3,$25
1358	 xor	$9,$17
1359	xor	$25,$1,$2
1360	addu	$3,$6
1361	 xor	$9,$22
1362	sll	$30,$24,30
1363	xor	$25,$24
1364	 srl	$6,$9,31
1365	 addu	$9,$9
1366	srl	$24,$24,2
1367	addu	$3,$8
1368	 or	$9,$6
1369	or	$24,$30
1370	addu	$3,$25
1371#endif
1372#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
1373	 xor	$10,$12
1374	addu	$2,$31		# 33
1375	rotr	$6,$3,27
1376	 xor	$10,$18
1377	xor	$25,$24,$1
1378	addu	$2,$6
1379	 xor	$10,$23
1380	xor	$25,$7
1381	addu	$2,$9
1382	 rotr	$10,$10,31
1383	rotr	$7,$7,2
1384	addu	$2,$25
1385#else
1386	 xor	$10,$12
1387	sll	$25,$3,5	# 33
1388	addu	$2,$31
1389	srl	$6,$3,27
1390	addu	$2,$25
1391	 xor	$10,$18
1392	xor	$25,$24,$1
1393	addu	$2,$6
1394	 xor	$10,$23
1395	sll	$30,$7,30
1396	xor	$25,$7
1397	 srl	$6,$10,31
1398	 addu	$10,$10
1399	srl	$7,$7,2
1400	addu	$2,$9
1401	 or	$10,$6
1402	or	$7,$30
1403	addu	$2,$25
1404#endif
1405#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
1406	 xor	$11,$13
1407	addu	$1,$31		# 34
1408	rotr	$6,$2,27
1409	 xor	$11,$19
1410	xor	$25,$7,$24
1411	addu	$1,$6
1412	 xor	$11,$8
1413	xor	$25,$3
1414	addu	$1,$10
1415	 rotr	$11,$11,31
1416	rotr	$3,$3,2
1417	addu	$1,$25
1418#else
1419	 xor	$11,$13
1420	sll	$25,$2,5	# 34
1421	addu	$1,$31
1422	srl	$6,$2,27
1423	addu	$1,$25
1424	 xor	$11,$19
1425	xor	$25,$7,$24
1426	addu	$1,$6
1427	 xor	$11,$8
1428	sll	$30,$3,30
1429	xor	$25,$3
1430	 srl	$6,$11,31
1431	 addu	$11,$11
1432	srl	$3,$3,2
1433	addu	$1,$10
1434	 or	$11,$6
1435	or	$3,$30
1436	addu	$1,$25
1437#endif
1438#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
1439	 xor	$12,$14
1440	addu	$24,$31		# 35
1441	rotr	$6,$1,27
1442	 xor	$12,$20
1443	xor	$25,$3,$7
1444	addu	$24,$6
1445	 xor	$12,$9
1446	xor	$25,$2
1447	addu	$24,$11
1448	 rotr	$12,$12,31
1449	rotr	$2,$2,2
1450	addu	$24,$25
1451#else
1452	 xor	$12,$14
1453	sll	$25,$1,5	# 35
1454	addu	$24,$31
1455	srl	$6,$1,27
1456	addu	$24,$25
1457	 xor	$12,$20
1458	xor	$25,$3,$7
1459	addu	$24,$6
1460	 xor	$12,$9
1461	sll	$30,$2,30
1462	xor	$25,$2
1463	 srl	$6,$12,31
1464	 addu	$12,$12
1465	srl	$2,$2,2
1466	addu	$24,$11
1467	 or	$12,$6
1468	or	$2,$30
1469	addu	$24,$25
1470#endif
1471#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
1472	 xor	$13,$15
1473	addu	$7,$31		# 36
1474	rotr	$6,$24,27
1475	 xor	$13,$21
1476	xor	$25,$2,$3
1477	addu	$7,$6
1478	 xor	$13,$10
1479	xor	$25,$1
1480	addu	$7,$12
1481	 rotr	$13,$13,31
1482	rotr	$1,$1,2
1483	addu	$7,$25
1484#else
1485	 xor	$13,$15
1486	sll	$25,$24,5	# 36
1487	addu	$7,$31
1488	srl	$6,$24,27
1489	addu	$7,$25
1490	 xor	$13,$21
1491	xor	$25,$2,$3
1492	addu	$7,$6
1493	 xor	$13,$10
1494	sll	$30,$1,30
1495	xor	$25,$1
1496	 srl	$6,$13,31
1497	 addu	$13,$13
1498	srl	$1,$1,2
1499	addu	$7,$12
1500	 or	$13,$6
1501	or	$1,$30
1502	addu	$7,$25
1503#endif
1504#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
1505	 xor	$14,$16
1506	addu	$3,$31		# 37
1507	rotr	$6,$7,27
1508	 xor	$14,$22
1509	xor	$25,$1,$2
1510	addu	$3,$6
1511	 xor	$14,$11
1512	xor	$25,$24
1513	addu	$3,$13
1514	 rotr	$14,$14,31
1515	rotr	$24,$24,2
1516	addu	$3,$25
1517#else
1518	 xor	$14,$16
1519	sll	$25,$7,5	# 37
1520	addu	$3,$31
1521	srl	$6,$7,27
1522	addu	$3,$25
1523	 xor	$14,$22
1524	xor	$25,$1,$2
1525	addu	$3,$6
1526	 xor	$14,$11
1527	sll	$30,$24,30
1528	xor	$25,$24
1529	 srl	$6,$14,31
1530	 addu	$14,$14
1531	srl	$24,$24,2
1532	addu	$3,$13
1533	 or	$14,$6
1534	or	$24,$30
1535	addu	$3,$25
1536#endif
1537#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
1538	 xor	$15,$17
1539	addu	$2,$31		# 38
1540	rotr	$6,$3,27
1541	 xor	$15,$23
1542	xor	$25,$24,$1
1543	addu	$2,$6
1544	 xor	$15,$12
1545	xor	$25,$7
1546	addu	$2,$14
1547	 rotr	$15,$15,31
1548	rotr	$7,$7,2
1549	addu	$2,$25
1550#else
1551	 xor	$15,$17
1552	sll	$25,$3,5	# 38
1553	addu	$2,$31
1554	srl	$6,$3,27
1555	addu	$2,$25
1556	 xor	$15,$23
1557	xor	$25,$24,$1
1558	addu	$2,$6
1559	 xor	$15,$12
1560	sll	$30,$7,30
1561	xor	$25,$7
1562	 srl	$6,$15,31
1563	 addu	$15,$15
1564	srl	$7,$7,2
1565	addu	$2,$14
1566	 or	$15,$6
1567	or	$7,$30
1568	addu	$2,$25
1569#endif
1570#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
1571	 xor	$16,$18
1572	addu	$1,$31		# 39
1573	rotr	$6,$2,27
1574	 xor	$16,$8
1575	xor	$25,$7,$24
1576	addu	$1,$6
1577	 xor	$16,$13
1578	xor	$25,$3
1579	addu	$1,$15
1580	 rotr	$16,$16,31
1581	rotr	$3,$3,2
1582	addu	$1,$25
1583#else
1584	 xor	$16,$18
1585	sll	$25,$2,5	# 39
1586	addu	$1,$31
1587	srl	$6,$2,27
1588	addu	$1,$25
1589	 xor	$16,$8
1590	xor	$25,$7,$24
1591	addu	$1,$6
1592	 xor	$16,$13
1593	sll	$30,$3,30
1594	xor	$25,$3
1595	 srl	$6,$16,31
1596	 addu	$16,$16
1597	srl	$3,$3,2
1598	addu	$1,$15
1599	 or	$16,$6
1600	or	$3,$30
1601	addu	$1,$25
1602#endif
1603	lui	$31,0x8f1b
1604	ori	$31,0xbcdc	# K_40_59
1605#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
1606	addu	$24,$31		# 40
1607	and	$25,$3,$7
1608	 xor	$17,$19
1609	rotr	$6,$1,27
1610	addu	$24,$25
1611	 xor	$17,$9
1612	xor	$25,$3,$7
1613	addu	$24,$6
1614	 xor	$17,$14
1615	and	$25,$2
1616	addu	$24,$16
1617	 rotr	$17,$17,31
1618	rotr	$2,$2,2
1619	addu	$24,$25
1620#else
1621	 xor	$17,$19
1622	sll	$25,$1,5	# 40
1623	addu	$24,$31
1624	srl	$6,$1,27
1625	addu	$24,$25
1626	 xor	$17,$9
1627	and	$25,$3,$7
1628	addu	$24,$6
1629	 xor	$17,$14
1630	sll	$30,$2,30
1631	addu	$24,$25
1632	 srl	$6,$17,31
1633	xor	$25,$3,$7
1634	 addu	$17,$17
1635	and	$25,$2
1636	srl	$2,$2,2
1637	 or	$17,$6
1638	addu	$24,$16
1639	or	$2,$30
1640	addu	$24,$25
1641#endif
1642#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
1643	addu	$7,$31		# 41
1644	and	$25,$2,$3
1645	 xor	$18,$20
1646	rotr	$6,$24,27
1647	addu	$7,$25
1648	 xor	$18,$10
1649	xor	$25,$2,$3
1650	addu	$7,$6
1651	 xor	$18,$15
1652	and	$25,$1
1653	addu	$7,$17
1654	 rotr	$18,$18,31
1655	rotr	$1,$1,2
1656	addu	$7,$25
1657#else
1658	 xor	$18,$20
1659	sll	$25,$24,5	# 41
1660	addu	$7,$31
1661	srl	$6,$24,27
1662	addu	$7,$25
1663	 xor	$18,$10
1664	and	$25,$2,$3
1665	addu	$7,$6
1666	 xor	$18,$15
1667	sll	$30,$1,30
1668	addu	$7,$25
1669	 srl	$6,$18,31
1670	xor	$25,$2,$3
1671	 addu	$18,$18
1672	and	$25,$1
1673	srl	$1,$1,2
1674	 or	$18,$6
1675	addu	$7,$17
1676	or	$1,$30
1677	addu	$7,$25
1678#endif
1679#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
1680	addu	$3,$31		# 42
1681	and	$25,$1,$2
1682	 xor	$19,$21
1683	rotr	$6,$7,27
1684	addu	$3,$25
1685	 xor	$19,$11
1686	xor	$25,$1,$2
1687	addu	$3,$6
1688	 xor	$19,$16
1689	and	$25,$24
1690	addu	$3,$18
1691	 rotr	$19,$19,31
1692	rotr	$24,$24,2
1693	addu	$3,$25
1694#else
1695	 xor	$19,$21
1696	sll	$25,$7,5	# 42
1697	addu	$3,$31
1698	srl	$6,$7,27
1699	addu	$3,$25
1700	 xor	$19,$11
1701	and	$25,$1,$2
1702	addu	$3,$6
1703	 xor	$19,$16
1704	sll	$30,$24,30
1705	addu	$3,$25
1706	 srl	$6,$19,31
1707	xor	$25,$1,$2
1708	 addu	$19,$19
1709	and	$25,$24
1710	srl	$24,$24,2
1711	 or	$19,$6
1712	addu	$3,$18
1713	or	$24,$30
1714	addu	$3,$25
1715#endif
1716#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
1717	addu	$2,$31		# 43
1718	and	$25,$24,$1
1719	 xor	$20,$22
1720	rotr	$6,$3,27
1721	addu	$2,$25
1722	 xor	$20,$12
1723	xor	$25,$24,$1
1724	addu	$2,$6
1725	 xor	$20,$17
1726	and	$25,$7
1727	addu	$2,$19
1728	 rotr	$20,$20,31
1729	rotr	$7,$7,2
1730	addu	$2,$25
1731#else
1732	 xor	$20,$22
1733	sll	$25,$3,5	# 43
1734	addu	$2,$31
1735	srl	$6,$3,27
1736	addu	$2,$25
1737	 xor	$20,$12
1738	and	$25,$24,$1
1739	addu	$2,$6
1740	 xor	$20,$17
1741	sll	$30,$7,30
1742	addu	$2,$25
1743	 srl	$6,$20,31
1744	xor	$25,$24,$1
1745	 addu	$20,$20
1746	and	$25,$7
1747	srl	$7,$7,2
1748	 or	$20,$6
1749	addu	$2,$19
1750	or	$7,$30
1751	addu	$2,$25
1752#endif
1753#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
1754	addu	$1,$31		# 44
1755	and	$25,$7,$24
1756	 xor	$21,$23
1757	rotr	$6,$2,27
1758	addu	$1,$25
1759	 xor	$21,$13
1760	xor	$25,$7,$24
1761	addu	$1,$6
1762	 xor	$21,$18
1763	and	$25,$3
1764	addu	$1,$20
1765	 rotr	$21,$21,31
1766	rotr	$3,$3,2
1767	addu	$1,$25
1768#else
1769	 xor	$21,$23
1770	sll	$25,$2,5	# 44
1771	addu	$1,$31
1772	srl	$6,$2,27
1773	addu	$1,$25
1774	 xor	$21,$13
1775	and	$25,$7,$24
1776	addu	$1,$6
1777	 xor	$21,$18
1778	sll	$30,$3,30
1779	addu	$1,$25
1780	 srl	$6,$21,31
1781	xor	$25,$7,$24
1782	 addu	$21,$21
1783	and	$25,$3
1784	srl	$3,$3,2
1785	 or	$21,$6
1786	addu	$1,$20
1787	or	$3,$30
1788	addu	$1,$25
1789#endif
1790#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
1791	addu	$24,$31		# 45
1792	and	$25,$3,$7
1793	 xor	$22,$8
1794	rotr	$6,$1,27
1795	addu	$24,$25
1796	 xor	$22,$14
1797	xor	$25,$3,$7
1798	addu	$24,$6
1799	 xor	$22,$19
1800	and	$25,$2
1801	addu	$24,$21
1802	 rotr	$22,$22,31
1803	rotr	$2,$2,2
1804	addu	$24,$25
1805#else
1806	 xor	$22,$8
1807	sll	$25,$1,5	# 45
1808	addu	$24,$31
1809	srl	$6,$1,27
1810	addu	$24,$25
1811	 xor	$22,$14
1812	and	$25,$3,$7
1813	addu	$24,$6
1814	 xor	$22,$19
1815	sll	$30,$2,30
1816	addu	$24,$25
1817	 srl	$6,$22,31
1818	xor	$25,$3,$7
1819	 addu	$22,$22
1820	and	$25,$2
1821	srl	$2,$2,2
1822	 or	$22,$6
1823	addu	$24,$21
1824	or	$2,$30
1825	addu	$24,$25
1826#endif
1827#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
1828	addu	$7,$31		# 46
1829	and	$25,$2,$3
1830	 xor	$23,$9
1831	rotr	$6,$24,27
1832	addu	$7,$25
1833	 xor	$23,$15
1834	xor	$25,$2,$3
1835	addu	$7,$6
1836	 xor	$23,$20
1837	and	$25,$1
1838	addu	$7,$22
1839	 rotr	$23,$23,31
1840	rotr	$1,$1,2
1841	addu	$7,$25
1842#else
1843	 xor	$23,$9
1844	sll	$25,$24,5	# 46
1845	addu	$7,$31
1846	srl	$6,$24,27
1847	addu	$7,$25
1848	 xor	$23,$15
1849	and	$25,$2,$3
1850	addu	$7,$6
1851	 xor	$23,$20
1852	sll	$30,$1,30
1853	addu	$7,$25
1854	 srl	$6,$23,31
1855	xor	$25,$2,$3
1856	 addu	$23,$23
1857	and	$25,$1
1858	srl	$1,$1,2
1859	 or	$23,$6
1860	addu	$7,$22
1861	or	$1,$30
1862	addu	$7,$25
1863#endif
1864#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
1865	addu	$3,$31		# 47
1866	and	$25,$1,$2
1867	 xor	$8,$10
1868	rotr	$6,$7,27
1869	addu	$3,$25
1870	 xor	$8,$16
1871	xor	$25,$1,$2
1872	addu	$3,$6
1873	 xor	$8,$21
1874	and	$25,$24
1875	addu	$3,$23
1876	 rotr	$8,$8,31
1877	rotr	$24,$24,2
1878	addu	$3,$25
1879#else
1880	 xor	$8,$10
1881	sll	$25,$7,5	# 47
1882	addu	$3,$31
1883	srl	$6,$7,27
1884	addu	$3,$25
1885	 xor	$8,$16
1886	and	$25,$1,$2
1887	addu	$3,$6
1888	 xor	$8,$21
1889	sll	$30,$24,30
1890	addu	$3,$25
1891	 srl	$6,$8,31
1892	xor	$25,$1,$2
1893	 addu	$8,$8
1894	and	$25,$24
1895	srl	$24,$24,2
1896	 or	$8,$6
1897	addu	$3,$23
1898	or	$24,$30
1899	addu	$3,$25
1900#endif
1901#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
1902	addu	$2,$31		# 48
1903	and	$25,$24,$1
1904	 xor	$9,$11
1905	rotr	$6,$3,27
1906	addu	$2,$25
1907	 xor	$9,$17
1908	xor	$25,$24,$1
1909	addu	$2,$6
1910	 xor	$9,$22
1911	and	$25,$7
1912	addu	$2,$8
1913	 rotr	$9,$9,31
1914	rotr	$7,$7,2
1915	addu	$2,$25
1916#else
1917	 xor	$9,$11
1918	sll	$25,$3,5	# 48
1919	addu	$2,$31
1920	srl	$6,$3,27
1921	addu	$2,$25
1922	 xor	$9,$17
1923	and	$25,$24,$1
1924	addu	$2,$6
1925	 xor	$9,$22
1926	sll	$30,$7,30
1927	addu	$2,$25
1928	 srl	$6,$9,31
1929	xor	$25,$24,$1
1930	 addu	$9,$9
1931	and	$25,$7
1932	srl	$7,$7,2
1933	 or	$9,$6
1934	addu	$2,$8
1935	or	$7,$30
1936	addu	$2,$25
1937#endif
1938#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
1939	addu	$1,$31		# 49
1940	and	$25,$7,$24
1941	 xor	$10,$12
1942	rotr	$6,$2,27
1943	addu	$1,$25
1944	 xor	$10,$18
1945	xor	$25,$7,$24
1946	addu	$1,$6
1947	 xor	$10,$23
1948	and	$25,$3
1949	addu	$1,$9
1950	 rotr	$10,$10,31
1951	rotr	$3,$3,2
1952	addu	$1,$25
1953#else
1954	 xor	$10,$12
1955	sll	$25,$2,5	# 49
1956	addu	$1,$31
1957	srl	$6,$2,27
1958	addu	$1,$25
1959	 xor	$10,$18
1960	and	$25,$7,$24
1961	addu	$1,$6
1962	 xor	$10,$23
1963	sll	$30,$3,30
1964	addu	$1,$25
1965	 srl	$6,$10,31
1966	xor	$25,$7,$24
1967	 addu	$10,$10
1968	and	$25,$3
1969	srl	$3,$3,2
1970	 or	$10,$6
1971	addu	$1,$9
1972	or	$3,$30
1973	addu	$1,$25
1974#endif
1975#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
1976	addu	$24,$31		# 50
1977	and	$25,$3,$7
1978	 xor	$11,$13
1979	rotr	$6,$1,27
1980	addu	$24,$25
1981	 xor	$11,$19
1982	xor	$25,$3,$7
1983	addu	$24,$6
1984	 xor	$11,$8
1985	and	$25,$2
1986	addu	$24,$10
1987	 rotr	$11,$11,31
1988	rotr	$2,$2,2
1989	addu	$24,$25
1990#else
1991	 xor	$11,$13
1992	sll	$25,$1,5	# 50
1993	addu	$24,$31
1994	srl	$6,$1,27
1995	addu	$24,$25
1996	 xor	$11,$19
1997	and	$25,$3,$7
1998	addu	$24,$6
1999	 xor	$11,$8
2000	sll	$30,$2,30
2001	addu	$24,$25
2002	 srl	$6,$11,31
2003	xor	$25,$3,$7
2004	 addu	$11,$11
2005	and	$25,$2
2006	srl	$2,$2,2
2007	 or	$11,$6
2008	addu	$24,$10
2009	or	$2,$30
2010	addu	$24,$25
2011#endif
2012#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
2013	addu	$7,$31		# 51
2014	and	$25,$2,$3
2015	 xor	$12,$14
2016	rotr	$6,$24,27
2017	addu	$7,$25
2018	 xor	$12,$20
2019	xor	$25,$2,$3
2020	addu	$7,$6
2021	 xor	$12,$9
2022	and	$25,$1
2023	addu	$7,$11
2024	 rotr	$12,$12,31
2025	rotr	$1,$1,2
2026	addu	$7,$25
2027#else
2028	 xor	$12,$14
2029	sll	$25,$24,5	# 51
2030	addu	$7,$31
2031	srl	$6,$24,27
2032	addu	$7,$25
2033	 xor	$12,$20
2034	and	$25,$2,$3
2035	addu	$7,$6
2036	 xor	$12,$9
2037	sll	$30,$1,30
2038	addu	$7,$25
2039	 srl	$6,$12,31
2040	xor	$25,$2,$3
2041	 addu	$12,$12
2042	and	$25,$1
2043	srl	$1,$1,2
2044	 or	$12,$6
2045	addu	$7,$11
2046	or	$1,$30
2047	addu	$7,$25
2048#endif
2049#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
2050	addu	$3,$31		# 52
2051	and	$25,$1,$2
2052	 xor	$13,$15
2053	rotr	$6,$7,27
2054	addu	$3,$25
2055	 xor	$13,$21
2056	xor	$25,$1,$2
2057	addu	$3,$6
2058	 xor	$13,$10
2059	and	$25,$24
2060	addu	$3,$12
2061	 rotr	$13,$13,31
2062	rotr	$24,$24,2
2063	addu	$3,$25
2064#else
2065	 xor	$13,$15
2066	sll	$25,$7,5	# 52
2067	addu	$3,$31
2068	srl	$6,$7,27
2069	addu	$3,$25
2070	 xor	$13,$21
2071	and	$25,$1,$2
2072	addu	$3,$6
2073	 xor	$13,$10
2074	sll	$30,$24,30
2075	addu	$3,$25
2076	 srl	$6,$13,31
2077	xor	$25,$1,$2
2078	 addu	$13,$13
2079	and	$25,$24
2080	srl	$24,$24,2
2081	 or	$13,$6
2082	addu	$3,$12
2083	or	$24,$30
2084	addu	$3,$25
2085#endif
2086#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
2087	addu	$2,$31		# 53
2088	and	$25,$24,$1
2089	 xor	$14,$16
2090	rotr	$6,$3,27
2091	addu	$2,$25
2092	 xor	$14,$22
2093	xor	$25,$24,$1
2094	addu	$2,$6
2095	 xor	$14,$11
2096	and	$25,$7
2097	addu	$2,$13
2098	 rotr	$14,$14,31
2099	rotr	$7,$7,2
2100	addu	$2,$25
2101#else
2102	 xor	$14,$16
2103	sll	$25,$3,5	# 53
2104	addu	$2,$31
2105	srl	$6,$3,27
2106	addu	$2,$25
2107	 xor	$14,$22
2108	and	$25,$24,$1
2109	addu	$2,$6
2110	 xor	$14,$11
2111	sll	$30,$7,30
2112	addu	$2,$25
2113	 srl	$6,$14,31
2114	xor	$25,$24,$1
2115	 addu	$14,$14
2116	and	$25,$7
2117	srl	$7,$7,2
2118	 or	$14,$6
2119	addu	$2,$13
2120	or	$7,$30
2121	addu	$2,$25
2122#endif
2123#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
2124	addu	$1,$31		# 54
2125	and	$25,$7,$24
2126	 xor	$15,$17
2127	rotr	$6,$2,27
2128	addu	$1,$25
2129	 xor	$15,$23
2130	xor	$25,$7,$24
2131	addu	$1,$6
2132	 xor	$15,$12
2133	and	$25,$3
2134	addu	$1,$14
2135	 rotr	$15,$15,31
2136	rotr	$3,$3,2
2137	addu	$1,$25
2138#else
2139	 xor	$15,$17
2140	sll	$25,$2,5	# 54
2141	addu	$1,$31
2142	srl	$6,$2,27
2143	addu	$1,$25
2144	 xor	$15,$23
2145	and	$25,$7,$24
2146	addu	$1,$6
2147	 xor	$15,$12
2148	sll	$30,$3,30
2149	addu	$1,$25
2150	 srl	$6,$15,31
2151	xor	$25,$7,$24
2152	 addu	$15,$15
2153	and	$25,$3
2154	srl	$3,$3,2
2155	 or	$15,$6
2156	addu	$1,$14
2157	or	$3,$30
2158	addu	$1,$25
2159#endif
2160#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
2161	addu	$24,$31		# 55
2162	and	$25,$3,$7
2163	 xor	$16,$18
2164	rotr	$6,$1,27
2165	addu	$24,$25
2166	 xor	$16,$8
2167	xor	$25,$3,$7
2168	addu	$24,$6
2169	 xor	$16,$13
2170	and	$25,$2
2171	addu	$24,$15
2172	 rotr	$16,$16,31
2173	rotr	$2,$2,2
2174	addu	$24,$25
2175#else
2176	 xor	$16,$18
2177	sll	$25,$1,5	# 55
2178	addu	$24,$31
2179	srl	$6,$1,27
2180	addu	$24,$25
2181	 xor	$16,$8
2182	and	$25,$3,$7
2183	addu	$24,$6
2184	 xor	$16,$13
2185	sll	$30,$2,30
2186	addu	$24,$25
2187	 srl	$6,$16,31
2188	xor	$25,$3,$7
2189	 addu	$16,$16
2190	and	$25,$2
2191	srl	$2,$2,2
2192	 or	$16,$6
2193	addu	$24,$15
2194	or	$2,$30
2195	addu	$24,$25
2196#endif
2197#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
2198	addu	$7,$31		# 56
2199	and	$25,$2,$3
2200	 xor	$17,$19
2201	rotr	$6,$24,27
2202	addu	$7,$25
2203	 xor	$17,$9
2204	xor	$25,$2,$3
2205	addu	$7,$6
2206	 xor	$17,$14
2207	and	$25,$1
2208	addu	$7,$16
2209	 rotr	$17,$17,31
2210	rotr	$1,$1,2
2211	addu	$7,$25
2212#else
2213	 xor	$17,$19
2214	sll	$25,$24,5	# 56
2215	addu	$7,$31
2216	srl	$6,$24,27
2217	addu	$7,$25
2218	 xor	$17,$9
2219	and	$25,$2,$3
2220	addu	$7,$6
2221	 xor	$17,$14
2222	sll	$30,$1,30
2223	addu	$7,$25
2224	 srl	$6,$17,31
2225	xor	$25,$2,$3
2226	 addu	$17,$17
2227	and	$25,$1
2228	srl	$1,$1,2
2229	 or	$17,$6
2230	addu	$7,$16
2231	or	$1,$30
2232	addu	$7,$25
2233#endif
2234#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
2235	addu	$3,$31		# 57
2236	and	$25,$1,$2
2237	 xor	$18,$20
2238	rotr	$6,$7,27
2239	addu	$3,$25
2240	 xor	$18,$10
2241	xor	$25,$1,$2
2242	addu	$3,$6
2243	 xor	$18,$15
2244	and	$25,$24
2245	addu	$3,$17
2246	 rotr	$18,$18,31
2247	rotr	$24,$24,2
2248	addu	$3,$25
2249#else
2250	 xor	$18,$20
2251	sll	$25,$7,5	# 57
2252	addu	$3,$31
2253	srl	$6,$7,27
2254	addu	$3,$25
2255	 xor	$18,$10
2256	and	$25,$1,$2
2257	addu	$3,$6
2258	 xor	$18,$15
2259	sll	$30,$24,30
2260	addu	$3,$25
2261	 srl	$6,$18,31
2262	xor	$25,$1,$2
2263	 addu	$18,$18
2264	and	$25,$24
2265	srl	$24,$24,2
2266	 or	$18,$6
2267	addu	$3,$17
2268	or	$24,$30
2269	addu	$3,$25
2270#endif
2271#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
2272	addu	$2,$31		# 58
2273	and	$25,$24,$1
2274	 xor	$19,$21
2275	rotr	$6,$3,27
2276	addu	$2,$25
2277	 xor	$19,$11
2278	xor	$25,$24,$1
2279	addu	$2,$6
2280	 xor	$19,$16
2281	and	$25,$7
2282	addu	$2,$18
2283	 rotr	$19,$19,31
2284	rotr	$7,$7,2
2285	addu	$2,$25
2286#else
2287	 xor	$19,$21
2288	sll	$25,$3,5	# 58
2289	addu	$2,$31
2290	srl	$6,$3,27
2291	addu	$2,$25
2292	 xor	$19,$11
2293	and	$25,$24,$1
2294	addu	$2,$6
2295	 xor	$19,$16
2296	sll	$30,$7,30
2297	addu	$2,$25
2298	 srl	$6,$19,31
2299	xor	$25,$24,$1
2300	 addu	$19,$19
2301	and	$25,$7
2302	srl	$7,$7,2
2303	 or	$19,$6
2304	addu	$2,$18
2305	or	$7,$30
2306	addu	$2,$25
2307#endif
2308#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
2309	addu	$1,$31		# 59
2310	and	$25,$7,$24
2311	 xor	$20,$22
2312	rotr	$6,$2,27
2313	addu	$1,$25
2314	 xor	$20,$12
2315	xor	$25,$7,$24
2316	addu	$1,$6
2317	 xor	$20,$17
2318	and	$25,$3
2319	addu	$1,$19
2320	 rotr	$20,$20,31
2321	rotr	$3,$3,2
2322	addu	$1,$25
2323#else
2324	 xor	$20,$22
2325	sll	$25,$2,5	# 59
2326	addu	$1,$31
2327	srl	$6,$2,27
2328	addu	$1,$25
2329	 xor	$20,$12
2330	and	$25,$7,$24
2331	addu	$1,$6
2332	 xor	$20,$17
2333	sll	$30,$3,30
2334	addu	$1,$25
2335	 srl	$6,$20,31
2336	xor	$25,$7,$24
2337	 addu	$20,$20
2338	and	$25,$3
2339	srl	$3,$3,2
2340	 or	$20,$6
2341	addu	$1,$19
2342	or	$3,$30
2343	addu	$1,$25
2344#endif
2345	lui	$31,0xca62
2346	ori	$31,0xc1d6	# K_60_79
2347#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
2348	 xor	$21,$23
2349	addu	$24,$31		# 60
2350	rotr	$6,$1,27
2351	 xor	$21,$13
2352	xor	$25,$3,$7
2353	addu	$24,$6
2354	 xor	$21,$18
2355	xor	$25,$2
2356	addu	$24,$20
2357	 rotr	$21,$21,31
2358	rotr	$2,$2,2
2359	addu	$24,$25
2360#else
2361	 xor	$21,$23
2362	sll	$25,$1,5	# 60
2363	addu	$24,$31
2364	srl	$6,$1,27
2365	addu	$24,$25
2366	 xor	$21,$13
2367	xor	$25,$3,$7
2368	addu	$24,$6
2369	 xor	$21,$18
2370	sll	$30,$2,30
2371	xor	$25,$2
2372	 srl	$6,$21,31
2373	 addu	$21,$21
2374	srl	$2,$2,2
2375	addu	$24,$20
2376	 or	$21,$6
2377	or	$2,$30
2378	addu	$24,$25
2379#endif
2380#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
2381	 xor	$22,$8
2382	addu	$7,$31		# 61
2383	rotr	$6,$24,27
2384	 xor	$22,$14
2385	xor	$25,$2,$3
2386	addu	$7,$6
2387	 xor	$22,$19
2388	xor	$25,$1
2389	addu	$7,$21
2390	 rotr	$22,$22,31
2391	rotr	$1,$1,2
2392	addu	$7,$25
2393#else
2394	 xor	$22,$8
2395	sll	$25,$24,5	# 61
2396	addu	$7,$31
2397	srl	$6,$24,27
2398	addu	$7,$25
2399	 xor	$22,$14
2400	xor	$25,$2,$3
2401	addu	$7,$6
2402	 xor	$22,$19
2403	sll	$30,$1,30
2404	xor	$25,$1
2405	 srl	$6,$22,31
2406	 addu	$22,$22
2407	srl	$1,$1,2
2408	addu	$7,$21
2409	 or	$22,$6
2410	or	$1,$30
2411	addu	$7,$25
2412#endif
2413#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
2414	 xor	$23,$9
2415	addu	$3,$31		# 62
2416	rotr	$6,$7,27
2417	 xor	$23,$15
2418	xor	$25,$1,$2
2419	addu	$3,$6
2420	 xor	$23,$20
2421	xor	$25,$24
2422	addu	$3,$22
2423	 rotr	$23,$23,31
2424	rotr	$24,$24,2
2425	addu	$3,$25
2426#else
2427	 xor	$23,$9
2428	sll	$25,$7,5	# 62
2429	addu	$3,$31
2430	srl	$6,$7,27
2431	addu	$3,$25
2432	 xor	$23,$15
2433	xor	$25,$1,$2
2434	addu	$3,$6
2435	 xor	$23,$20
2436	sll	$30,$24,30
2437	xor	$25,$24
2438	 srl	$6,$23,31
2439	 addu	$23,$23
2440	srl	$24,$24,2
2441	addu	$3,$22
2442	 or	$23,$6
2443	or	$24,$30
2444	addu	$3,$25
2445#endif
2446#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
2447	 xor	$8,$10
2448	addu	$2,$31		# 63
2449	rotr	$6,$3,27
2450	 xor	$8,$16
2451	xor	$25,$24,$1
2452	addu	$2,$6
2453	 xor	$8,$21
2454	xor	$25,$7
2455	addu	$2,$23
2456	 rotr	$8,$8,31
2457	rotr	$7,$7,2
2458	addu	$2,$25
2459#else
2460	 xor	$8,$10
2461	sll	$25,$3,5	# 63
2462	addu	$2,$31
2463	srl	$6,$3,27
2464	addu	$2,$25
2465	 xor	$8,$16
2466	xor	$25,$24,$1
2467	addu	$2,$6
2468	 xor	$8,$21
2469	sll	$30,$7,30
2470	xor	$25,$7
2471	 srl	$6,$8,31
2472	 addu	$8,$8
2473	srl	$7,$7,2
2474	addu	$2,$23
2475	 or	$8,$6
2476	or	$7,$30
2477	addu	$2,$25
2478#endif
2479#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
2480	 xor	$9,$11
2481	addu	$1,$31		# 64
2482	rotr	$6,$2,27
2483	 xor	$9,$17
2484	xor	$25,$7,$24
2485	addu	$1,$6
2486	 xor	$9,$22
2487	xor	$25,$3
2488	addu	$1,$8
2489	 rotr	$9,$9,31
2490	rotr	$3,$3,2
2491	addu	$1,$25
2492#else
2493	 xor	$9,$11
2494	sll	$25,$2,5	# 64
2495	addu	$1,$31
2496	srl	$6,$2,27
2497	addu	$1,$25
2498	 xor	$9,$17
2499	xor	$25,$7,$24
2500	addu	$1,$6
2501	 xor	$9,$22
2502	sll	$30,$3,30
2503	xor	$25,$3
2504	 srl	$6,$9,31
2505	 addu	$9,$9
2506	srl	$3,$3,2
2507	addu	$1,$8
2508	 or	$9,$6
2509	or	$3,$30
2510	addu	$1,$25
2511#endif
2512#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
2513	 xor	$10,$12
2514	addu	$24,$31		# 65
2515	rotr	$6,$1,27
2516	 xor	$10,$18
2517	xor	$25,$3,$7
2518	addu	$24,$6
2519	 xor	$10,$23
2520	xor	$25,$2
2521	addu	$24,$9
2522	 rotr	$10,$10,31
2523	rotr	$2,$2,2
2524	addu	$24,$25
2525#else
2526	 xor	$10,$12
2527	sll	$25,$1,5	# 65
2528	addu	$24,$31
2529	srl	$6,$1,27
2530	addu	$24,$25
2531	 xor	$10,$18
2532	xor	$25,$3,$7
2533	addu	$24,$6
2534	 xor	$10,$23
2535	sll	$30,$2,30
2536	xor	$25,$2
2537	 srl	$6,$10,31
2538	 addu	$10,$10
2539	srl	$2,$2,2
2540	addu	$24,$9
2541	 or	$10,$6
2542	or	$2,$30
2543	addu	$24,$25
2544#endif
2545#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
2546	 xor	$11,$13
2547	addu	$7,$31		# 66
2548	rotr	$6,$24,27
2549	 xor	$11,$19
2550	xor	$25,$2,$3
2551	addu	$7,$6
2552	 xor	$11,$8
2553	xor	$25,$1
2554	addu	$7,$10
2555	 rotr	$11,$11,31
2556	rotr	$1,$1,2
2557	addu	$7,$25
2558#else
2559	 xor	$11,$13
2560	sll	$25,$24,5	# 66
2561	addu	$7,$31
2562	srl	$6,$24,27
2563	addu	$7,$25
2564	 xor	$11,$19
2565	xor	$25,$2,$3
2566	addu	$7,$6
2567	 xor	$11,$8
2568	sll	$30,$1,30
2569	xor	$25,$1
2570	 srl	$6,$11,31
2571	 addu	$11,$11
2572	srl	$1,$1,2
2573	addu	$7,$10
2574	 or	$11,$6
2575	or	$1,$30
2576	addu	$7,$25
2577#endif
2578#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
2579	 xor	$12,$14
2580	addu	$3,$31		# 67
2581	rotr	$6,$7,27
2582	 xor	$12,$20
2583	xor	$25,$1,$2
2584	addu	$3,$6
2585	 xor	$12,$9
2586	xor	$25,$24
2587	addu	$3,$11
2588	 rotr	$12,$12,31
2589	rotr	$24,$24,2
2590	addu	$3,$25
2591#else
2592	 xor	$12,$14
2593	sll	$25,$7,5	# 67
2594	addu	$3,$31
2595	srl	$6,$7,27
2596	addu	$3,$25
2597	 xor	$12,$20
2598	xor	$25,$1,$2
2599	addu	$3,$6
2600	 xor	$12,$9
2601	sll	$30,$24,30
2602	xor	$25,$24
2603	 srl	$6,$12,31
2604	 addu	$12,$12
2605	srl	$24,$24,2
2606	addu	$3,$11
2607	 or	$12,$6
2608	or	$24,$30
2609	addu	$3,$25
2610#endif
2611#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
2612	 xor	$13,$15
2613	addu	$2,$31		# 68
2614	rotr	$6,$3,27
2615	 xor	$13,$21
2616	xor	$25,$24,$1
2617	addu	$2,$6
2618	 xor	$13,$10
2619	xor	$25,$7
2620	addu	$2,$12
2621	 rotr	$13,$13,31
2622	rotr	$7,$7,2
2623	addu	$2,$25
2624#else
2625	 xor	$13,$15
2626	sll	$25,$3,5	# 68
2627	addu	$2,$31
2628	srl	$6,$3,27
2629	addu	$2,$25
2630	 xor	$13,$21
2631	xor	$25,$24,$1
2632	addu	$2,$6
2633	 xor	$13,$10
2634	sll	$30,$7,30
2635	xor	$25,$7
2636	 srl	$6,$13,31
2637	 addu	$13,$13
2638	srl	$7,$7,2
2639	addu	$2,$12
2640	 or	$13,$6
2641	or	$7,$30
2642	addu	$2,$25
2643#endif
2644#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
2645	 xor	$14,$16
2646	addu	$1,$31		# 69
2647	rotr	$6,$2,27
2648	 xor	$14,$22
2649	xor	$25,$7,$24
2650	addu	$1,$6
2651	 xor	$14,$11
2652	xor	$25,$3
2653	addu	$1,$13
2654	 rotr	$14,$14,31
2655	rotr	$3,$3,2
2656	addu	$1,$25
2657#else
2658	 xor	$14,$16
2659	sll	$25,$2,5	# 69
2660	addu	$1,$31
2661	srl	$6,$2,27
2662	addu	$1,$25
2663	 xor	$14,$22
2664	xor	$25,$7,$24
2665	addu	$1,$6
2666	 xor	$14,$11
2667	sll	$30,$3,30
2668	xor	$25,$3
2669	 srl	$6,$14,31
2670	 addu	$14,$14
2671	srl	$3,$3,2
2672	addu	$1,$13
2673	 or	$14,$6
2674	or	$3,$30
2675	addu	$1,$25
2676#endif
2677#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
2678	 xor	$15,$17
2679	addu	$24,$31		# 70
2680	rotr	$6,$1,27
2681	 xor	$15,$23
2682	xor	$25,$3,$7
2683	addu	$24,$6
2684	 xor	$15,$12
2685	xor	$25,$2
2686	addu	$24,$14
2687	 rotr	$15,$15,31
2688	rotr	$2,$2,2
2689	addu	$24,$25
2690#else
2691	 xor	$15,$17
2692	sll	$25,$1,5	# 70
2693	addu	$24,$31
2694	srl	$6,$1,27
2695	addu	$24,$25
2696	 xor	$15,$23
2697	xor	$25,$3,$7
2698	addu	$24,$6
2699	 xor	$15,$12
2700	sll	$30,$2,30
2701	xor	$25,$2
2702	 srl	$6,$15,31
2703	 addu	$15,$15
2704	srl	$2,$2,2
2705	addu	$24,$14
2706	 or	$15,$6
2707	or	$2,$30
2708	addu	$24,$25
2709#endif
2710#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
2711	 xor	$16,$18
2712	addu	$7,$31		# 71
2713	rotr	$6,$24,27
2714	 xor	$16,$8
2715	xor	$25,$2,$3
2716	addu	$7,$6
2717	 xor	$16,$13
2718	xor	$25,$1
2719	addu	$7,$15
2720	 rotr	$16,$16,31
2721	rotr	$1,$1,2
2722	addu	$7,$25
2723#else
2724	 xor	$16,$18
2725	sll	$25,$24,5	# 71
2726	addu	$7,$31
2727	srl	$6,$24,27
2728	addu	$7,$25
2729	 xor	$16,$8
2730	xor	$25,$2,$3
2731	addu	$7,$6
2732	 xor	$16,$13
2733	sll	$30,$1,30
2734	xor	$25,$1
2735	 srl	$6,$16,31
2736	 addu	$16,$16
2737	srl	$1,$1,2
2738	addu	$7,$15
2739	 or	$16,$6
2740	or	$1,$30
2741	addu	$7,$25
2742#endif
2743#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
2744	 xor	$17,$19
2745	addu	$3,$31		# 72
2746	rotr	$6,$7,27
2747	 xor	$17,$9
2748	xor	$25,$1,$2
2749	addu	$3,$6
2750	 xor	$17,$14
2751	xor	$25,$24
2752	addu	$3,$16
2753	 rotr	$17,$17,31
2754	rotr	$24,$24,2
2755	addu	$3,$25
2756#else
2757	 xor	$17,$19
2758	sll	$25,$7,5	# 72
2759	addu	$3,$31
2760	srl	$6,$7,27
2761	addu	$3,$25
2762	 xor	$17,$9
2763	xor	$25,$1,$2
2764	addu	$3,$6
2765	 xor	$17,$14
2766	sll	$30,$24,30
2767	xor	$25,$24
2768	 srl	$6,$17,31
2769	 addu	$17,$17
2770	srl	$24,$24,2
2771	addu	$3,$16
2772	 or	$17,$6
2773	or	$24,$30
2774	addu	$3,$25
2775#endif
2776#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
2777	 xor	$18,$20
2778	addu	$2,$31		# 73
2779	rotr	$6,$3,27
2780	 xor	$18,$10
2781	xor	$25,$24,$1
2782	addu	$2,$6
2783	 xor	$18,$15
2784	xor	$25,$7
2785	addu	$2,$17
2786	 rotr	$18,$18,31
2787	rotr	$7,$7,2
2788	addu	$2,$25
2789#else
2790	 xor	$18,$20
2791	sll	$25,$3,5	# 73
2792	addu	$2,$31
2793	srl	$6,$3,27
2794	addu	$2,$25
2795	 xor	$18,$10
2796	xor	$25,$24,$1
2797	addu	$2,$6
2798	 xor	$18,$15
2799	sll	$30,$7,30
2800	xor	$25,$7
2801	 srl	$6,$18,31
2802	 addu	$18,$18
2803	srl	$7,$7,2
2804	addu	$2,$17
2805	 or	$18,$6
2806	or	$7,$30
2807	addu	$2,$25
2808#endif
2809#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
2810	 xor	$19,$21
2811	addu	$1,$31		# 74
2812	rotr	$6,$2,27
2813	 xor	$19,$11
2814	xor	$25,$7,$24
2815	addu	$1,$6
2816	 xor	$19,$16
2817	xor	$25,$3
2818	addu	$1,$18
2819	 rotr	$19,$19,31
2820	rotr	$3,$3,2
2821	addu	$1,$25
2822#else
2823	 xor	$19,$21
2824	sll	$25,$2,5	# 74
2825	addu	$1,$31
2826	srl	$6,$2,27
2827	addu	$1,$25
2828	 xor	$19,$11
2829	xor	$25,$7,$24
2830	addu	$1,$6
2831	 xor	$19,$16
2832	sll	$30,$3,30
2833	xor	$25,$3
2834	 srl	$6,$19,31
2835	 addu	$19,$19
2836	srl	$3,$3,2
2837	addu	$1,$18
2838	 or	$19,$6
2839	or	$3,$30
2840	addu	$1,$25
2841#endif
2842#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
2843	 xor	$20,$22
2844	addu	$24,$31		# 75
2845	rotr	$6,$1,27
2846	 xor	$20,$12
2847	xor	$25,$3,$7
2848	addu	$24,$6
2849	 xor	$20,$17
2850	xor	$25,$2
2851	addu	$24,$19
2852	 rotr	$20,$20,31
2853	rotr	$2,$2,2
2854	addu	$24,$25
2855#else
2856	 xor	$20,$22
2857	sll	$25,$1,5	# 75
2858	addu	$24,$31
2859	srl	$6,$1,27
2860	addu	$24,$25
2861	 xor	$20,$12
2862	xor	$25,$3,$7
2863	addu	$24,$6
2864	 xor	$20,$17
2865	sll	$30,$2,30
2866	xor	$25,$2
2867	 srl	$6,$20,31
2868	 addu	$20,$20
2869	srl	$2,$2,2
2870	addu	$24,$19
2871	 or	$20,$6
2872	or	$2,$30
2873	addu	$24,$25
2874#endif
2875#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
2876	 xor	$21,$23
2877	addu	$7,$31		# 76
2878	rotr	$6,$24,27
2879	 xor	$21,$13
2880	xor	$25,$2,$3
2881	addu	$7,$6
2882	 xor	$21,$18
2883	xor	$25,$1
2884	addu	$7,$20
2885	 rotr	$21,$21,31
2886	rotr	$1,$1,2
2887	addu	$7,$25
2888#else
2889	 xor	$21,$23
2890	sll	$25,$24,5	# 76
2891	addu	$7,$31
2892	srl	$6,$24,27
2893	addu	$7,$25
2894	 xor	$21,$13
2895	xor	$25,$2,$3
2896	addu	$7,$6
2897	 xor	$21,$18
2898	sll	$30,$1,30
2899	xor	$25,$1
2900	 srl	$6,$21,31
2901	 addu	$21,$21
2902	srl	$1,$1,2
2903	addu	$7,$20
2904	 or	$21,$6
2905	or	$1,$30
2906	addu	$7,$25
2907#endif
2908#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
2909	 xor	$22,$8
2910	addu	$3,$31		# 77
2911	rotr	$6,$7,27
2912	 xor	$22,$14
2913	xor	$25,$1,$2
2914	addu	$3,$6
2915	 xor	$22,$19
2916	xor	$25,$24
2917	addu	$3,$21
2918	 rotr	$22,$22,31
2919	rotr	$24,$24,2
2920	addu	$3,$25
2921#else
2922	 xor	$22,$8
2923	sll	$25,$7,5	# 77
2924	addu	$3,$31
2925	srl	$6,$7,27
2926	addu	$3,$25
2927	 xor	$22,$14
2928	xor	$25,$1,$2
2929	addu	$3,$6
2930	 xor	$22,$19
2931	sll	$30,$24,30
2932	xor	$25,$24
2933	 srl	$6,$22,31
2934	 addu	$22,$22
2935	srl	$24,$24,2
2936	addu	$3,$21
2937	 or	$22,$6
2938	or	$24,$30
2939	addu	$3,$25
2940#endif
2941#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
2942	 xor	$23,$9
2943	addu	$2,$31		# 78
2944	rotr	$6,$3,27
2945	 xor	$23,$15
2946	xor	$25,$24,$1
2947	addu	$2,$6
2948	 xor	$23,$20
2949	xor	$25,$7
2950	addu	$2,$22
2951	 rotr	$23,$23,31
2952	rotr	$7,$7,2
2953	addu	$2,$25
2954#else
2955	 xor	$23,$9
2956	sll	$25,$3,5	# 78
2957	addu	$2,$31
2958	srl	$6,$3,27
2959	addu	$2,$25
2960	 xor	$23,$15
2961	xor	$25,$24,$1
2962	addu	$2,$6
2963	 xor	$23,$20
2964	sll	$30,$7,30
2965	xor	$25,$7
2966	 srl	$6,$23,31
2967	 addu	$23,$23
2968	srl	$7,$7,2
2969	addu	$2,$22
2970	 or	$23,$6
2971	or	$7,$30
2972	addu	$2,$25
2973#endif
2974#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
2975	 lw	$8,0($4)
2976	addu	$1,$31		# 79
2977	 lw	$9,4($4)
2978	rotr	$6,$2,27
2979	 lw	$10,8($4)
2980	xor	$25,$7,$24
2981	addu	$1,$6
2982	 lw	$11,12($4)
2983	xor	$25,$3
2984	addu	$1,$23
2985	 lw	$12,16($4)
2986	rotr	$3,$3,2
2987	addu	$1,$25
2988#else
2989	 lw	$8,0($4)
2990	sll	$25,$2,5	# 79
2991	addu	$1,$31
2992	 lw	$9,4($4)
2993	srl	$6,$2,27
2994	addu	$1,$25
2995	 lw	$10,8($4)
2996	xor	$25,$7,$24
2997	addu	$1,$6
2998	 lw	$11,12($4)
2999	sll	$30,$3,30
3000	xor	$25,$3
3001	 lw	$12,16($4)
3002	srl	$3,$3,2
3003	addu	$1,$23
3004	or	$3,$30
3005	addu	$1,$25
3006#endif
3007	daddu $5,64
3008	ld	$6,0($29)
3009
3010	addu	$1,$8
3011	addu	$2,$9
3012	sw	$1,0($4)
3013	addu	$3,$10
3014	addu	$7,$11
3015	sw	$2,4($4)
3016	addu	$24,$12
3017	sw	$3,8($4)
3018	sw	$7,12($4)
3019	sw	$24,16($4)
3020	.set	noreorder
3021	bne	$5,$6,.Loop
3022	nop
3023
3024	.set	noreorder
3025	ld	$31,(16-1)*8($29)
3026	ld	$30,(16-2)*8($29)
3027	ld	$23,(16-3)*8($29)
3028	ld	$22,(16-4)*8($29)
3029	ld	$21,(16-5)*8($29)
3030	ld	$20,(16-6)*8($29)
3031	ld	$19,(16-7)*8($29)
3032	ld	$18,(16-8)*8($29)
3033	ld	$17,(16-9)*8($29)
3034	ld	$16,(16-10)*8($29)
3035	jr	$31
3036	daddu $29,16*8
3037.end	sha1_block_data_order
3038.rdata
3039.asciiz	"SHA1 for MIPS, CRYPTOGAMS by <appro@openssl.org>"
3040