1#include "drmP.h"
2#include "drm.h"
3#include "nouveau_drv.h"
4#include "nouveau_drm.h"
5
6int
7nv04_timer_init(struct drm_device *dev)
8{
9	struct drm_nouveau_private *dev_priv = dev->dev_private;
10
11	NV_WRITE(NV04_PTIMER_INTR_EN_0, 0x00000000);
12	NV_WRITE(NV04_PTIMER_INTR_0, 0xFFFFFFFF);
13
14	/* Just use the pre-existing values when possible for now; these regs
15	 * are not written in nv (driver writer missed a /4 on the address), and
16	 * writing 8 and 3 to the correct regs breaks the timings on the LVDS
17	 * hardware sequencing microcode.
18	 * A correct solution (involving calculations with the GPU PLL) can
19	 * be done when kernel modesetting lands
20	 */
21	if (!NV_READ(NV04_PTIMER_NUMERATOR) || !NV_READ(NV04_PTIMER_DENOMINATOR)) {
22		NV_WRITE(NV04_PTIMER_NUMERATOR, 0x00000008);
23		NV_WRITE(NV04_PTIMER_DENOMINATOR, 0x00000003);
24	}
25
26	return 0;
27}
28
29uint64_t
30nv04_timer_read(struct drm_device *dev)
31{
32	struct drm_nouveau_private *dev_priv = dev->dev_private;
33	uint32_t low;
34	/* From kmmio dumps on nv28 this looks like how the blob does this.
35	 * It reads the high dword twice, before and after.
36	 * The only explanation seems to be that the 64-bit timer counter
37	 * advances between high and low dword reads and may corrupt the
38	 * result. Not confirmed.
39	 */
40	uint32_t high2 = NV_READ(NV04_PTIMER_TIME_1);
41	uint32_t high1;
42	do {
43		high1 = high2;
44		low = NV_READ(NV04_PTIMER_TIME_0);
45		high2 = NV_READ(NV04_PTIMER_TIME_1);
46	} while(high1 != high2);
47	return (((uint64_t)high2) << 32) | (uint64_t)low;
48}
49
50void
51nv04_timer_takedown(struct drm_device *dev)
52{
53}
54