1/* $NetBSD: spiflash.h,v 1.3 2006/12/25 18:39:48 wiz Exp $ */ 2 3/*- 4 * Copyright (c) 2006 Urbana-Champaign Independent Media Center. 5 * Copyright (c) 2006 Garrett D'Amore. 6 * All rights reserved. 7 * 8 * Portions of this code were written by Garrett D'Amore for the 9 * Champaign-Urbana Community Wireless Network Project. 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer in the documentation and/or other materials provided 19 * with the distribution. 20 * 3. All advertising materials mentioning features or use of this 21 * software must display the following acknowledgements: 22 * This product includes software developed by the Urbana-Champaign 23 * Independent Media Center. 24 * This product includes software developed by Garrett D'Amore. 25 * 4. Urbana-Champaign Independent Media Center's name and Garrett 26 * D'Amore's name may not be used to endorse or promote products 27 * derived from this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE URBANA-CHAMPAIGN INDEPENDENT 30 * MEDIA CENTER AND GARRETT D'AMORE ``AS IS'' AND ANY EXPRESS OR 31 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 32 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 33 * ARE DISCLAIMED. IN NO EVENT SHALL THE URBANA-CHAMPAIGN INDEPENDENT 34 * MEDIA CENTER OR GARRETT D'AMORE BE LIABLE FOR ANY DIRECT, INDIRECT, 35 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 36 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 37 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 38 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 39 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 40 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 41 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 42 */ 43 44#ifndef _DEV_SPI_SPIFLASH_H_ 45#define _DEV_SPI_SPIFLASH_H_ 46 47#define SPIFLASH_CMD_RDSR 0x05 /* read status register */ 48#define SPIFLASH_CMD_WRSR 0x01 /* write status register */ 49#define SPIFLASH_CMD_WREN 0x06 /* enable WRSR */ 50#define SPIFLASH_CMD_WRDI 0x04 /* disable WRSR */ 51 52/* 53 * Different chips offer different ways to read a device ID, although 54 * newer parts should all offer the standard JEDEC variant. 55 * Additionally, many parts have a faster read, though how to make use 56 * of this sometimes requires special hacks. E.g. some parts use an 57 * extra data pin, and some crank the clock rate up. 58 */ 59#define SPIFLASH_CMD_READ 0x03 /* read data (normal) */ 60#define SPIFLASH_CMD_RDID 0xab /* read id */ 61#define SPIFLASH_CMD_RDID2 0x90 /* read id (alternate) */ 62#define SPIFLASH_CMD_RDJI 0x9f /* read JEDEC id */ 63#define SPIFLASH_CMD_READFAST 0x0b /* fast read */ 64 65/* 66 * Different chips offer different variations on the sector erase. 67 * E.g. SST parts offer 4k, 32k, and 64k erase sizes on the same part, 68 * with just different cmds. However, at least SST, AMD, and Winbond 69 * all offer at least the main (0xd8) variant. 70 */ 71#define SPIFLASH_CMD_ERASE 0xd8 /* sector erase */ 72#define SPIFLASH_CMD_ERASE2 0x52 /* sector erase (alternate) */ 73#define SPIFLASH_CMD_ERASE3 0x20 /* sector erase (alternate) */ 74#define SPIFLASH_CMD_ERASE4 0x81 /* page erase */ 75#define SPIFLASH_CMD_CHIPERASE 0xc7 /* chip erase */ 76 77/* 78 * Some parts can stream bytes with the program command, whereas others require 79 * a separate command sequence for each byte. 80 */ 81#define SPIFLASH_CMD_PROGRAM 0x02 /* page or byte program */ 82#define SPIFLASH_CMD_PROGRAM_AA 0xad /* program (autoincrement) */ 83 84/* 85 * Some additional commands. Again, mostly device specific. 86 */ 87#define SPIFLASH_CMD_EBSY 0x70 /* output busy signal (SST) */ 88#define SPIFLASH_CMD_DBSY 0x80 /* disable busy signal (SST) */ 89 90/* 91 * Status register bits. Not all devices implement all bits. In 92 * addition, the meanings of the BP bits seem to vary from device to 93 * device. 94 */ 95#define SPIFLASH_SR_BUSY 0x01 /* program in progress */ 96#define SPIFLASH_SR_WEL 0x02 /* write enable latch */ 97#define SPIFLASH_SR_BP0 0x04 /* block protect bits */ 98#define SPIFLASH_SR_BP1 0x08 99#define SPIFLASH_SR_BP2 0x10 100#define SPIFLASH_SR_BP3 0x20 101#define SPIFLASH_SR_AAI 0x40 /* auto-increment mode */ 102#define SPIFLASH_SR_SRP 0x80 /* SR write protected */ 103 104/* 105 * This needs to change to accommodate boot-sectored devices. 106 */ 107 108typedef struct spiflash_softc *spiflash_handle_t; 109 110struct spiflash_hw_if { 111 /* 112 * Driver MUST provide these. 113 */ 114 const char *(*sf_getname)(void *); 115 struct spi_handle *(*sf_gethandle)(void *); 116 int (*sf_getflags)(void *); 117 int (*sf_getsize)(void *, int); 118 119 /* 120 * SPI framework will provide these if the driver does not. 121 */ 122 int (*sf_erase)(spiflash_handle_t, size_t, size_t); 123 int (*sf_write)(spiflash_handle_t, size_t, size_t, 124 const uint8_t *); 125 int (*sf_read)(spiflash_handle_t, size_t, size_t, uint8_t *); 126 /* 127 * Not implemented yet. 128 */ 129 int (*sf_getstatus)(spiflash_handle_t, int, int); 130 int (*sf_setstatus)(spiflash_handle_t, int, int, int); 131}; 132 133#define SPIFLASH_SIZE_DEVICE 0 134#define SPIFLASH_SIZE_ERASE 1 135#define SPIFLASH_SIZE_WRITE 2 /* return -1 for unlimited */ 136#define SPIFLASH_SIZE_READ 3 /* return -1 for unlimited */ 137#define SPIFLASH_SIZE_COUNT 4 138 139#define SPIFLASH_FLAG_FAST_READ 0x0004 /* use fast read sequence */ 140 141spiflash_handle_t spiflash_attach_mi(const struct spiflash_hw_if *, void *, 142 device_t); 143void spiflash_set_private(spiflash_handle_t, void *); 144void *spiflash_get_private(spiflash_handle_t); 145int spiflash_read_status(spiflash_handle_t, uint8_t *); 146int spiflash_write_disable(spiflash_handle_t); 147int spiflash_write_enable(spiflash_handle_t); 148int spiflash_cmd(spiflash_handle_t, uint8_t, size_t, uint32_t, size_t, 149 const uint8_t *, uint8_t *); 150int spiflash_wait(spiflash_handle_t, int); 151 152 153#endif /* _DEV_SPI_SPIFLASH_H_ */ 154