1/* $NetBSD$ */ 2/* 3 * Device Driver for Tekram DC395U/UW/F, DC315/U 4 * PCI SCSI Bus Master Host Adapter 5 * (SCSI chip set used Tekram ASIC TRM-S1040) 6 * 7 * Copyright (c) 2001 Rui-Xiang Guo 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32/* 33 * Ported from 34 * dc395x_trm.h 35 * 36 * Written for NetBSD 1.4.x by 37 * Erich Chen (erich@tekram.com.tw) 38 * 39 * Provided by 40 * (C)Copyright 1995-1999 Tekram Technology Co., Ltd. All rights reserved. 41 */ 42 43/* 44 ********************************************************************** 45 * 46 * The SCSI register offset for TRM_S1040 47 * 48 ********************************************************************** 49 */ 50#define TRM_SCSI_STATUS 0x80 /* SCSI Status (R) */ 51#define COMMANDPHASEDONE 0x2000 /* SCSI command phase done */ 52#define SCSIXFERDONE 0x0800 /* SCSI transfer done */ 53#define SCSIXFERCNT_2_ZERO 0x0100 /* SCSI transfer count to zero */ 54#define SCSIINTERRUPT 0x0080 /* SCSI interrupt pending */ 55#define COMMANDABORT 0x0040 /* SCSI command abort */ 56#define SEQUENCERACTIVE 0x0020 /* SCSI sequencer active */ 57#define PHASEMISMATCH 0x0010 /* SCSI phase mismatch */ 58#define PARITYERROR 0x0008 /* SCSI parity error */ 59#define PHASEMASK 0x0007 /* Phase MSG/CD/IO */ 60#define PH_DATA_OUT 0x00 /* Data out phase */ 61#define PH_DATA_IN 0x01 /* Data in phase */ 62#define PH_COMMAND 0x02 /* Command phase */ 63#define PH_STATUS 0x03 /* Status phase */ 64#define PH_BUS_FREE 0x05 /* Invalid phase as bus free */ 65#define PH_MSG_OUT 0x06 /* Message out phase */ 66#define PH_MSG_IN 0x07 /* Message in phase */ 67#define TRM_SCSI_CONTROL 0x80 /* SCSI Control (W) */ 68#define DO_CLRATN 0x0400 /* Clear ATN */ 69#define DO_SETATN 0x0200 /* Set ATN */ 70#define DO_CMDABORT 0x0100 /* Abort SCSI command */ 71#define DO_RSTMODULE 0x0010 /* Reset SCSI chip */ 72#define DO_RSTSCSI 0x0008 /* Reset SCSI bus */ 73#define DO_CLRFIFO 0x0004 /* Clear SCSI transfer FIFO */ 74#define DO_DATALATCH 0x0002 /* Enable SCSI bus data latch */ 75#define DO_HWRESELECT 0x0001 /* Enable hardware reselection */ 76#define TRM_SCSI_FIFOCNT 0x82 /* SCSI FIFO Counter (R) */ 77#define SCSI_FIFOCNT_MASK 0x1F /* 5 bits SCSI FIFO counter */ 78#define SCSI_FIFO_EMPTY 0x40 /* SCSI FIFO Empty */ 79#define TRM_SCSI_SIGNAL 0x83 /* SCSI low level signal (R/W) */ 80#define TRM_SCSI_INTSTATUS 0x84 /* SCSI Interrupt Status (R) */ 81#define INT_SCAM 0x80 /* SCAM selection interrupt */ 82#define INT_SELECT 0x40 /* Selection interrupt */ 83#define INT_SELTIMEOUT 0x20 /* Selection timeout interrupt */ 84#define INT_DISCONNECT 0x10 /* Bus disconnected interrupt */ 85#define INT_RESELECTED 0x08 /* Reselected interrupt */ 86#define INT_SCSIRESET 0x04 /* SCSI reset detected interrupt */ 87#define INT_BUSSERVICE 0x02 /* Bus service interrupt */ 88#define INT_CMDDONE 0x01 /* SCSI command done interrupt */ 89#define TRM_SCSI_OFFSET 0x84 /* SCSI Offset Count (W) */ 90/* 91 * Bit Name Definition 92 * 07-05 0 RSVD Reversed. Always 0. 93 * 04 0 OFFSET4 Reversed for LVDS. Always 0. 94 * 03-00 0 OFFSET[03:00] Offset number from 0 to 15 95 */ 96#define TRM_SCSI_SYNC 0x85 /* SCSI Sync Control (R/W) */ 97#define LVDS_SYNC 0x20 /* Enable LVDS sync */ 98#define WIDE_SYNC 0x10 /* Enable WIDE sync */ 99#define ALT_SYNC 0x08 /* Enable Fast-20 alternate sync */ 100/* 101 * SYNCM 7 6 5 4 3 2 1 0 102 * Name RSVD RSVD LVDS WIDE ALTPERD PERIOD2 PERIOD1 PERIOD0 103 * Default 0 0 0 0 0 0 0 0 104 * 105 * Bit Name Definition 106 * 07-06 0 RSVD Reversed. Always read 0 107 * 05 0 LVDS Reversed. Always read 0 108 * 04 0 WIDE/WSCSI Enable wide (16-bits) SCSI transfer. 109 * 03 0 ALTPERD/ALTPD Alternate (Sync./Period) mode. 110 * 111 * @@ When this bit is set, 112 * the synchronous period bits 2:0 113 * in the Synchronous Mode register 114 * are used to transfer data 115 * at the Fast-20 rate. 116 * @@ When this bit is reset, 117 * the synchronous period bits 2:0 118 * in the Synchronous Mode Register 119 * are used to transfer data 120 * at the Fast-40 rate. 121 * 122 * 02-00 0 PERIOD[2:0]/SXPD[02:00] Synchronous SCSI Transfer Rate. 123 * These 3 bits specify 124 * the Synchronous SCSI Transfer Rate 125 * for Fast-20 and Fast-10. 126 * These bits are also reset 127 * by a SCSI Bus reset. 128 * 129 * For Fast-10 bit ALTPD = 0 and LVDS = 0 130 * and bit2,bit1,bit0 is defined as follows : 131 * 132 * 000 100ns, 10.0 Mbytes/s 133 * 001 150ns, 6.6 Mbytes/s 134 * 010 200ns, 5.0 Mbytes/s 135 * 011 250ns, 4.0 Mbytes/s 136 * 100 300ns, 3.3 Mbytes/s 137 * 101 350ns, 2.8 Mbytes/s 138 * 110 400ns, 2.5 Mbytes/s 139 * 111 450ns, 2.2 Mbytes/s 140 * 141 * For Fast-20 bit ALTPD = 1 and LVDS = 0 142 * and bit2,bit1,bit0 is defined as follows : 143 * 144 * 000 50ns, 20.0 Mbytes/s 145 * 001 75ns, 13.3 Mbytes/s 146 * 010 100ns, 10.0 Mbytes/s 147 * 011 125ns, 8.0 Mbytes/s 148 * 100 150ns, 6.6 Mbytes/s 149 * 101 175ns, 5.7 Mbytes/s 150 * 110 200ns, 5.0 Mbytes/s 151 * 111 250ns, 4.0 Mbytes/s 152 * 153 * For Fast-40 bit ALTPD = 0 and LVDS = 1 154 * and bit2,bit1,bit0 is defined as follows : 155 * 156 * 000 25ns, 40.0 Mbytes/s 157 * 001 50ns, 20.0 Mbytes/s 158 * 010 75ns, 13.3 Mbytes/s 159 * 011 100ns, 10.0 Mbytes/s 160 * 100 125ns, 8.0 Mbytes/s 161 * 101 150ns, 6.6 Mbytes/s 162 * 110 175ns, 5.7 Mbytes/s 163 * 111 200ns, 5.0 Mbytes/s 164 */ 165#define TRM_SCSI_TARGETID 0x86 /* SCSI Target ID (R/W) */ 166#define TRM_SCSI_IDMSG 0x87 /* SCSI Identify Message (R) */ 167#define TRM_SCSI_HOSTID 0x87 /* SCSI Host ID (W) */ 168#define TRM_SCSI_XCNT 0x88 /* SCSI Transfer Counter (R/W) */ 169#define SCSI_XCNT_MASK 0x00FFFFFF /* 24 bits SCSI transfer counter */ 170#define TRM_SCSI_INTEN 0x8C /* SCSI Interrupt Enable (R/W) */ 171#define EN_SCAM 0x80 /* Enable SCAM selection intr */ 172#define EN_SELECT 0x40 /* Enable selection intr */ 173#define EN_SELTIMEOUT 0x20 /* Enable selection timeout intr */ 174#define EN_DISCONNECT 0x10 /* Enable bus disconnected intr */ 175#define EN_RESELECTED 0x08 /* Enable reselected intr */ 176#define EN_SCSIRESET 0x04 /* Enable SCSI reset detected intr */ 177#define EN_BUSSERVICE 0x02 /* Enable bus service intr */ 178#define EN_CMDDONE 0x01 /* Enable SCSI command done intr */ 179#define TRM_SCSI_CONFIG0 0x8D /* SCSI Configuration 0 (R/W) */ 180#define PHASELATCH 0x40 /* Enable phase latch */ 181#define INITIATOR 0x20 /* Enable initiator mode */ 182#define PARITYCHECK 0x10 /* Enable parity check */ 183#define BLOCKRST 0x01 /* Disable SCSI reset */ 184#define TRM_SCSI_CONFIG1 0x8E /* SCSI Configuration 1 (R/W) */ 185#define ACTIVE_NEGPLUS 0x10 /* Enhance active negation */ 186#define FILTER_DISABLE 0x08 /* Disable SCSI data filter */ 187#define ACTIVE_NEG 0x02 /* Enable active negation */ 188#define TRM_SCSI_COMMAND 0x90 /* SCSI Command (R/W) */ 189#define SCMD_COMP 0x12 /* Command complete */ 190#define SCMD_SEL_ATN 0x60 /* Selection with ATN */ 191#define SCMD_SEL_ATN3 0x64 /* Selection with ATN3 */ 192#define SCMD_SEL_ATNSTOP 0xB8 /* Selection with ATN and Stop */ 193#define SCMD_FIFO_OUT 0xC0 /* SCSI FIFO transfer out */ 194#define SCMD_DMA_OUT 0xC1 /* SCSI DMA transfer out */ 195#define SCMD_FIFO_IN 0xC2 /* SCSI FIFO transfer in */ 196#define SCMD_DMA_IN 0xC3 /* SCSI DMA transfer in */ 197#define SCMD_MSGACCEPT 0xD8 /* Message accept */ 198/* 199 * Code Command Description 200 * 201 * 02 Enable reselection with FIFO 202 * 40 Select without ATN with FIFO 203 * 60 Select with ATN with FIFO 204 * 64 Select with ATN3 with FIFO 205 * A0 Select with ATN and stop with FIFO 206 * C0 Transfer information out with FIFO 207 * C1 Transfer information out with DMA 208 * C2 Transfer information in with FIFO 209 * C3 Transfer information in with DMA 210 * 12 Initiator command complete with FIFO 211 * 50 Initiator transfer information out sequence without ATN with FIFO 212 * 70 Initiator transfer information out sequence with ATN with FIFO 213 * 74 Initiator transfer information out sequence with ATN3 with FIFO 214 * 52 Initiator transfer information in sequence without ATN with FIFO 215 * 72 Initiator transfer information in sequence with ATN with FIFO 216 * 76 Initiator transfer information in sequence with ATN3 with FIFO 217 * 90 Initiator transfer information out command complete with FIFO 218 * 92 Initiator transfer information in command complete with FIFO 219 * D2 Enable selection 220 * 08 Reselection 221 * 48 Disconnect command with FIFO 222 * 88 Terminate command with FIFO 223 * C8 Target command complete with FIFO 224 * 18 SCAM Arbitration/ Selection 225 * 5A Enable reselection 226 * 98 Select without ATN with FIFO 227 * B8 Select with ATN with FIFO 228 * D8 Message Accepted 229 * 58 NOP 230 */ 231#define TRM_SCSI_TIMEOUT 0x91 /* SCSI Time Out Value (R/W) */ 232#define SEL_TIMEOUT 153 /* 250ms selection timeout (@ 40 MHz) */ 233#define TRM_SCSI_FIFO 0x98 /* SCSI FIFO (R/W) */ 234#define TRM_SCSI_TCR0 0x9C /* SCSI Target Control 0 (R/W) */ 235#define TCR0_WIDE_NEGO_DONE 0x8000 /* Wide nego done */ 236#define TCR0_SYNC_NEGO_DONE 0x4000 /* Sync nego done */ 237#define TCR0_ENABLE_LVDS 0x2000 /* Enable LVDS sync */ 238#define TCR0_ENABLE_WIDE 0x1000 /* Enable WIDE sync */ 239#define TCR0_ENABLE_ALT 0x0800 /* Enable alternate sync */ 240#define TCR0_PERIOD_MASK 0x0700 /* Transfer rate */ 241#define TCR0_DO_WIDE_NEGO 0x0080 /* Do wide NEGO */ 242#define TCR0_DO_SYNC_NEGO 0x0040 /* Do sync NEGO */ 243#define TCR0_DISCONNECT_EN 0x0020 /* Disconnection enable */ 244#define TCR0_OFFSET_MASK 0x001F /* Offset number */ 245#define TRM_SCSI_TCR1 0x9E /* SCSI Target Control 1 (R/W) */ 246#define MAXTAG_MASK 0x7F00 /* Maximum tags (127) */ 247#define NON_TAG_BUSY 0x0080 /* Non tag command active */ 248#define ACTTAG_MASK 0x007F /* Active tags */ 249/* 250 ********************************************************************** 251 * 252 * The DMA register offset for TRM_S1040 253 * 254 ********************************************************************** 255 */ 256#define TRM_DMA_COMMAND 0xA0 /* DMA Command (R/W) */ 257#define SGXFER 0x02 /* Scatter/Gather transfer */ 258#define XFERDATAIN 0x01 /* Transfer data in */ 259#define XFERDATAOUT 0x00 /* Transfer data out */ 260#define TRM_DMA_CONTROL 0xA1 /* DMA Control (W) */ 261#define STOPDMAXFER 0x08 /* Stop DMA transfer */ 262#define ABORTXFER 0x04 /* Abort DMA transfer */ 263#define CLRXFIFO 0x02 /* Clear DMA transfer FIFO */ 264#define STARTDMAXFER 0x01 /* Start DMA transfer */ 265#define TRM_DMA_FIFOCNT 0xA1 /* DMA FIFO Counter (R) */ 266#define DMA_FIFOCNT_MASK 0xFF /* Data FIFO Count */ 267#define TRM_DMA_FIFOSTATUS 0xA2 /* DMA FIFO Status (R) */ 268#define DMA_FIFO_EMPTY 0x80 /* DMA FIFO Empty */ 269#define DMA_FIFO_FULL 0x01 /* DMA FIFO Full */ 270#define TRM_DMA_STATUS 0xA3 /* DMA Interrupt Status (R/W) */ 271#define XFERPENDING 0x80 /* Transfer pending */ 272#define DMAXFERCOMP 0x02 /* Bus Master XFER Complete status */ 273#define SCSICOMP 0x01 /* SCSI complete interrupt */ 274#define TRM_DMA_INTEN 0xA4 /* DMA Interrupt Enable (R/W) */ 275#define EN_SCSIINTR 0x01 /* Enable SCSI complete interrupt */ 276#define TRM_DMA_CONFIG 0xA6 /* DMA Configuration (R/W) */ 277#define DMA_ENHANCE 0x8000 /* Enable DMA enhance feature */ 278#define TRM_DMA_XCNT 0xA8 /* DMA Transfer Counter (R/W) */ 279#define TRM_DMA_CXCNT 0xAC /* DMA Current Transfer Counter (R) */ 280#define TRM_DMA_XLOWADDR 0xB0 /* DMA Xfer Physical Low Addr (R/W) */ 281#define TRM_DMA_XHIGHADDR 0xB4 /* DMA Xfer Physical High Addr (R/W) */ 282/* 283 ********************************************************************** 284 * 285 * The general register offset for TRM_S1040 286 * 287 ********************************************************************** 288 */ 289#define TRM_GEN_CONTROL 0xD4 /* Global Control (R/W) */ 290#define EN_LED 0x80 /* Enable Control onboard LED */ 291#define EN_EEPROM 0x10 /* Enable EEPROM programming */ 292#define AUTOTERM 0x04 /* Enable Auto SCSI terminator */ 293#define LOW8TERM 0x02 /* Enable Lower 8 bit SCSI terminator */ 294#define UP8TERM 0x01 /* Enable Upper 8 bit SCSI terminator */ 295#define TRM_GEN_STATUS 0xD5 /* Global Status (R) */ 296#define GTIMEOUT 0x80 /* Global timer reach 0 */ 297#define CON5068 0x10 /* External 50/68 pin connected */ 298#define CON68 0x08 /* Internal 68 pin connected */ 299#define CON50 0x04 /* Internal 50 pin connected */ 300#define WIDESCSI 0x02 /* Wide SCSI card */ 301#define TRM_GEN_NVRAM 0xD6 /* Serial NON-VOLATILE RAM port (R/W) */ 302#define NVR_BITOUT 0x08 /* Serial data out */ 303#define NVR_BITIN 0x04 /* Serial data in */ 304#define NVR_CLOCK 0x02 /* Serial clock */ 305#define NVR_SELECT 0x01 /* Serial select */ 306#define TRM_GEN_EDATA 0xD7 /* Parallel EEPROM data port (R/W) */ 307#define TRM_GEN_EADDRESS 0xD8 /* Parallel EEPROM address (R/W) */ 308#define TRM_GEN_TIMER 0xDB /* Global timer (R/W) */ 309