1/* $NetBSD$ */ 2/*- 3 * Copyright (c) 2002 Izumi Tsutsui. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 26/* 27 * Device Driver for Tekram DC395U/UW/F, DC315/U 28 * PCI SCSI Bus Master Host Adapter 29 * (SCSI chip set used Tekram ASIC TRM-S1040) 30 * 31 * Copyright (c) 2001 Rui-Xiang Guo 32 * All rights reserved. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 3. The name of the author may not be used to endorse or promote products 43 * derived from this software without specific prior written permission. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 46 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 47 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 48 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 49 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 50 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 51 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 52 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 53 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 54 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 55 */ 56/* 57 * Ported from 58 * dc395x_trm.c 59 * 60 * Written for NetBSD 1.4.x by 61 * Erich Chen (erich@tekram.com.tw) 62 * 63 * Provided by 64 * (C)Copyright 1995-1999 Tekram Technology Co., Ltd. All rights reserved. 65 */ 66 67#include <sys/cdefs.h> 68__KERNEL_RCSID(0, "$NetBSD$"); 69 70/* #define TRM_DEBUG */ 71#ifdef TRM_DEBUG 72int trm_debug = 1; 73#define DPRINTF(arg) if (trm_debug > 0) printf arg; 74#else 75#define DPRINTF(arg) 76#endif 77 78#include <sys/param.h> 79#include <sys/systm.h> 80#include <sys/malloc.h> 81#include <sys/buf.h> 82#include <sys/kernel.h> 83#include <sys/device.h> 84#include <sys/queue.h> 85 86#include <sys/bus.h> 87#include <sys/intr.h> 88 89#include <dev/scsipi/scsi_spc.h> 90#include <dev/scsipi/scsi_all.h> 91#include <dev/scsipi/scsi_message.h> 92#include <dev/scsipi/scsipi_all.h> 93#include <dev/scsipi/scsiconf.h> 94 95#include <dev/pci/pcidevs.h> 96#include <dev/pci/pcireg.h> 97#include <dev/pci/pcivar.h> 98#include <dev/pci/trmreg.h> 99 100/* 101 * feature of chip set MAX value 102 */ 103#define TRM_MAX_TARGETS 16 104#define TRM_MAX_LUNS 8 105#define TRM_MAX_SG_ENTRIES (MAXPHYS / PAGE_SIZE + 1) 106#define TRM_MAX_SRB 32 /* XXX */ 107#define TRM_MAX_TAG TRM_MAX_SRB /* XXX */ 108#define TRM_MAX_OFFSET 15 109#define TRM_MAX_PERIOD 125 110 111/* 112 * Segment Entry 113 */ 114struct trm_sg_entry { 115 uint32_t address; 116 uint32_t length; 117}; 118 119#define TRM_SG_SIZE (sizeof(struct trm_sg_entry) * TRM_MAX_SG_ENTRIES) 120 121/* 122 ********************************************************************** 123 * The SEEPROM structure for TRM_S1040 124 ********************************************************************** 125 */ 126struct nvram_target { 127 uint8_t config0; /* Target configuration byte 0 */ 128#define NTC_DO_WIDE_NEGO 0x20 /* Wide negotiate */ 129#define NTC_DO_TAG_QUEUING 0x10 /* Enable SCSI tagged queuing */ 130#define NTC_DO_SEND_START 0x08 /* Send start command SPINUP */ 131#define NTC_DO_DISCONNECT 0x04 /* Enable SCSI disconnect */ 132#define NTC_DO_SYNC_NEGO 0x02 /* Sync negotiation */ 133#define NTC_DO_PARITY_CHK 0x01 /* Parity check enable */ 134 uint8_t period; /* Target period */ 135 uint8_t config2; /* Target configuration byte 2 */ 136 uint8_t config3; /* Target configuration byte 3 */ 137}; 138 139struct trm_nvram { 140 uint8_t subvendor_id[2]; /* 0,1 Sub Vendor ID */ 141 uint8_t subsys_id[2]; /* 2,3 Sub System ID */ 142 uint8_t subclass; /* 4 Sub Class */ 143 uint8_t vendor_id[2]; /* 5,6 Vendor ID */ 144 uint8_t device_id[2]; /* 7,8 Device ID */ 145 uint8_t reserved0; /* 9 Reserved */ 146 struct nvram_target target[TRM_MAX_TARGETS]; 147 /* 10,11,12,13 148 * 14,15,16,17 149 * .... 150 * 70,71,72,73 */ 151 uint8_t scsi_id; /* 74 Host Adapter SCSI ID */ 152 uint8_t channel_cfg; /* 75 Channel configuration */ 153#define NAC_SCANLUN 0x20 /* Include LUN as BIOS device */ 154#define NAC_DO_PARITY_CHK 0x08 /* Parity check enable */ 155#define NAC_POWERON_SCSI_RESET 0x04 /* Power on reset enable */ 156#define NAC_GREATER_1G 0x02 /* > 1G support enable */ 157#define NAC_GT2DRIVES 0x01 /* Support more than 2 drives */ 158 uint8_t delay_time; /* 76 Power on delay time */ 159 uint8_t max_tag; /* 77 Maximum tags */ 160 uint8_t reserved1; /* 78 */ 161 uint8_t boot_target; /* 79 */ 162 uint8_t boot_lun; /* 80 */ 163 uint8_t reserved2; /* 81 */ 164 uint8_t reserved3[44]; /* 82,..125 */ 165 uint8_t checksum0; /* 126 */ 166 uint8_t checksum1; /* 127 */ 167#define TRM_NVRAM_CKSUM 0x1234 168}; 169 170/* Nvram Initiater bits definition */ 171#define MORE2_DRV 0x00000001 172#define GREATER_1G 0x00000002 173#define RST_SCSI_BUS 0x00000004 174#define ACTIVE_NEGATION 0x00000008 175#define NO_SEEK 0x00000010 176#define LUN_CHECK 0x00000020 177 178#define trm_eeprom_wait() DELAY(30) 179 180/* 181 *----------------------------------------------------------------------- 182 * SCSI Request Block 183 *----------------------------------------------------------------------- 184 */ 185struct trm_srb { 186 TAILQ_ENTRY(trm_srb) next; 187 188 struct trm_sg_entry *sgentry; 189 struct scsipi_xfer *xs; /* scsipi_xfer for this cmd */ 190 bus_dmamap_t dmap; 191 bus_size_t sgoffset; /* Xfer buf offset */ 192 193 uint32_t buflen; /* Total xfer length */ 194 uint32_t sgaddr; /* SGList physical starting address */ 195 196 int sgcnt; 197 int sgindex; 198 199 int hastat; /* Host Adapter Status */ 200#define H_STATUS_GOOD 0x00 201#define H_SEL_TIMEOUT 0x11 202#define H_OVER_UNDER_RUN 0x12 203#define H_UNEXP_BUS_FREE 0x13 204#define H_TARGET_PHASE_F 0x14 205#define H_INVALID_CCB_OP 0x16 206#define H_LINK_CCB_BAD 0x17 207#define H_BAD_TARGET_DIR 0x18 208#define H_DUPLICATE_CCB 0x19 209#define H_BAD_CCB_OR_SG 0x1A 210#define H_ABORT 0xFF 211 int tastat; /* Target SCSI Status Byte */ 212 int flag; /* SRBFlag */ 213#define AUTO_REQSENSE 0x0001 214#define PARITY_ERROR 0x0002 215#define SRB_TIMEOUT 0x0004 216 217 int cmdlen; /* SCSI command length */ 218 uint8_t cmd[12]; /* SCSI command */ 219 220 uint8_t tag[2]; 221}; 222 223/* 224 * some info about each target and lun on the SCSI bus 225 */ 226struct trm_linfo { 227 int used; /* number of slots in use */ 228 int avail; /* where to start scanning */ 229 int busy; /* lun in use */ 230 struct trm_srb *untagged; 231 struct trm_srb *queued[TRM_MAX_TAG]; 232}; 233 234struct trm_tinfo { 235 u_int flag; /* Sync mode ? (1 sync):(0 async) */ 236#define SYNC_NEGO_ENABLE 0x0001 237#define SYNC_NEGO_DOING 0x0002 238#define SYNC_NEGO_DONE 0x0004 239#define WIDE_NEGO_ENABLE 0x0008 240#define WIDE_NEGO_DOING 0x0010 241#define WIDE_NEGO_DONE 0x0020 242#define USE_TAG_QUEUING 0x0040 243#define NO_RESELECT 0x0080 244 struct trm_linfo *linfo[TRM_MAX_LUNS]; 245 246 uint8_t config0; /* Target Config */ 247 uint8_t period; /* Max Period for nego. */ 248 uint8_t synctl; /* Sync control for reg. */ 249 uint8_t offset; /* Sync offset for reg. and nego.(low nibble) */ 250}; 251 252/* 253 *----------------------------------------------------------------------- 254 * Adapter Control Block 255 *----------------------------------------------------------------------- 256 */ 257struct trm_softc { 258 device_t sc_dev; 259 260 bus_space_tag_t sc_iot; 261 bus_space_handle_t sc_ioh; 262 bus_dma_tag_t sc_dmat; 263 bus_dmamap_t sc_dmamap; /* Map the control structures */ 264 265 struct trm_srb *sc_actsrb; 266 struct trm_tinfo sc_tinfo[TRM_MAX_TARGETS]; 267 268 TAILQ_HEAD(, trm_srb) sc_freesrb, 269 sc_readysrb; 270 struct trm_srb *sc_srb; /* SRB array */ 271 272 struct trm_sg_entry *sc_sglist; 273 274 int sc_maxid; 275 /* 276 * Link to the generic SCSI driver 277 */ 278 struct scsipi_channel sc_channel; 279 struct scsipi_adapter sc_adapter; 280 281 int sc_id; /* Adapter SCSI Target ID */ 282 283 int sc_state; /* SRB State */ 284#define TRM_IDLE 0 285#define TRM_WAIT 1 286#define TRM_READY 2 287#define TRM_MSGOUT 3 /* arbitration+msg_out 1st byte */ 288#define TRM_MSGIN 4 289#define TRM_EXTEND_MSGIN 5 290#define TRM_COMMAND 6 291#define TRM_START 7 /* arbitration+msg_out+command_out */ 292#define TRM_DISCONNECTED 8 293#define TRM_DATA_XFER 9 294#define TRM_XFERPAD 10 295#define TRM_STATUS 11 296#define TRM_COMPLETED 12 297#define TRM_ABORT_SENT 13 298#define TRM_UNEXPECT_RESEL 14 299 300 int sc_phase; /* SCSI phase */ 301 int sc_config; 302#define HCC_WIDE_CARD 0x01 303#define HCC_SCSI_RESET 0x02 304#define HCC_PARITY 0x04 305#define HCC_AUTOTERM 0x08 306#define HCC_LOW8TERM 0x10 307#define HCC_UP8TERM 0x20 308 309 int sc_flag; 310#define RESET_DEV 0x01 311#define RESET_DETECT 0x02 312#define RESET_DONE 0x04 313#define WAIT_TAGMSG 0x08 /* XXX */ 314 315 int sc_msgcnt; 316 317 int resel_target; /* XXX */ 318 int resel_lun; /* XXX */ 319 320 uint8_t *sc_msg; 321 uint8_t sc_msgbuf[6]; 322}; 323 324/* 325 * SCSI Status codes not defined in scsi_all.h 326 */ 327#define SCSI_COND_MET 0x04 /* Condition Met */ 328#define SCSI_INTERM_COND_MET 0x14 /* Intermediate condition met */ 329#define SCSI_UNEXP_BUS_FREE 0xFD /* Unexpected Bus Free */ 330#define SCSI_BUS_RST_DETECT 0xFE /* SCSI Bus Reset detected */ 331#define SCSI_SEL_TIMEOUT 0xFF /* Selection Timeout */ 332 333static int trm_match(device_t, cfdata_t, void *); 334static void trm_attach(device_t, device_t, void *); 335 336static int trm_init(struct trm_softc *); 337 338static void trm_scsipi_request(struct scsipi_channel *, scsipi_adapter_req_t, 339 void *); 340static void trm_update_xfer_mode(struct trm_softc *, int); 341static void trm_sched(struct trm_softc *); 342static int trm_select(struct trm_softc *, struct trm_srb *); 343static void trm_reset(struct trm_softc *); 344static void trm_timeout(void *); 345static int trm_intr(void *); 346 347static void trm_dataout_phase0(struct trm_softc *, int); 348static void trm_datain_phase0(struct trm_softc *, int); 349static void trm_status_phase0(struct trm_softc *); 350static void trm_msgin_phase0(struct trm_softc *); 351static void trm_command_phase1(struct trm_softc *); 352static void trm_status_phase1(struct trm_softc *); 353static void trm_msgout_phase1(struct trm_softc *); 354static void trm_msgin_phase1(struct trm_softc *); 355 356static void trm_dataio_xfer(struct trm_softc *, int); 357static void trm_disconnect(struct trm_softc *); 358static void trm_reselect(struct trm_softc *); 359static void trm_done(struct trm_softc *, struct trm_srb *); 360static int trm_request_sense(struct trm_softc *, struct trm_srb *); 361static void trm_dequeue(struct trm_softc *, struct trm_srb *); 362 363static void trm_scsi_reset_detect(struct trm_softc *); 364static void trm_reset_scsi_bus(struct trm_softc *); 365 366static void trm_check_eeprom(struct trm_softc *, struct trm_nvram *); 367static void trm_eeprom_read_all(struct trm_softc *, struct trm_nvram *); 368static void trm_eeprom_write_all(struct trm_softc *, struct trm_nvram *); 369static void trm_eeprom_set_data(struct trm_softc *, uint8_t, uint8_t); 370static void trm_eeprom_write_cmd(struct trm_softc *, uint8_t, uint8_t); 371static uint8_t trm_eeprom_get_data(struct trm_softc *, uint8_t); 372 373CFATTACH_DECL_NEW(trm, sizeof(struct trm_softc), 374 trm_match, trm_attach, NULL, NULL); 375 376/* real period: */ 377static const uint8_t trm_clock_period[] = { 378 12, /* 48 ns 20.0 MB/sec */ 379 18, /* 72 ns 13.3 MB/sec */ 380 25, /* 100 ns 10.0 MB/sec */ 381 31, /* 124 ns 8.0 MB/sec */ 382 37, /* 148 ns 6.6 MB/sec */ 383 43, /* 172 ns 5.7 MB/sec */ 384 50, /* 200 ns 5.0 MB/sec */ 385 62 /* 248 ns 4.0 MB/sec */ 386}; 387#define NPERIOD __arraycount(trm_clock_period) 388 389static int 390trm_match(device_t parent, cfdata_t cf, void *aux) 391{ 392 struct pci_attach_args *pa = aux; 393 394 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TEKRAM2) 395 switch (PCI_PRODUCT(pa->pa_id)) { 396 case PCI_PRODUCT_TEKRAM2_DC315: 397 return 1; 398 } 399 return 0; 400} 401 402/* 403 * attach and init a host adapter 404 */ 405static void 406trm_attach(device_t parent, device_t self, void *aux) 407{ 408 struct trm_softc *sc = device_private(self); 409 struct pci_attach_args *const pa = aux; 410 bus_space_tag_t iot; 411 bus_space_handle_t ioh; 412 pci_intr_handle_t ih; 413 pcireg_t command; 414 const char *intrstr; 415 416 sc->sc_dev = self; 417 418 /* 419 * These cards do not allow memory mapped accesses 420 * pa_pc: chipset tag 421 * pa_tag: pci tag 422 */ 423 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 424 if ((command & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE)) != 425 (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE)) { 426 command |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE; 427 pci_conf_write(pa->pa_pc, pa->pa_tag, 428 PCI_COMMAND_STATUS_REG, command); 429 } 430 /* 431 * mask for get correct base address of pci IO port 432 */ 433 if (pci_mapreg_map(pa, PCI_MAPREG_START, PCI_MAPREG_TYPE_IO, 0, 434 &iot, &ioh, NULL, NULL)) { 435 aprint_error(": unable to map registers\n"); 436 return; 437 } 438 /* 439 * test checksum of eeprom.. & initialize softc... 440 */ 441 sc->sc_iot = iot; 442 sc->sc_ioh = ioh; 443 sc->sc_dmat = pa->pa_dmat; 444 445 if (trm_init(sc) != 0) { 446 /* 447 * Error during initialization! 448 */ 449 return; 450 } 451 /* 452 * Now try to attach all the sub-devices 453 */ 454 if ((sc->sc_config & HCC_WIDE_CARD) != 0) 455 aprint_normal(": Tekram DC395UW/F (TRM-S1040) Fast40 " 456 "Ultra Wide SCSI Adapter\n"); 457 else 458 aprint_normal(": Tekram DC395U, DC315/U (TRM-S1040) Fast20 " 459 "Ultra SCSI Adapter\n"); 460 461 /* 462 * Now tell the generic SCSI layer about our bus. 463 * map and establish interrupt 464 */ 465 if (pci_intr_map(pa, &ih)) { 466 aprint_error_dev(self, "couldn't map interrupt\n"); 467 return; 468 } 469 intrstr = pci_intr_string(pa->pa_pc, ih); 470 471 if (pci_intr_establish(pa->pa_pc, ih, IPL_BIO, trm_intr, sc) == NULL) { 472 aprint_error_dev(self, "couldn't establish interrupt"); 473 if (intrstr != NULL) 474 aprint_error(" at %s", intrstr); 475 aprint_error("\n"); 476 return; 477 } 478 if (intrstr != NULL) 479 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 480 481 sc->sc_adapter.adapt_dev = self; 482 sc->sc_adapter.adapt_nchannels = 1; 483 sc->sc_adapter.adapt_openings = TRM_MAX_SRB; 484 sc->sc_adapter.adapt_max_periph = TRM_MAX_SRB; 485 sc->sc_adapter.adapt_request = trm_scsipi_request; 486 sc->sc_adapter.adapt_minphys = minphys; 487 488 sc->sc_channel.chan_adapter = &sc->sc_adapter; 489 sc->sc_channel.chan_bustype = &scsi_bustype; 490 sc->sc_channel.chan_channel = 0; 491 sc->sc_channel.chan_ntargets = sc->sc_maxid + 1; 492 sc->sc_channel.chan_nluns = 8; 493 sc->sc_channel.chan_id = sc->sc_id; 494 495 config_found(self, &sc->sc_channel, scsiprint); 496} 497 498/* 499 * initialize the internal structures for a given SCSI host 500 */ 501static int 502trm_init(struct trm_softc *sc) 503{ 504 bus_space_tag_t iot = sc->sc_iot; 505 bus_space_handle_t ioh = sc->sc_ioh; 506 bus_dma_segment_t seg; 507 struct trm_nvram eeprom; 508 struct trm_srb *srb; 509 struct trm_tinfo *ti; 510 struct nvram_target *tconf; 511 int error, rseg, all_sgsize; 512 int i, target; 513 uint8_t bval; 514 515 DPRINTF(("\n")); 516 517 /* 518 * allocate the space for all SCSI control blocks (SRB) for DMA memory 519 */ 520 all_sgsize = TRM_MAX_SRB * TRM_SG_SIZE; 521 if ((error = bus_dmamem_alloc(sc->sc_dmat, all_sgsize, PAGE_SIZE, 522 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 523 aprint_error(": unable to allocate SCSI REQUEST BLOCKS, " 524 "error = %d\n", error); 525 return 1; 526 } 527 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 528 all_sgsize, (void **) &sc->sc_sglist, 529 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 530 aprint_error(": unable to map SCSI REQUEST BLOCKS, " 531 "error = %d\n", error); 532 return 1; 533 } 534 if ((error = bus_dmamap_create(sc->sc_dmat, all_sgsize, 1, 535 all_sgsize, 0, BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 536 aprint_error(": unable to create SRB DMA maps, " 537 "error = %d\n", error); 538 return 1; 539 } 540 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 541 sc->sc_sglist, all_sgsize, NULL, BUS_DMA_NOWAIT)) != 0) { 542 aprint_error(": unable to load SRB DMA maps, " 543 "error = %d\n", error); 544 return 1; 545 } 546 DPRINTF(("all_sgsize=%x\n", all_sgsize)); 547 memset(sc->sc_sglist, 0, all_sgsize); 548 549 /* 550 * EEPROM CHECKSUM 551 */ 552 trm_check_eeprom(sc, &eeprom); 553 554 sc->sc_maxid = 7; 555 sc->sc_config = HCC_AUTOTERM | HCC_PARITY; 556 if (bus_space_read_1(iot, ioh, TRM_GEN_STATUS) & WIDESCSI) { 557 sc->sc_config |= HCC_WIDE_CARD; 558 sc->sc_maxid = 15; 559 } 560 if (eeprom.channel_cfg & NAC_POWERON_SCSI_RESET) 561 sc->sc_config |= HCC_SCSI_RESET; 562 563 sc->sc_actsrb = NULL; 564 sc->sc_id = eeprom.scsi_id; 565 sc->sc_flag = 0; 566 567 /* 568 * initialize and link all device's SRB queues of this adapter 569 */ 570 TAILQ_INIT(&sc->sc_freesrb); 571 TAILQ_INIT(&sc->sc_readysrb); 572 573 sc->sc_srb = malloc(sizeof(struct trm_srb) * TRM_MAX_SRB, 574 M_DEVBUF, M_NOWAIT|M_ZERO); 575 DPRINTF(("all SRB size=%zx\n", sizeof(struct trm_srb) * TRM_MAX_SRB)); 576 if (sc->sc_srb == NULL) { 577 aprint_error(": can not allocate SRB\n"); 578 return 1; 579 } 580 581 for (i = 0, srb = sc->sc_srb; i < TRM_MAX_SRB; i++) { 582 srb->sgentry = sc->sc_sglist + TRM_MAX_SG_ENTRIES * i; 583 srb->sgoffset = TRM_SG_SIZE * i; 584 srb->sgaddr = sc->sc_dmamap->dm_segs[0].ds_addr + srb->sgoffset; 585 /* 586 * map all SRB space to SRB_array 587 */ 588 if (bus_dmamap_create(sc->sc_dmat, 589 MAXPHYS, TRM_MAX_SG_ENTRIES, MAXPHYS, 0, 590 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &srb->dmap)) { 591 aprint_error(": unable to create DMA transfer map.\n"); 592 free(sc->sc_srb, M_DEVBUF); 593 return 1; 594 } 595 TAILQ_INSERT_TAIL(&sc->sc_freesrb, srb, next); 596 srb++; 597 } 598 599 /* 600 * initialize all target info structures 601 */ 602 for (target = 0; target < TRM_MAX_TARGETS; target++) { 603 ti = &sc->sc_tinfo[target]; 604 ti->synctl = 0; 605 ti->offset = 0; 606 tconf = &eeprom.target[target]; 607 ti->config0 = tconf->config0; 608 ti->period = trm_clock_period[tconf->period & 0x07]; 609 ti->flag = 0; 610 if ((ti->config0 & NTC_DO_DISCONNECT) != 0) { 611#ifdef notyet 612 if ((ti->config0 & NTC_DO_TAG_QUEUING) != 0) 613 ti->flag |= USE_TAG_QUEUING; 614#endif 615 } else 616 ti->flag |= NO_RESELECT; 617 618 DPRINTF(("target %d: config0 = 0x%02x, period = 0x%02x", 619 target, ti->config0, ti->period)); 620 DPRINTF((", flag = 0x%02x\n", ti->flag)); 621 } 622 623 /* program configuration 0 */ 624 bval = PHASELATCH | INITIATOR | BLOCKRST; 625 if ((sc->sc_config & HCC_PARITY) != 0) 626 bval |= PARITYCHECK; 627 bus_space_write_1(iot, ioh, TRM_SCSI_CONFIG0, bval); 628 629 /* program configuration 1 */ 630 bus_space_write_1(iot, ioh, TRM_SCSI_CONFIG1, 631 ACTIVE_NEG | ACTIVE_NEGPLUS); 632 633 /* 250ms selection timeout */ 634 bus_space_write_1(iot, ioh, TRM_SCSI_TIMEOUT, SEL_TIMEOUT); 635 636 /* Mask all interrupts */ 637 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, 0); 638 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 0); 639 640 /* Reset SCSI module */ 641 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_RSTMODULE); 642 643 /* program Host ID */ 644 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 645 646 /* set asynchronous transfer */ 647 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, 0); 648 649 /* Turn LED control off */ 650 bus_space_write_2(iot, ioh, TRM_GEN_CONTROL, 651 bus_space_read_2(iot, ioh, TRM_GEN_CONTROL) & ~EN_LED); 652 653 /* DMA config */ 654 bus_space_write_2(iot, ioh, TRM_DMA_CONFIG, 655 bus_space_read_2(iot, ioh, TRM_DMA_CONFIG) | DMA_ENHANCE); 656 657 /* Clear pending interrupt status */ 658 (void)bus_space_read_1(iot, ioh, TRM_SCSI_INTSTATUS); 659 660 /* Enable SCSI interrupt */ 661 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 662 EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED | 663 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE); 664 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, EN_SCSIINTR); 665 666 trm_reset(sc); 667 668 return 0; 669} 670 671/* 672 * enqueues a SCSI command 673 * called by the higher level SCSI driver 674 */ 675static void 676trm_scsipi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req, 677 void *arg) 678{ 679 bus_space_tag_t iot; 680 bus_space_handle_t ioh; 681 struct trm_softc *sc; 682 struct trm_srb *srb; 683 struct scsipi_xfer *xs; 684 int error, i, target, lun, s; 685 686 sc = device_private(chan->chan_adapter->adapt_dev); 687 iot = sc->sc_iot; 688 ioh = sc->sc_ioh; 689 690 switch (req) { 691 case ADAPTER_REQ_RUN_XFER: 692 xs = arg; 693 target = xs->xs_periph->periph_target; 694 lun = xs->xs_periph->periph_lun; 695 DPRINTF(("trm_scsipi_request.....\n")); 696 DPRINTF(("target= %d lun= %d\n", target, lun)); 697 if (xs->xs_control & XS_CTL_RESET) { 698 trm_reset(sc); 699 xs->error = XS_NOERROR | XS_RESET; 700 return; 701 } 702 if (xs->xs_status & XS_STS_DONE) { 703 printf("%s: Is it done?\n", device_xname(sc->sc_dev)); 704 xs->xs_status &= ~XS_STS_DONE; 705 } 706 707 s = splbio(); 708 709 /* Get SRB */ 710 srb = TAILQ_FIRST(&sc->sc_freesrb); 711 if (srb != NULL) { 712 TAILQ_REMOVE(&sc->sc_freesrb, srb, next); 713 } else { 714 xs->error = XS_RESOURCE_SHORTAGE; 715 scsipi_done(xs); 716 splx(s); 717 return; 718 } 719 720 srb->xs = xs; 721 srb->cmdlen = xs->cmdlen; 722 memcpy(srb->cmd, xs->cmd, xs->cmdlen); 723 724 if (xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) { 725 if ((error = bus_dmamap_load(sc->sc_dmat, srb->dmap, 726 xs->data, xs->datalen, NULL, 727 ((xs->xs_control & XS_CTL_NOSLEEP) ? 728 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | 729 BUS_DMA_STREAMING | 730 ((xs->xs_control & XS_CTL_DATA_IN) ? 731 BUS_DMA_READ : BUS_DMA_WRITE))) != 0) { 732 printf("%s: DMA transfer map unable to load, " 733 "error = %d\n", device_xname(sc->sc_dev), 734 error); 735 xs->error = XS_DRIVER_STUFFUP; 736 /* 737 * free SRB 738 */ 739 TAILQ_INSERT_TAIL(&sc->sc_freesrb, srb, next); 740 splx(s); 741 return; 742 } 743 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 744 srb->dmap->dm_mapsize, 745 (xs->xs_control & XS_CTL_DATA_IN) ? 746 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 747 748 /* Set up the scatter gather list */ 749 for (i = 0; i < srb->dmap->dm_nsegs; i++) { 750 srb->sgentry[i].address = 751 htole32(srb->dmap->dm_segs[i].ds_addr); 752 srb->sgentry[i].length = 753 htole32(srb->dmap->dm_segs[i].ds_len); 754 } 755 srb->buflen = xs->datalen; 756 srb->sgcnt = srb->dmap->dm_nsegs; 757 } else { 758 srb->sgentry[0].address = 0; 759 srb->sgentry[0].length = 0; 760 srb->buflen = 0; 761 srb->sgcnt = 0; 762 } 763 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 764 srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 765 766 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 767 768 srb->sgindex = 0; 769 srb->hastat = 0; 770 srb->tastat = 0; 771 srb->flag = 0; 772 773 TAILQ_INSERT_TAIL(&sc->sc_readysrb, srb, next); 774 if (sc->sc_actsrb == NULL) 775 trm_sched(sc); 776 splx(s); 777 778 if ((xs->xs_control & XS_CTL_POLL) != 0) { 779 int timeout = xs->timeout; 780 781 s = splbio(); 782 do { 783 while (--timeout) { 784 DELAY(1000); 785 if (bus_space_read_2(iot, ioh, 786 TRM_SCSI_STATUS) & SCSIINTERRUPT) 787 break; 788 } 789 if (timeout == 0) { 790 trm_timeout(srb); 791 break; 792 } else 793 trm_intr(sc); 794 } while ((xs->xs_status & XS_STS_DONE) == 0); 795 splx(s); 796 } 797 return; 798 799 case ADAPTER_REQ_GROW_RESOURCES: 800 /* XXX Not supported. */ 801 return; 802 803 case ADAPTER_REQ_SET_XFER_MODE: 804 { 805 struct trm_tinfo *ti; 806 struct scsipi_xfer_mode *xm; 807 808 xm = arg; 809 ti = &sc->sc_tinfo[xm->xm_target]; 810 ti->flag &= ~(SYNC_NEGO_ENABLE|WIDE_NEGO_ENABLE); 811 812#ifdef notyet 813 if ((xm->xm_mode & PERIPH_CAP_TQING) != 0) 814 ti->flag |= USE_TAG_QUEUING; 815 else 816#endif 817 ti->flag &= ~USE_TAG_QUEUING; 818 819 if ((xm->xm_mode & PERIPH_CAP_WIDE16) != 0 && 820 (sc->sc_config & HCC_WIDE_CARD) != 0 && 821 (ti->config0 & NTC_DO_WIDE_NEGO) != 0) { 822 ti->flag |= WIDE_NEGO_ENABLE; 823 ti->flag &= ~WIDE_NEGO_DONE; 824 } 825 826 if ((xm->xm_mode & PERIPH_CAP_SYNC) != 0 && 827 (ti->config0 & NTC_DO_SYNC_NEGO) != 0) { 828 ti->flag |= SYNC_NEGO_ENABLE; 829 ti->flag &= ~SYNC_NEGO_DONE; 830 ti->period = trm_clock_period[0]; 831 } 832 833 /* 834 * If we're not going to negotiate, send the 835 * notification now, since it won't happen later. 836 */ 837 if ((ti->flag & (WIDE_NEGO_DONE|SYNC_NEGO_DONE)) == 838 (WIDE_NEGO_DONE|SYNC_NEGO_DONE)) 839 trm_update_xfer_mode(sc, xm->xm_target); 840 841 return; 842 } 843 } 844} 845 846static void 847trm_update_xfer_mode(struct trm_softc *sc, int target) 848{ 849 struct scsipi_xfer_mode xm; 850 struct trm_tinfo *ti; 851 852 ti = &sc->sc_tinfo[target]; 853 xm.xm_target = target; 854 xm.xm_mode = 0; 855 xm.xm_period = 0; 856 xm.xm_offset = 0; 857 858 if ((ti->synctl & WIDE_SYNC) != 0) 859 xm.xm_mode |= PERIPH_CAP_WIDE16; 860 861 if (ti->period > 0) { 862 xm.xm_mode |= PERIPH_CAP_SYNC; 863 xm.xm_period = ti->period; 864 xm.xm_offset = ti->offset; 865 } 866 867#ifdef notyet 868 if ((ti->flag & USE_TAG_QUEUING) != 0) 869 xm.xm_mode |= PERIPH_CAP_TQING; 870#endif 871 872 scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_XFER_MODE, &xm); 873} 874 875static void 876trm_sched(struct trm_softc *sc) 877{ 878 struct trm_srb *srb; 879 struct scsipi_periph *periph; 880 struct trm_tinfo *ti; 881 struct trm_linfo *li; 882 int s, lun, tag; 883 884 DPRINTF(("trm_sched...\n")); 885 886 TAILQ_FOREACH(srb, &sc->sc_readysrb, next) { 887 periph = srb->xs->xs_periph; 888 ti = &sc->sc_tinfo[periph->periph_target]; 889 lun = periph->periph_lun; 890 891 /* select type of tag for this command */ 892 if ((ti->flag & NO_RESELECT) != 0 || 893 (ti->flag & USE_TAG_QUEUING) == 0 || 894 (srb->flag & AUTO_REQSENSE) != 0 || 895 (srb->xs->xs_control & XS_CTL_REQSENSE) != 0) 896 tag = 0; 897 else 898 tag = srb->xs->xs_tag_type; 899#if 0 900 /* XXX use tags for polled commands? */ 901 if (srb->xs->xs_control & XS_CTL_POLL) 902 tag = 0; 903#endif 904 905 s = splbio(); 906 li = ti->linfo[lun]; 907 if (li == NULL) { 908 /* initialize lun info */ 909 if ((li = malloc(sizeof(*li), M_DEVBUF, 910 M_NOWAIT|M_ZERO)) == NULL) { 911 splx(s); 912 continue; 913 } 914 ti->linfo[lun] = li; 915 } 916 917 if (tag == 0) { 918 /* try to issue this srb as an un-tagged command */ 919 if (li->untagged == NULL) 920 li->untagged = srb; 921 } 922 if (li->untagged != NULL) { 923 tag = 0; 924 if (li->busy != 1 && li->used == 0) { 925 /* we need to issue the untagged command now */ 926 srb = li->untagged; 927 periph = srb->xs->xs_periph; 928 } else { 929 /* not ready yet */ 930 splx(s); 931 continue; 932 } 933 } 934 srb->tag[0] = tag; 935 if (tag != 0) { 936 li->queued[srb->xs->xs_tag_id] = srb; 937 srb->tag[1] = srb->xs->xs_tag_id; 938 li->used++; 939 } 940 941 if (li->untagged != NULL && li->busy != 1) { 942 li->busy = 1; 943 TAILQ_REMOVE(&sc->sc_readysrb, srb, next); 944 sc->sc_actsrb = srb; 945 trm_select(sc, srb); 946 splx(s); 947 break; 948 } 949 if (li->untagged == NULL && tag != 0) { 950 TAILQ_REMOVE(&sc->sc_readysrb, srb, next); 951 sc->sc_actsrb = srb; 952 trm_select(sc, srb); 953 splx(s); 954 break; 955 } else 956 splx(s); 957 } 958} 959 960static int 961trm_select(struct trm_softc *sc, struct trm_srb *srb) 962{ 963 bus_space_tag_t iot = sc->sc_iot; 964 bus_space_handle_t ioh = sc->sc_ioh; 965 struct scsipi_periph *periph = srb->xs->xs_periph; 966 int target = periph->periph_target; 967 int lun = periph->periph_lun; 968 struct trm_tinfo *ti = &sc->sc_tinfo[target]; 969 uint8_t scsicmd; 970 971 DPRINTF(("trm_select.....\n")); 972 973 if ((srb->xs->xs_control & XS_CTL_POLL) == 0) { 974 callout_reset(&srb->xs->xs_callout, mstohz(srb->xs->timeout), 975 trm_timeout, srb); 976 } 977 978 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 979 bus_space_write_1(iot, ioh, TRM_SCSI_TARGETID, target); 980 bus_space_write_1(iot, ioh, TRM_SCSI_SYNC, ti->synctl); 981 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, ti->offset); 982 /* Flush FIFO */ 983 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 984 DELAY(10); 985 986 sc->sc_phase = PH_BUS_FREE; /* initial phase */ 987 988 DPRINTF(("cmd = 0x%02x\n", srb->cmd[0])); 989 990 if (((ti->flag & WIDE_NEGO_ENABLE) && 991 (ti->flag & WIDE_NEGO_DONE) == 0) || 992 ((ti->flag & SYNC_NEGO_ENABLE) && 993 (ti->flag & SYNC_NEGO_DONE) == 0)) { 994 sc->sc_state = TRM_MSGOUT; 995 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 996 MSG_IDENTIFY(lun, 0)); 997 bus_space_write_multi_1(iot, ioh, 998 TRM_SCSI_FIFO, srb->cmd, srb->cmdlen); 999 /* it's important for atn stop */ 1000 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1001 DO_DATALATCH | DO_HWRESELECT); 1002 /* SCSI command */ 1003 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_SEL_ATNSTOP); 1004 DPRINTF(("select with SEL_ATNSTOP\n")); 1005 return 0; 1006 } 1007 1008 if (srb->tag[0] != 0) { 1009 /* Send identify message */ 1010 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1011 MSG_IDENTIFY(lun, 1)); 1012 /* Send Tag id */ 1013 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, srb->tag[0]); 1014 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, srb->tag[1]); 1015 scsicmd = SCMD_SEL_ATN3; 1016 DPRINTF(("select with SEL_ATN3\n")); 1017 } else { 1018 /* Send identify message */ 1019 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1020 MSG_IDENTIFY(lun, 1021 (ti->flag & NO_RESELECT) == 0 && 1022 (srb->flag & AUTO_REQSENSE) == 0 && 1023 (srb->xs->xs_control & XS_CTL_REQSENSE) == 0)); 1024 scsicmd = SCMD_SEL_ATN; 1025 DPRINTF(("select with SEL_ATN\n")); 1026 } 1027 sc->sc_state = TRM_START; 1028 1029 /* 1030 * Send CDB ..command block... 1031 */ 1032 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, srb->cmd, srb->cmdlen); 1033 1034 /* 1035 * If trm_select returns 0: current interrupt status 1036 * is interrupt enable. It's said that SCSI processor is 1037 * unoccupied. 1038 */ 1039 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 1040 /* SCSI command */ 1041 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, scsicmd); 1042 return 0; 1043} 1044 1045/* 1046 * perform a hard reset on the SCSI bus (and TRM_S1040 chip). 1047 */ 1048static void 1049trm_reset(struct trm_softc *sc) 1050{ 1051 bus_space_tag_t iot = sc->sc_iot; 1052 bus_space_handle_t ioh = sc->sc_ioh; 1053 int s; 1054 1055 DPRINTF(("trm_reset.........\n")); 1056 1057 s = splbio(); 1058 1059 /* disable SCSI and DMA interrupt */ 1060 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, 0); 1061 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 0); 1062 1063 trm_reset_scsi_bus(sc); 1064 DELAY(100000); 1065 1066 /* Enable SCSI interrupt */ 1067 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 1068 EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED | 1069 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE); 1070 1071 /* Enable DMA interrupt */ 1072 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, EN_SCSIINTR); 1073 1074 /* Clear DMA FIFO */ 1075 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 1076 1077 /* Clear SCSI FIFO */ 1078 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1079 1080 sc->sc_actsrb = NULL; 1081 sc->sc_flag = 0; /* RESET_DETECT, RESET_DONE, RESET_DEV */ 1082 1083 splx(s); 1084} 1085 1086static void 1087trm_timeout(void *arg) 1088{ 1089 struct trm_srb *srb = (struct trm_srb *)arg; 1090 struct scsipi_xfer *xs; 1091 struct scsipi_periph *periph; 1092 struct trm_softc *sc; 1093 int s; 1094 1095 if (srb == NULL) { 1096 printf("trm_timeout called with srb == NULL\n"); 1097 return; 1098 } 1099 1100 xs = srb->xs; 1101 if (xs == NULL) { 1102 printf("trm_timeout called with xs == NULL\n"); 1103 return; 1104 } 1105 1106 periph = xs->xs_periph; 1107 scsipi_printaddr(xs->xs_periph); 1108 printf("SCSI OpCode 0x%02x timed out\n", xs->cmd->opcode); 1109 1110 sc = device_private(periph->periph_channel->chan_adapter->adapt_dev); 1111 1112 trm_reset_scsi_bus(sc); 1113 s = splbio(); 1114 srb->flag |= SRB_TIMEOUT; 1115 trm_done(sc, srb); 1116 /* XXX needs more.. */ 1117 splx(s); 1118} 1119 1120/* 1121 * Catch an interrupt from the adapter 1122 * Process pending device interrupts. 1123 */ 1124static int 1125trm_intr(void *arg) 1126{ 1127 bus_space_tag_t iot; 1128 bus_space_handle_t ioh; 1129 struct trm_softc *sc; 1130 int intstat, stat; 1131 1132 DPRINTF(("trm_intr......\n")); 1133 sc = arg; 1134 if (sc == NULL) 1135 return 0; 1136 1137 iot = sc->sc_iot; 1138 ioh = sc->sc_ioh; 1139 1140 stat = bus_space_read_2(iot, ioh, TRM_SCSI_STATUS); 1141 if ((stat & SCSIINTERRUPT) == 0) 1142 return 0; 1143 1144 DPRINTF(("stat = %04x, ", stat)); 1145 intstat = bus_space_read_1(iot, ioh, TRM_SCSI_INTSTATUS); 1146 1147 DPRINTF(("intstat=%02x, ", intstat)); 1148 if (intstat & (INT_SELTIMEOUT | INT_DISCONNECT)) { 1149 DPRINTF(("\n")); 1150 trm_disconnect(sc); 1151 return 1; 1152 } 1153 if (intstat & INT_RESELECTED) { 1154 DPRINTF(("\n")); 1155 trm_reselect(sc); 1156 return 1; 1157 } 1158 if (intstat & INT_SCSIRESET) { 1159 DPRINTF(("\n")); 1160 trm_scsi_reset_detect(sc); 1161 return 1; 1162 } 1163 if (intstat & (INT_BUSSERVICE | INT_CMDDONE)) { 1164 DPRINTF(("sc->sc_phase = %2d, sc->sc_state = %2d\n", 1165 sc->sc_phase, sc->sc_state)); 1166 /* 1167 * software sequential machine 1168 */ 1169 1170 /* 1171 * call phase0 functions... "phase entry" handle 1172 * every phase before start transfer 1173 */ 1174 switch (sc->sc_phase) { 1175 case PH_DATA_OUT: 1176 trm_dataout_phase0(sc, stat); 1177 break; 1178 case PH_DATA_IN: 1179 trm_datain_phase0(sc, stat); 1180 break; 1181 case PH_COMMAND: 1182 break; 1183 case PH_STATUS: 1184 trm_status_phase0(sc); 1185 stat = PH_BUS_FREE; 1186 break; 1187 case PH_MSG_OUT: 1188 if (sc->sc_state == TRM_UNEXPECT_RESEL || 1189 sc->sc_state == TRM_ABORT_SENT) 1190 stat = PH_BUS_FREE; 1191 break; 1192 case PH_MSG_IN: 1193 trm_msgin_phase0(sc); 1194 stat = PH_BUS_FREE; 1195 break; 1196 case PH_BUS_FREE: 1197 break; 1198 default: 1199 printf("%s: unexpected phase in trm_intr() phase0\n", 1200 device_xname(sc->sc_dev)); 1201 break; 1202 } 1203 1204 sc->sc_phase = stat & PHASEMASK; 1205 1206 switch (sc->sc_phase) { 1207 case PH_DATA_OUT: 1208 trm_dataio_xfer(sc, XFERDATAOUT); 1209 break; 1210 case PH_DATA_IN: 1211 trm_dataio_xfer(sc, XFERDATAIN); 1212 break; 1213 case PH_COMMAND: 1214 trm_command_phase1(sc); 1215 break; 1216 case PH_STATUS: 1217 trm_status_phase1(sc); 1218 break; 1219 case PH_MSG_OUT: 1220 trm_msgout_phase1(sc); 1221 break; 1222 case PH_MSG_IN: 1223 trm_msgin_phase1(sc); 1224 break; 1225 case PH_BUS_FREE: 1226 break; 1227 default: 1228 printf("%s: unexpected phase in trm_intr() phase1\n", 1229 device_xname(sc->sc_dev)); 1230 break; 1231 } 1232 1233 return 1; 1234 } 1235 return 0; 1236} 1237 1238static void 1239trm_msgout_phase1(struct trm_softc *sc) 1240{ 1241 bus_space_tag_t iot = sc->sc_iot; 1242 bus_space_handle_t ioh = sc->sc_ioh; 1243 struct trm_srb *srb; 1244 struct scsipi_periph *periph; 1245 struct trm_tinfo *ti; 1246 1247 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1248 1249 srb = sc->sc_actsrb; 1250 1251 /* message out phase */ 1252 if (srb != NULL) { 1253 periph = srb->xs->xs_periph; 1254 ti = &sc->sc_tinfo[periph->periph_target]; 1255 1256 if ((ti->flag & WIDE_NEGO_DOING) == 0 && 1257 (ti->flag & WIDE_NEGO_ENABLE)) { 1258 /* send WDTR */ 1259 ti->flag &= ~SYNC_NEGO_DONE; 1260 1261 sc->sc_msgbuf[0] = MSG_IDENTIFY(periph->periph_lun, 0); 1262 sc->sc_msgbuf[1] = MSG_EXTENDED; 1263 sc->sc_msgbuf[2] = MSG_EXT_WDTR_LEN; 1264 sc->sc_msgbuf[3] = MSG_EXT_WDTR; 1265 sc->sc_msgbuf[4] = MSG_EXT_WDTR_BUS_16_BIT; 1266 sc->sc_msgcnt = 5; 1267 1268 ti->flag |= WIDE_NEGO_DOING; 1269 } else if ((ti->flag & SYNC_NEGO_DOING) == 0 && 1270 (ti->flag & SYNC_NEGO_ENABLE)) { 1271 /* send SDTR */ 1272 int cnt = 0; 1273 1274 if ((ti->flag & WIDE_NEGO_DONE) == 0) 1275 sc->sc_msgbuf[cnt++] = 1276 MSG_IDENTIFY(periph->periph_lun, 0); 1277 1278 sc->sc_msgbuf[cnt++] = MSG_EXTENDED; 1279 sc->sc_msgbuf[cnt++] = MSG_EXT_SDTR_LEN; 1280 sc->sc_msgbuf[cnt++] = MSG_EXT_SDTR; 1281 sc->sc_msgbuf[cnt++] = ti->period; 1282 sc->sc_msgbuf[cnt++] = TRM_MAX_OFFSET; 1283 sc->sc_msgcnt = cnt; 1284 ti->flag |= SYNC_NEGO_DOING; 1285 } 1286 } 1287 if (sc->sc_msgcnt == 0) { 1288 sc->sc_msgbuf[0] = MSG_ABORT; 1289 sc->sc_msgcnt = 1; 1290 sc->sc_state = TRM_ABORT_SENT; 1291 } 1292 1293 DPRINTF(("msgout: cnt = %d, ", sc->sc_msgcnt)); 1294 DPRINTF(("msgbuf = %02x %02x %02x %02x %02x %02x\n", 1295 sc->sc_msgbuf[0], sc->sc_msgbuf[1], sc->sc_msgbuf[2], 1296 sc->sc_msgbuf[3], sc->sc_msgbuf[4], sc->sc_msgbuf[5])); 1297 1298 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, 1299 sc->sc_msgbuf, sc->sc_msgcnt); 1300 sc->sc_msgcnt = 0; 1301 memset(sc->sc_msgbuf, 0, sizeof(sc->sc_msgbuf)); 1302 1303 /* it's important for atn stop */ 1304 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1305 1306 /* 1307 * SCSI command 1308 */ 1309 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_OUT); 1310} 1311 1312static void 1313trm_command_phase1(struct trm_softc *sc) 1314{ 1315 bus_space_tag_t iot = sc->sc_iot; 1316 bus_space_handle_t ioh = sc->sc_ioh; 1317 struct trm_srb *srb; 1318 1319 srb = sc->sc_actsrb; 1320 if (srb == NULL) { 1321 DPRINTF(("trm_command_phase1: no active srb\n")); 1322 return; 1323 } 1324 1325 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRATN | DO_CLRFIFO); 1326 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, srb->cmd, srb->cmdlen); 1327 1328 sc->sc_state = TRM_COMMAND; 1329 /* it's important for atn stop */ 1330 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1331 1332 /* 1333 * SCSI command 1334 */ 1335 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_OUT); 1336} 1337 1338static void 1339trm_dataout_phase0(struct trm_softc *sc, int stat) 1340{ 1341 bus_space_tag_t iot = sc->sc_iot; 1342 bus_space_handle_t ioh = sc->sc_ioh; 1343 struct trm_srb *srb; 1344 struct scsipi_periph *periph; 1345 struct trm_tinfo *ti; 1346 struct trm_sg_entry *sg; 1347 int sgindex; 1348 uint32_t xferlen, leftcnt = 0; 1349 1350 if (sc->sc_state == TRM_XFERPAD) 1351 return; 1352 1353 srb = sc->sc_actsrb; 1354 if (srb == NULL) { 1355 DPRINTF(("trm_dataout_phase0: no active srb\n")); 1356 return; 1357 } 1358 periph = srb->xs->xs_periph; 1359 ti = &sc->sc_tinfo[periph->periph_target]; 1360 1361 if ((stat & PARITYERROR) != 0) 1362 srb->flag |= PARITY_ERROR; 1363 1364 if ((stat & SCSIXFERDONE) == 0) { 1365 /* 1366 * when data transfer from DMA FIFO to SCSI FIFO 1367 * if there was some data left in SCSI FIFO 1368 */ 1369 leftcnt = bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) & 1370 SCSI_FIFOCNT_MASK; 1371 if (ti->synctl & WIDE_SYNC) 1372 /* 1373 * if WIDE scsi SCSI FIFOCNT unit is word 1374 * so need to * 2 1375 */ 1376 leftcnt <<= 1; 1377 } 1378 /* 1379 * calculate all the residue data that was not yet transferred 1380 * SCSI transfer counter + left in SCSI FIFO data 1381 * 1382 * .....TRM_SCSI_XCNT (24bits) 1383 * The counter always decrements by one for every SCSI 1384 * byte transfer. 1385 * .....TRM_SCSI_FIFOCNT ( 5bits) 1386 * The counter is SCSI FIFO offset counter 1387 */ 1388 leftcnt += bus_space_read_4(iot, ioh, TRM_SCSI_XCNT); 1389 if (leftcnt == 1) { 1390 leftcnt = 0; 1391 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1392 } 1393 if ((leftcnt == 0) || (stat & SCSIXFERCNT_2_ZERO)) { 1394 while ((bus_space_read_1(iot, ioh, TRM_DMA_STATUS) & 1395 DMAXFERCOMP) == 0) 1396 ; /* XXX needs timeout */ 1397 1398 srb->buflen = 0; 1399 } else { 1400 /* Update SG list */ 1401 1402 /* 1403 * if transfer not yet complete 1404 * there were some data residue in SCSI FIFO or 1405 * SCSI transfer counter not empty 1406 */ 1407 if (srb->buflen != leftcnt) { 1408 /* data that had transferred length */ 1409 xferlen = srb->buflen - leftcnt; 1410 1411 /* next time to be transferred length */ 1412 srb->buflen = leftcnt; 1413 1414 /* 1415 * parsing from last time disconnect sgindex 1416 */ 1417 sg = srb->sgentry + srb->sgindex; 1418 for (sgindex = srb->sgindex; 1419 sgindex < srb->sgcnt; 1420 sgindex++, sg++) { 1421 /* 1422 * find last time which SG transfer 1423 * be disconnect 1424 */ 1425 if (xferlen >= le32toh(sg->length)) 1426 xferlen -= le32toh(sg->length); 1427 else { 1428 /* 1429 * update last time 1430 * disconnected SG list 1431 */ 1432 /* residue data length */ 1433 sg->length = 1434 htole32(le32toh(sg->length) 1435 - xferlen); 1436 /* residue data pointer */ 1437 sg->address = 1438 htole32(le32toh(sg->address) 1439 + xferlen); 1440 srb->sgindex = sgindex; 1441 break; 1442 } 1443 } 1444 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1445 srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 1446 } 1447 } 1448 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, STOPDMAXFER); 1449} 1450 1451static void 1452trm_datain_phase0(struct trm_softc *sc, int stat) 1453{ 1454 bus_space_tag_t iot = sc->sc_iot; 1455 bus_space_handle_t ioh = sc->sc_ioh; 1456 struct trm_srb *srb; 1457 struct trm_sg_entry *sg; 1458 int sgindex; 1459 uint32_t xferlen, leftcnt = 0; 1460 1461 if (sc->sc_state == TRM_XFERPAD) 1462 return; 1463 1464 srb = sc->sc_actsrb; 1465 if (srb == NULL) { 1466 DPRINTF(("trm_datain_phase0: no active srb\n")); 1467 return; 1468 } 1469 1470 if (stat & PARITYERROR) 1471 srb->flag |= PARITY_ERROR; 1472 1473 leftcnt += bus_space_read_4(iot, ioh, TRM_SCSI_XCNT); 1474 if ((leftcnt == 0) || (stat & SCSIXFERCNT_2_ZERO)) { 1475 while ((bus_space_read_1(iot, ioh, TRM_DMA_STATUS) & 1476 DMAXFERCOMP) == 0) 1477 ; /* XXX needs timeout */ 1478 1479 srb->buflen = 0; 1480 } else { /* phase changed */ 1481 /* 1482 * parsing the case: 1483 * when a transfer not yet complete 1484 * but be disconnected by upper layer 1485 * if transfer not yet complete 1486 * there were some data residue in SCSI FIFO or 1487 * SCSI transfer counter not empty 1488 */ 1489 if (srb->buflen != leftcnt) { 1490 /* 1491 * data that had transferred length 1492 */ 1493 xferlen = srb->buflen - leftcnt; 1494 1495 /* 1496 * next time to be transferred length 1497 */ 1498 srb->buflen = leftcnt; 1499 1500 /* 1501 * parsing from last time disconnect sgindex 1502 */ 1503 sg = srb->sgentry + srb->sgindex; 1504 for (sgindex = srb->sgindex; 1505 sgindex < srb->sgcnt; 1506 sgindex++, sg++) { 1507 /* 1508 * find last time which SG transfer 1509 * be disconnect 1510 */ 1511 if (xferlen >= le32toh(sg->length)) 1512 xferlen -= le32toh(sg->length); 1513 else { 1514 /* 1515 * update last time 1516 * disconnected SG list 1517 */ 1518 /* residue data length */ 1519 sg->length = 1520 htole32(le32toh(sg->length) 1521 - xferlen); 1522 /* residue data pointer */ 1523 sg->address = 1524 htole32(le32toh(sg->address) 1525 + xferlen); 1526 srb->sgindex = sgindex; 1527 break; 1528 } 1529 } 1530 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1531 srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 1532 } 1533 } 1534} 1535 1536static void 1537trm_dataio_xfer(struct trm_softc *sc, int iodir) 1538{ 1539 bus_space_tag_t iot = sc->sc_iot; 1540 bus_space_handle_t ioh = sc->sc_ioh; 1541 struct trm_srb *srb; 1542 struct scsipi_periph *periph; 1543 struct trm_tinfo *ti; 1544 1545 srb = sc->sc_actsrb; 1546 if (srb == NULL) { 1547 DPRINTF(("trm_dataio_xfer: no active srb\n")); 1548 return; 1549 } 1550 periph = srb->xs->xs_periph; 1551 ti = &sc->sc_tinfo[periph->periph_target]; 1552 1553 if (srb->sgindex < srb->sgcnt) { 1554 if (srb->buflen > 0) { 1555 /* 1556 * load what physical address of Scatter/Gather 1557 * list table want to be transfer 1558 */ 1559 sc->sc_state = TRM_DATA_XFER; 1560 bus_space_write_4(iot, ioh, TRM_DMA_XHIGHADDR, 0); 1561 bus_space_write_4(iot, ioh, TRM_DMA_XLOWADDR, 1562 srb->sgaddr + 1563 srb->sgindex * sizeof(struct trm_sg_entry)); 1564 /* 1565 * load how many bytes in the Scatter/Gather list table 1566 */ 1567 bus_space_write_4(iot, ioh, TRM_DMA_XCNT, 1568 (srb->sgcnt - srb->sgindex) 1569 * sizeof(struct trm_sg_entry)); 1570 /* 1571 * load total xfer length (24bits) max value 16Mbyte 1572 */ 1573 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, srb->buflen); 1574 /* Start DMA transfer */ 1575 bus_space_write_1(iot, ioh, TRM_DMA_COMMAND, 1576 iodir | SGXFER); 1577 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, 1578 STARTDMAXFER); 1579 1580 /* Start SCSI transfer */ 1581 /* it's important for atn stop */ 1582 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1583 DO_DATALATCH); 1584 1585 /* 1586 * SCSI command 1587 */ 1588 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, 1589 (iodir == XFERDATAOUT) ? 1590 SCMD_DMA_OUT : SCMD_DMA_IN); 1591 } else { /* xfer pad */ 1592 if (srb->sgcnt) { 1593 srb->hastat = H_OVER_UNDER_RUN; 1594 } 1595 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1596 (ti->synctl & WIDE_SYNC) ? 2 : 1); 1597 1598 if (iodir == XFERDATAOUT) 1599 bus_space_write_2(iot, ioh, TRM_SCSI_FIFO, 0); 1600 else 1601 (void)bus_space_read_2(iot, ioh, TRM_SCSI_FIFO); 1602 1603 sc->sc_state = TRM_XFERPAD; 1604 /* it's important for atn stop */ 1605 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1606 DO_DATALATCH); 1607 1608 /* 1609 * SCSI command 1610 */ 1611 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, 1612 (iodir == XFERDATAOUT) ? 1613 SCMD_FIFO_OUT : SCMD_FIFO_IN); 1614 } 1615 } 1616} 1617 1618static void 1619trm_status_phase0(struct trm_softc *sc) 1620{ 1621 bus_space_tag_t iot = sc->sc_iot; 1622 bus_space_handle_t ioh = sc->sc_ioh; 1623 struct trm_srb *srb; 1624 1625 srb = sc->sc_actsrb; 1626 if (srb == NULL) { 1627 DPRINTF(("trm_status_phase0: no active srb\n")); 1628 return; 1629 } 1630 srb->tastat = bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1631 sc->sc_state = TRM_COMPLETED; 1632 /* it's important for atn stop */ 1633 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1634 1635 /* 1636 * SCSI command 1637 */ 1638 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 1639} 1640 1641static void 1642trm_status_phase1(struct trm_softc *sc) 1643{ 1644 bus_space_tag_t iot = sc->sc_iot; 1645 bus_space_handle_t ioh = sc->sc_ioh; 1646 1647 if (bus_space_read_1(iot, ioh, TRM_DMA_COMMAND) & XFERDATAIN) { 1648 if ((bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) 1649 & SCSI_FIFO_EMPTY) == 0) 1650 bus_space_write_2(iot, ioh, 1651 TRM_SCSI_CONTROL, DO_CLRFIFO); 1652 if ((bus_space_read_1(iot, ioh, TRM_DMA_FIFOSTATUS) 1653 & DMA_FIFO_EMPTY) == 0) 1654 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 1655 } else { 1656 if ((bus_space_read_1(iot, ioh, TRM_DMA_FIFOSTATUS) 1657 & DMA_FIFO_EMPTY) == 0) 1658 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 1659 if ((bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) 1660 & SCSI_FIFO_EMPTY) == 0) 1661 bus_space_write_2(iot, ioh, 1662 TRM_SCSI_CONTROL, DO_CLRFIFO); 1663 } 1664 sc->sc_state = TRM_STATUS; 1665 /* it's important for atn stop */ 1666 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1667 1668 /* 1669 * SCSI command 1670 */ 1671 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_COMP); 1672} 1673 1674static void 1675trm_msgin_phase0(struct trm_softc *sc) 1676{ 1677 bus_space_tag_t iot = sc->sc_iot; 1678 bus_space_handle_t ioh = sc->sc_ioh; 1679 struct trm_srb *srb; 1680 struct scsipi_periph *periph; 1681 struct trm_tinfo *ti; 1682 int index; 1683 uint8_t msgin_code; 1684 1685 msgin_code = bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1686 if (sc->sc_state != TRM_EXTEND_MSGIN) { 1687 DPRINTF(("msgin: code = %02x\n", msgin_code)); 1688 switch (msgin_code) { 1689 case MSG_DISCONNECT: 1690 sc->sc_state = TRM_DISCONNECTED; 1691 break; 1692 1693 case MSG_SAVEDATAPOINTER: 1694 break; 1695 1696 case MSG_EXTENDED: 1697 case MSG_SIMPLE_Q_TAG: 1698 case MSG_HEAD_OF_Q_TAG: 1699 case MSG_ORDERED_Q_TAG: 1700 sc->sc_state = TRM_EXTEND_MSGIN; 1701 /* extended message (01h) */ 1702 sc->sc_msgbuf[0] = msgin_code; 1703 1704 sc->sc_msgcnt = 1; 1705 /* extended message length (n) */ 1706 sc->sc_msg = &sc->sc_msgbuf[1]; 1707 1708 break; 1709 case MSG_MESSAGE_REJECT: 1710 /* Reject message */ 1711 srb = sc->sc_actsrb; 1712 if (srb == NULL) { 1713 DPRINTF(("trm_msgin_phase0: " 1714 " message reject without actsrb\n")); 1715 break; 1716 } 1717 periph = srb->xs->xs_periph; 1718 ti = &sc->sc_tinfo[periph->periph_target]; 1719 1720 if (ti->flag & WIDE_NEGO_ENABLE) { 1721 /* do wide nego reject */ 1722 ti->flag |= WIDE_NEGO_DONE; 1723 ti->flag &= 1724 ~(SYNC_NEGO_DONE | WIDE_NEGO_ENABLE); 1725 if ((ti->flag & SYNC_NEGO_ENABLE) && 1726 (ti->flag & SYNC_NEGO_DONE) == 0) { 1727 /* Set ATN, in case ATN was clear */ 1728 sc->sc_state = TRM_MSGOUT; 1729 bus_space_write_2(iot, ioh, 1730 TRM_SCSI_CONTROL, DO_SETATN); 1731 } else 1732 /* Clear ATN */ 1733 bus_space_write_2(iot, ioh, 1734 TRM_SCSI_CONTROL, DO_CLRATN); 1735 } else if (ti->flag & SYNC_NEGO_ENABLE) { 1736 /* do sync nego reject */ 1737 bus_space_write_2(iot, ioh, 1738 TRM_SCSI_CONTROL, DO_CLRATN); 1739 if (ti->flag & SYNC_NEGO_DOING) { 1740 ti->flag &=~(SYNC_NEGO_ENABLE | 1741 SYNC_NEGO_DONE); 1742 ti->synctl = 0; 1743 ti->offset = 0; 1744 bus_space_write_1(iot, ioh, 1745 TRM_SCSI_SYNC, ti->synctl); 1746 bus_space_write_1(iot, ioh, 1747 TRM_SCSI_OFFSET, ti->offset); 1748 } 1749 } 1750 break; 1751 1752 case MSG_IGN_WIDE_RESIDUE: 1753 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1); 1754 (void)bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1755 break; 1756 1757 default: 1758 /* 1759 * Restore data pointer message 1760 * Save data pointer message 1761 * Completion message 1762 * NOP message 1763 */ 1764 break; 1765 } 1766 } else { 1767 /* 1768 * when extend message in: sc->sc_state = TRM_EXTEND_MSGIN 1769 * Parsing incoming extented messages 1770 */ 1771 *sc->sc_msg++ = msgin_code; 1772 sc->sc_msgcnt++; 1773 1774 DPRINTF(("extended_msgin: cnt = %d, ", sc->sc_msgcnt)); 1775 DPRINTF(("msgbuf = %02x %02x %02x %02x %02x %02x\n", 1776 sc->sc_msgbuf[0], sc->sc_msgbuf[1], sc->sc_msgbuf[2], 1777 sc->sc_msgbuf[3], sc->sc_msgbuf[4], sc->sc_msgbuf[5])); 1778 1779 switch (sc->sc_msgbuf[0]) { 1780 case MSG_SIMPLE_Q_TAG: 1781 case MSG_HEAD_OF_Q_TAG: 1782 case MSG_ORDERED_Q_TAG: 1783 /* 1784 * is QUEUE tag message : 1785 * 1786 * byte 0: 1787 * HEAD QUEUE TAG (20h) 1788 * ORDERED QUEUE TAG (21h) 1789 * SIMPLE QUEUE TAG (22h) 1790 * byte 1: 1791 * Queue tag (00h - FFh) 1792 */ 1793 if (sc->sc_msgcnt == 2 && sc->sc_actsrb == NULL) { 1794 /* XXX XXX XXX */ 1795 struct trm_linfo *li; 1796 int tagid; 1797 1798 sc->sc_flag &= ~WAIT_TAGMSG; 1799 tagid = sc->sc_msgbuf[1]; 1800 ti = &sc->sc_tinfo[sc->resel_target]; 1801 li = ti->linfo[sc->resel_lun]; 1802 srb = li->queued[tagid]; 1803 if (srb != NULL) { 1804 sc->sc_actsrb = srb; 1805 sc->sc_state = TRM_DATA_XFER; 1806 break; 1807 } else { 1808 printf("%s: invalid tag id\n", 1809 device_xname(sc->sc_dev)); 1810 } 1811 1812 sc->sc_state = TRM_UNEXPECT_RESEL; 1813 sc->sc_msgbuf[0] = MSG_ABORT_TAG; 1814 sc->sc_msgcnt = 1; 1815 bus_space_write_2(iot, ioh, 1816 TRM_SCSI_CONTROL, DO_SETATN); 1817 } else 1818 sc->sc_state = TRM_IDLE; 1819 break; 1820 1821 case MSG_EXTENDED: 1822 srb = sc->sc_actsrb; 1823 if (srb == NULL) { 1824 DPRINTF(("trm_msgin_phase0: " 1825 "extended message without actsrb\n")); 1826 break; 1827 } 1828 periph = srb->xs->xs_periph; 1829 ti = &sc->sc_tinfo[periph->periph_target]; 1830 1831 if (sc->sc_msgbuf[2] == MSG_EXT_WDTR && 1832 sc->sc_msgcnt == 4) { 1833 /* 1834 * is Wide data xfer Extended message : 1835 * ====================================== 1836 * WIDE DATA TRANSFER REQUEST 1837 * ====================================== 1838 * byte 0 : Extended message (01h) 1839 * byte 1 : Extended message length (02h) 1840 * byte 2 : WIDE DATA TRANSFER code (03h) 1841 * byte 3 : Transfer width exponent 1842 */ 1843 if (sc->sc_msgbuf[1] != MSG_EXT_WDTR_LEN) { 1844 /* Length is wrong, reject it */ 1845 ti->flag &= ~(WIDE_NEGO_ENABLE | 1846 WIDE_NEGO_DONE); 1847 sc->sc_state = TRM_MSGOUT; 1848 sc->sc_msgbuf[0] = MSG_MESSAGE_REJECT; 1849 sc->sc_msgcnt = 1; 1850 bus_space_write_2(iot, ioh, 1851 TRM_SCSI_CONTROL, DO_SETATN); 1852 break; 1853 } 1854 1855 if ((ti->flag & WIDE_NEGO_ENABLE) == 0) 1856 sc->sc_msgbuf[3] = 1857 MSG_EXT_WDTR_BUS_8_BIT; 1858 1859 if (sc->sc_msgbuf[3] > 1860 MSG_EXT_WDTR_BUS_32_BIT) { 1861 /* reject_msg: */ 1862 ti->flag &= ~(WIDE_NEGO_ENABLE | 1863 WIDE_NEGO_DONE); 1864 sc->sc_state = TRM_MSGOUT; 1865 sc->sc_msgbuf[0] = MSG_MESSAGE_REJECT; 1866 sc->sc_msgcnt = 1; 1867 bus_space_write_2(iot, ioh, 1868 TRM_SCSI_CONTROL, DO_SETATN); 1869 break; 1870 } 1871 if (sc->sc_msgbuf[3] == MSG_EXT_WDTR_BUS_32_BIT) 1872 /* do 16 bits */ 1873 sc->sc_msgbuf[3] = 1874 MSG_EXT_WDTR_BUS_16_BIT; 1875 if ((ti->flag & WIDE_NEGO_DONE) == 0) { 1876 ti->flag |= WIDE_NEGO_DONE; 1877 ti->flag &= ~(SYNC_NEGO_DONE | 1878 WIDE_NEGO_ENABLE); 1879 if (sc->sc_msgbuf[3] != 1880 MSG_EXT_WDTR_BUS_8_BIT) 1881 /* is Wide data xfer */ 1882 ti->synctl |= WIDE_SYNC; 1883 trm_update_xfer_mode(sc, 1884 periph->periph_target); 1885 } 1886 1887 sc->sc_state = TRM_MSGOUT; 1888 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1889 DO_SETATN); 1890 break; 1891 1892 } else if (sc->sc_msgbuf[2] == MSG_EXT_SDTR && 1893 sc->sc_msgcnt == 5) { 1894 /* 1895 * is 8bit transfer Extended message : 1896 * ================================= 1897 * SYNCHRONOUS DATA TRANSFER REQUEST 1898 * ================================= 1899 * byte 0 : Extended message (01h) 1900 * byte 1 : Extended message length (03) 1901 * byte 2 : SYNC DATA TRANSFER code (01h) 1902 * byte 3 : Transfer period factor 1903 * byte 4 : REQ/ACK offset 1904 */ 1905 if (sc->sc_msgbuf[1] != MSG_EXT_SDTR_LEN) { 1906 /* reject_msg */ 1907 sc->sc_state = TRM_MSGOUT; 1908 sc->sc_msgbuf[0] = MSG_MESSAGE_REJECT; 1909 sc->sc_msgcnt = 1; 1910 bus_space_write_2(iot, ioh, 1911 TRM_SCSI_CONTROL, DO_SETATN); 1912 break; 1913 } 1914 1915 if ((ti->flag & SYNC_NEGO_DONE) == 0) { 1916 ti->flag &= 1917 ~(SYNC_NEGO_ENABLE|SYNC_NEGO_DOING); 1918 ti->flag |= SYNC_NEGO_DONE; 1919 if (sc->sc_msgbuf[3] >= TRM_MAX_PERIOD) 1920 sc->sc_msgbuf[3] = 0; 1921 if (sc->sc_msgbuf[4] > TRM_MAX_OFFSET) 1922 sc->sc_msgbuf[4] = 1923 TRM_MAX_OFFSET; 1924 1925 if (sc->sc_msgbuf[3] == 0 || 1926 sc->sc_msgbuf[4] == 0) { 1927 /* set async */ 1928 ti->synctl = 0; 1929 ti->offset = 0; 1930 } else { 1931 /* set sync */ 1932 /* Transfer period factor */ 1933 ti->period = sc->sc_msgbuf[3]; 1934 /* REQ/ACK offset */ 1935 ti->offset = sc->sc_msgbuf[4]; 1936 for (index = 0; 1937 index < NPERIOD; 1938 index++) 1939 if (ti->period <= 1940 trm_clock_period[ 1941 index]) 1942 break; 1943 1944 ti->synctl |= ALT_SYNC | index; 1945 } 1946 /* 1947 * program SCSI control register 1948 */ 1949 bus_space_write_1(iot, ioh, 1950 TRM_SCSI_SYNC, ti->synctl); 1951 bus_space_write_1(iot, ioh, 1952 TRM_SCSI_OFFSET, ti->offset); 1953 trm_update_xfer_mode(sc, 1954 periph->periph_target); 1955 } 1956 sc->sc_state = TRM_IDLE; 1957 } 1958 break; 1959 default: 1960 break; 1961 } 1962 } 1963 1964 /* it's important for atn stop */ 1965 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1966 1967 /* 1968 * SCSI command 1969 */ 1970 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 1971} 1972 1973static void 1974trm_msgin_phase1(struct trm_softc *sc) 1975{ 1976 bus_space_tag_t iot = sc->sc_iot; 1977 bus_space_handle_t ioh = sc->sc_ioh; 1978 1979 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1980 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1); 1981 if (sc->sc_state != TRM_MSGIN && sc->sc_state != TRM_EXTEND_MSGIN) { 1982 sc->sc_state = TRM_MSGIN; 1983 } 1984 1985 /* it's important for atn stop */ 1986 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1987 1988 /* 1989 * SCSI command 1990 */ 1991 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_IN); 1992} 1993 1994static void 1995trm_disconnect(struct trm_softc *sc) 1996{ 1997 bus_space_tag_t iot = sc->sc_iot; 1998 bus_space_handle_t ioh = sc->sc_ioh; 1999 struct trm_srb *srb; 2000 int s; 2001 2002 s = splbio(); 2003 2004 srb = sc->sc_actsrb; 2005 DPRINTF(("trm_disconnect...............\n")); 2006 2007 if (srb == NULL) { 2008 DPRINTF(("trm_disconnect: no active srb\n")); 2009 DELAY(1000); /* 1 msec */ 2010 2011 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 2012 DO_CLRFIFO | DO_HWRESELECT); 2013 return; 2014 } 2015 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 2016 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 2017 DO_CLRFIFO | DO_HWRESELECT); 2018 DELAY(100); 2019 2020 switch (sc->sc_state) { 2021 case TRM_UNEXPECT_RESEL: 2022 sc->sc_state = TRM_IDLE; 2023 break; 2024 2025 case TRM_ABORT_SENT: 2026 goto finish; 2027 2028 case TRM_START: 2029 case TRM_MSGOUT: 2030 { 2031 /* Selection time out - discard all LUNs if empty */ 2032 struct scsipi_periph *periph; 2033 struct trm_tinfo *ti; 2034 struct trm_linfo *li; 2035 int lun; 2036 2037 DPRINTF(("selection timeout\n")); 2038 2039 srb->tastat = SCSI_SEL_TIMEOUT; /* XXX Ok? */ 2040 2041 periph = srb->xs->xs_periph; 2042 ti = &sc->sc_tinfo[periph->periph_target]; 2043 for (lun = 0; lun < TRM_MAX_LUNS; lun++) { 2044 li = ti->linfo[lun]; 2045 if (li != NULL && 2046 li->untagged == NULL && li->used == 0) { 2047 ti->linfo[lun] = NULL; 2048 free(li, M_DEVBUF); 2049 } 2050 } 2051 } 2052 goto finish; 2053 2054 case TRM_DISCONNECTED: 2055 sc->sc_actsrb = NULL; 2056 sc->sc_state = TRM_IDLE; 2057 goto sched; 2058 2059 case TRM_COMPLETED: 2060 goto finish; 2061 } 2062 2063 out: 2064 splx(s); 2065 return; 2066 2067 finish: 2068 sc->sc_state = TRM_IDLE; 2069 trm_done(sc, srb); 2070 goto out; 2071 2072 sched: 2073 trm_sched(sc); 2074 goto out; 2075} 2076 2077static void 2078trm_reselect(struct trm_softc *sc) 2079{ 2080 bus_space_tag_t iot = sc->sc_iot; 2081 bus_space_handle_t ioh = sc->sc_ioh; 2082 struct trm_tinfo *ti; 2083 struct trm_linfo *li; 2084 int target, lun; 2085 2086 DPRINTF(("trm_reselect.................\n")); 2087 2088 if (sc->sc_actsrb != NULL) { 2089 /* arbitration lost but reselection win */ 2090 sc->sc_state = TRM_READY; 2091 target = sc->sc_actsrb->xs->xs_periph->periph_target; 2092 ti = &sc->sc_tinfo[target]; 2093 } else { 2094 /* Read Reselected Target Id and LUN */ 2095 target = bus_space_read_1(iot, ioh, TRM_SCSI_TARGETID); 2096 lun = bus_space_read_1(iot, ioh, TRM_SCSI_IDMSG) & 0x07; 2097 ti = &sc->sc_tinfo[target]; 2098 li = ti->linfo[lun]; 2099 DPRINTF(("target = %d, lun = %d\n", target, lun)); 2100 2101 /* 2102 * Check to see if we are running an un-tagged command. 2103 * Otherwise ack the IDENTIFY and wait for a tag message. 2104 */ 2105 if (li != NULL) { 2106 if (li->untagged != NULL && li->busy) { 2107 sc->sc_actsrb = li->untagged; 2108 sc->sc_state = TRM_DATA_XFER; 2109 } else { 2110 sc->resel_target = target; 2111 sc->resel_lun = lun; 2112 /* XXX XXX XXX */ 2113 sc->sc_flag |= WAIT_TAGMSG; 2114 } 2115 } 2116 2117 if ((ti->flag & USE_TAG_QUEUING) == 0 && 2118 sc->sc_actsrb == NULL) { 2119 printf("%s: reselect from target %d lun %d " 2120 "without nexus; sending abort\n", 2121 device_xname(sc->sc_dev), target, lun); 2122 sc->sc_state = TRM_UNEXPECT_RESEL; 2123 sc->sc_msgbuf[0] = MSG_ABORT_TAG; 2124 sc->sc_msgcnt = 1; 2125 bus_space_write_2(iot, ioh, 2126 TRM_SCSI_CONTROL, DO_SETATN); 2127 } 2128 } 2129 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 2130 /* 2131 * Program HA ID, target ID, period and offset 2132 */ 2133 /* target ID */ 2134 bus_space_write_1(iot, ioh, TRM_SCSI_TARGETID, target); 2135 2136 /* host ID */ 2137 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 2138 2139 /* period */ 2140 bus_space_write_1(iot, ioh, TRM_SCSI_SYNC, ti->synctl); 2141 2142 /* offset */ 2143 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, ti->offset); 2144 2145 /* it's important for atn stop */ 2146 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 2147 /* 2148 * SCSI command 2149 */ 2150 /* to rls the /ACK signal */ 2151 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 2152} 2153 2154/* 2155 * Complete execution of a SCSI command 2156 * Signal completion to the generic SCSI driver 2157 */ 2158static void 2159trm_done(struct trm_softc *sc, struct trm_srb *srb) 2160{ 2161 struct scsipi_xfer *xs = srb->xs; 2162 2163 DPRINTF(("trm_done..................\n")); 2164 2165 if (xs == NULL) 2166 return; 2167 2168 if ((xs->xs_control & XS_CTL_POLL) == 0) 2169 callout_stop(&xs->xs_callout); 2170 2171 if (xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT) || 2172 srb->flag & AUTO_REQSENSE) { 2173 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 2174 srb->dmap->dm_mapsize, 2175 ((xs->xs_control & XS_CTL_DATA_IN) || 2176 (srb->flag & AUTO_REQSENSE)) ? 2177 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2178 bus_dmamap_unload(sc->sc_dmat, srb->dmap); 2179 } 2180 2181 /* 2182 * target status 2183 */ 2184 xs->status = srb->tastat; 2185 2186 DPRINTF(("xs->status = 0x%02x\n", xs->status)); 2187 2188 switch (xs->status) { 2189 case SCSI_OK: 2190 /* 2191 * process initiator status...... 2192 * Adapter (initiator) status 2193 */ 2194 if ((srb->hastat & H_OVER_UNDER_RUN) != 0) { 2195 printf("%s: over/under run error\n", 2196 device_xname(sc->sc_dev)); 2197 srb->tastat = 0; 2198 /* Illegal length (over/under run) */ 2199 xs->error = XS_DRIVER_STUFFUP; 2200 } else if ((srb->flag & PARITY_ERROR) != 0) { 2201 printf("%s: parity error\n", device_xname(sc->sc_dev)); 2202 /* Driver failed to perform operation */ 2203 xs->error = XS_DRIVER_STUFFUP; /* XXX */ 2204 } else if ((srb->flag & SRB_TIMEOUT) != 0) { 2205 xs->resid = srb->buflen; 2206 xs->error = XS_TIMEOUT; 2207 } else { 2208 /* No error */ 2209 xs->resid = srb->buflen; 2210 srb->hastat = 0; 2211 if (srb->flag & AUTO_REQSENSE) { 2212 /* there is no error, (sense is invalid) */ 2213 xs->error = XS_SENSE; 2214 } else { 2215 srb->tastat = 0; 2216 xs->error = XS_NOERROR; 2217 } 2218 } 2219 break; 2220 2221 case SCSI_CHECK: 2222 if ((srb->flag & AUTO_REQSENSE) != 0 || 2223 trm_request_sense(sc, srb) != 0) { 2224 printf("%s: request sense failed\n", 2225 device_xname(sc->sc_dev)); 2226 xs->error = XS_DRIVER_STUFFUP; 2227 break; 2228 } 2229 xs->error = XS_SENSE; 2230 return; 2231 2232 case SCSI_SEL_TIMEOUT: 2233 srb->hastat = H_SEL_TIMEOUT; 2234 srb->tastat = 0; 2235 xs->error = XS_SELTIMEOUT; 2236 break; 2237 2238 case SCSI_QUEUE_FULL: 2239 case SCSI_BUSY: 2240 xs->error = XS_BUSY; 2241 break; 2242 2243 case SCSI_RESV_CONFLICT: 2244 DPRINTF(("%s: target reserved at ", device_xname(sc->sc_dev))); 2245 DPRINTF(("%s %d\n", __FILE__, __LINE__)); 2246 xs->error = XS_BUSY; 2247 break; 2248 2249 default: 2250 srb->hastat = 0; 2251 printf("%s: trm_done(): unknown status = %02x\n", 2252 device_xname(sc->sc_dev), xs->status); 2253 xs->error = XS_DRIVER_STUFFUP; 2254 break; 2255 } 2256 2257 trm_dequeue(sc, srb); 2258 if (srb == sc->sc_actsrb) { 2259 sc->sc_actsrb = NULL; 2260 trm_sched(sc); 2261 } 2262 2263 TAILQ_INSERT_TAIL(&sc->sc_freesrb, srb, next); 2264 2265 /* Notify cmd done */ 2266 scsipi_done(xs); 2267} 2268 2269static int 2270trm_request_sense(struct trm_softc *sc, struct trm_srb *srb) 2271{ 2272 struct scsipi_xfer *xs; 2273 struct scsipi_periph *periph; 2274 struct trm_tinfo *ti; 2275 struct trm_linfo *li; 2276 struct scsi_request_sense *ss = (struct scsi_request_sense *)srb->cmd; 2277 int error; 2278 2279 DPRINTF(("trm_request_sense...\n")); 2280 2281 xs = srb->xs; 2282 periph = xs->xs_periph; 2283 2284 srb->flag |= AUTO_REQSENSE; 2285 2286 /* Status of initiator/target */ 2287 srb->hastat = 0; 2288 srb->tastat = 0; 2289 2290 memset(ss, 0, sizeof(*ss)); 2291 ss->opcode = SCSI_REQUEST_SENSE; 2292 ss->byte2 = periph->periph_lun << SCSI_CMD_LUN_SHIFT; 2293 ss->length = sizeof(struct scsi_sense_data); 2294 2295 srb->buflen = sizeof(struct scsi_sense_data); 2296 srb->sgcnt = 1; 2297 srb->sgindex = 0; 2298 srb->cmdlen = sizeof(struct scsi_request_sense); 2299 2300 if ((error = bus_dmamap_load(sc->sc_dmat, srb->dmap, 2301 &xs->sense.scsi_sense, srb->buflen, NULL, 2302 BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 2303 return error; 2304 } 2305 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 2306 srb->buflen, BUS_DMASYNC_PREREAD); 2307 2308 srb->sgentry[0].address = htole32(srb->dmap->dm_segs[0].ds_addr); 2309 srb->sgentry[0].length = htole32(sizeof(struct scsi_sense_data)); 2310 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, srb->sgoffset, 2311 TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 2312 2313 ti = &sc->sc_tinfo[periph->periph_target]; 2314 li = ti->linfo[periph->periph_lun]; 2315 if (li->busy > 0) 2316 li->busy = 0; 2317 trm_dequeue(sc, srb); 2318 li->untagged = srb; /* must be executed first to fix C/A */ 2319 li->busy = 2; 2320 2321 if (srb == sc->sc_actsrb) 2322 trm_select(sc, srb); 2323 else { 2324 TAILQ_INSERT_HEAD(&sc->sc_readysrb, srb, next); 2325 if (sc->sc_actsrb == NULL) 2326 trm_sched(sc); 2327 } 2328 return 0; 2329} 2330 2331static void 2332trm_dequeue(struct trm_softc *sc, struct trm_srb *srb) 2333{ 2334 struct scsipi_periph *periph; 2335 struct trm_tinfo *ti; 2336 struct trm_linfo *li; 2337 2338 periph = srb->xs->xs_periph; 2339 ti = &sc->sc_tinfo[periph->periph_target]; 2340 li = ti->linfo[periph->periph_lun]; 2341 2342 if (li->untagged == srb) { 2343 li->busy = 0; 2344 li->untagged = NULL; 2345 } 2346 if (srb->tag[0] != 0 && li->queued[srb->tag[1]] != NULL) { 2347 li->queued[srb->tag[1]] = NULL; 2348 li->used--; 2349 } 2350} 2351 2352static void 2353trm_reset_scsi_bus(struct trm_softc *sc) 2354{ 2355 bus_space_tag_t iot = sc->sc_iot; 2356 bus_space_handle_t ioh = sc->sc_ioh; 2357 int timeout, s; 2358 2359 DPRINTF(("trm_reset_scsi_bus.........\n")); 2360 2361 s = splbio(); 2362 2363 sc->sc_flag |= RESET_DEV; 2364 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_RSTSCSI); 2365 for (timeout = 20000; timeout >= 0; timeout--) { 2366 DELAY(1); 2367 if ((bus_space_read_2(iot, ioh, TRM_SCSI_INTSTATUS) & 2368 INT_SCSIRESET) == 0) 2369 break; 2370 } 2371 if (timeout == 0) 2372 printf(": scsibus reset timeout\n"); 2373 2374 splx(s); 2375} 2376 2377static void 2378trm_scsi_reset_detect(struct trm_softc *sc) 2379{ 2380 bus_space_tag_t iot = sc->sc_iot; 2381 bus_space_handle_t ioh = sc->sc_ioh; 2382 int s; 2383 2384 DPRINTF(("trm_scsi_reset_detect...............\n")); 2385 DELAY(1000000); /* delay 1 sec */ 2386 2387 s = splbio(); 2388 2389 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, STOPDMAXFER); 2390 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 2391 2392 if (sc->sc_flag & RESET_DEV) { 2393 sc->sc_flag |= RESET_DONE; 2394 } else { 2395 sc->sc_flag |= RESET_DETECT; 2396 sc->sc_actsrb = NULL; 2397 sc->sc_flag = 0; 2398 trm_sched(sc); 2399 } 2400 splx(s); 2401} 2402 2403/* 2404 * read seeprom 128 bytes to struct eeprom and check checksum. 2405 * If it is wrong, update with default value. 2406 */ 2407static void 2408trm_check_eeprom(struct trm_softc *sc, struct trm_nvram *eeprom) 2409{ 2410 struct nvram_target *target; 2411 uint16_t *ep; 2412 uint16_t chksum; 2413 int i; 2414 2415 DPRINTF(("trm_check_eeprom......\n")); 2416 trm_eeprom_read_all(sc, eeprom); 2417 ep = (uint16_t *)eeprom; 2418 chksum = 0; 2419 for (i = 0; i < 64; i++) 2420 chksum += le16toh(*ep++); 2421 2422 if (chksum != TRM_NVRAM_CKSUM) { 2423 DPRINTF(("TRM_S1040 EEPROM Check Sum ERROR (load default).\n")); 2424 /* 2425 * Checksum error, load default 2426 */ 2427 eeprom->subvendor_id[0] = PCI_VENDOR_TEKRAM2 & 0xFF; 2428 eeprom->subvendor_id[1] = PCI_VENDOR_TEKRAM2 >> 8; 2429 eeprom->subsys_id[0] = PCI_PRODUCT_TEKRAM2_DC315 & 0xFF; 2430 eeprom->subsys_id[1] = PCI_PRODUCT_TEKRAM2_DC315 >> 8; 2431 eeprom->subclass = 0x00; 2432 eeprom->vendor_id[0] = PCI_VENDOR_TEKRAM2 & 0xFF; 2433 eeprom->vendor_id[1] = PCI_VENDOR_TEKRAM2 >> 8; 2434 eeprom->device_id[0] = PCI_PRODUCT_TEKRAM2_DC315 & 0xFF; 2435 eeprom->device_id[1] = PCI_PRODUCT_TEKRAM2_DC315 >> 8; 2436 eeprom->reserved0 = 0x00; 2437 2438 for (i = 0, target = eeprom->target; 2439 i < TRM_MAX_TARGETS; 2440 i++, target++) { 2441 target->config0 = 0x77; 2442 target->period = 0x00; 2443 target->config2 = 0x00; 2444 target->config3 = 0x00; 2445 } 2446 2447 eeprom->scsi_id = 7; 2448 eeprom->channel_cfg = 0x0F; 2449 eeprom->delay_time = 0; 2450 eeprom->max_tag = 4; 2451 eeprom->reserved1 = 0x15; 2452 eeprom->boot_target = 0; 2453 eeprom->boot_lun = 0; 2454 eeprom->reserved2 = 0; 2455 memset(eeprom->reserved3, 0, sizeof(eeprom->reserved3)); 2456 2457 chksum = 0; 2458 ep = (uint16_t *)eeprom; 2459 for (i = 0; i < 63; i++) 2460 chksum += le16toh(*ep++); 2461 2462 chksum = TRM_NVRAM_CKSUM - chksum; 2463 eeprom->checksum0 = chksum & 0xFF; 2464 eeprom->checksum1 = chksum >> 8; 2465 2466 trm_eeprom_write_all(sc, eeprom); 2467 } 2468} 2469 2470/* 2471 * write struct eeprom 128 bytes to seeprom 2472 */ 2473static void 2474trm_eeprom_write_all(struct trm_softc *sc, struct trm_nvram *eeprom) 2475{ 2476 bus_space_tag_t iot = sc->sc_iot; 2477 bus_space_handle_t ioh = sc->sc_ioh; 2478 uint8_t *sbuf = (uint8_t *)eeprom; 2479 uint8_t addr; 2480 2481 /* Enable SEEPROM */ 2482 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2483 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) | EN_EEPROM); 2484 2485 /* 2486 * Write enable 2487 */ 2488 trm_eeprom_write_cmd(sc, 0x04, 0xFF); 2489 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2490 trm_eeprom_wait(); 2491 2492 for (addr = 0; addr < 128; addr++, sbuf++) 2493 trm_eeprom_set_data(sc, addr, *sbuf); 2494 2495 /* 2496 * Write disable 2497 */ 2498 trm_eeprom_write_cmd(sc, 0x04, 0x00); 2499 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2500 trm_eeprom_wait(); 2501 2502 /* Disable SEEPROM */ 2503 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2504 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) & ~EN_EEPROM); 2505} 2506 2507/* 2508 * write one byte to seeprom 2509 */ 2510static void 2511trm_eeprom_set_data(struct trm_softc *sc, uint8_t addr, uint8_t data) 2512{ 2513 bus_space_tag_t iot = sc->sc_iot; 2514 bus_space_handle_t ioh = sc->sc_ioh; 2515 int i; 2516 uint8_t send; 2517 2518 /* 2519 * Send write command & address 2520 */ 2521 trm_eeprom_write_cmd(sc, 0x05, addr); 2522 /* 2523 * Write data 2524 */ 2525 for (i = 0; i < 8; i++, data <<= 1) { 2526 send = NVR_SELECT; 2527 if (data & 0x80) /* Start from bit 7 */ 2528 send |= NVR_BITOUT; 2529 2530 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 2531 trm_eeprom_wait(); 2532 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 2533 trm_eeprom_wait(); 2534 } 2535 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2536 trm_eeprom_wait(); 2537 /* 2538 * Disable chip select 2539 */ 2540 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2541 trm_eeprom_wait(); 2542 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2543 trm_eeprom_wait(); 2544 /* 2545 * Wait for write ready 2546 */ 2547 for (;;) { 2548 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 2549 NVR_SELECT | NVR_CLOCK); 2550 trm_eeprom_wait(); 2551 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2552 trm_eeprom_wait(); 2553 if (bus_space_read_1(iot, ioh, TRM_GEN_NVRAM) & NVR_BITIN) 2554 break; 2555 } 2556 /* 2557 * Disable chip select 2558 */ 2559 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2560} 2561 2562/* 2563 * read seeprom 128 bytes to struct eeprom 2564 */ 2565static void 2566trm_eeprom_read_all(struct trm_softc *sc, struct trm_nvram *eeprom) 2567{ 2568 bus_space_tag_t iot = sc->sc_iot; 2569 bus_space_handle_t ioh = sc->sc_ioh; 2570 uint8_t *sbuf = (uint8_t *)eeprom; 2571 uint8_t addr; 2572 2573 /* 2574 * Enable SEEPROM 2575 */ 2576 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2577 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) | EN_EEPROM); 2578 2579 for (addr = 0; addr < 128; addr++) 2580 *sbuf++ = trm_eeprom_get_data(sc, addr); 2581 2582 /* 2583 * Disable SEEPROM 2584 */ 2585 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2586 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) & ~EN_EEPROM); 2587} 2588 2589/* 2590 * read one byte from seeprom 2591 */ 2592static uint8_t 2593trm_eeprom_get_data(struct trm_softc *sc, uint8_t addr) 2594{ 2595 bus_space_tag_t iot = sc->sc_iot; 2596 bus_space_handle_t ioh = sc->sc_ioh; 2597 int i; 2598 uint8_t read, data = 0; 2599 2600 /* 2601 * Send read command & address 2602 */ 2603 trm_eeprom_write_cmd(sc, 0x06, addr); 2604 2605 for (i = 0; i < 8; i++) { /* Read data */ 2606 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 2607 NVR_SELECT | NVR_CLOCK); 2608 trm_eeprom_wait(); 2609 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2610 /* 2611 * Get data bit while falling edge 2612 */ 2613 read = bus_space_read_1(iot, ioh, TRM_GEN_NVRAM); 2614 data <<= 1; 2615 if (read & NVR_BITIN) 2616 data |= 1; 2617 2618 trm_eeprom_wait(); 2619 } 2620 /* 2621 * Disable chip select 2622 */ 2623 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2624 return data; 2625} 2626 2627/* 2628 * write SB and Op Code into seeprom 2629 */ 2630static void 2631trm_eeprom_write_cmd(struct trm_softc *sc, uint8_t cmd, uint8_t addr) 2632{ 2633 bus_space_tag_t iot = sc->sc_iot; 2634 bus_space_handle_t ioh = sc->sc_ioh; 2635 int i; 2636 uint8_t send; 2637 2638 /* Program SB+OP code */ 2639 for (i = 0; i < 3; i++, cmd <<= 1) { 2640 send = NVR_SELECT; 2641 if (cmd & 0x04) /* Start from bit 2 */ 2642 send |= NVR_BITOUT; 2643 2644 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 2645 trm_eeprom_wait(); 2646 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 2647 trm_eeprom_wait(); 2648 } 2649 2650 /* Program address */ 2651 for (i = 0; i < 7; i++, addr <<= 1) { 2652 send = NVR_SELECT; 2653 if (addr & 0x40) /* Start from bit 6 */ 2654 send |= NVR_BITOUT; 2655 2656 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 2657 trm_eeprom_wait(); 2658 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 2659 trm_eeprom_wait(); 2660 } 2661 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2662 trm_eeprom_wait(); 2663} 2664