1/*	$NetBSD: pciide_acer_reg.h,v 1.11 2007/12/25 18:33:41 perry Exp $	*/
2
3/*
4 * Copyright (c) 1999 Manuel Bouyer.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 */
27
28/*  class code attribute register 1 (1 byte) */
29#define ACER_CCAR1	0x43
30#define ACER_CHANSTATUS_RO            0x40
31#define PCIIDE_CHAN_RO(chan)            (0x20 >> (chan))
32
33/* from Linux, 80 pins cable detect */
34#define ACER_0x4A	0x4a
35/*
36 * bit 0 is 0 -> primary has 80 pin cable
37 * bit 1 is 0 -> secondary has 80 pin cable
38 */
39#define ACER_0x4A_80PIN(chan)	(0x1 << (chan))
40
41/* From FreeBSD, for UDMA mode > 2 */
42#define ACER_0x4B	0x4b
43#define ACER_0x4B_UDMA66	0x01
44/* From Linux */
45#define ACER_0x4B_CDETECT	0x08
46
47/* class code attribute register 2 (1 byte) */
48#define ACER_CCAR2	0x4d
49#define ACER_CHANSTATUSREGS_RO 0x80
50
51/* class code attribute register 3 (1 byte) */
52#define ACER_CCAR3	0x50
53#define ACER_CCAR3_PI	0x02
54
55/* flexible channel setting register */
56#define ACER_FCS	0x52
57#define ACER_FCS_TIMREG(chan,drv)	((0x8) >> ((drv) + (chan) * 2))
58
59/* CD-ROM control register */
60#define ACER_CDRC	0x53
61#define ACER_CDRC_FIFO_DISABLE	0x02
62#define ACER_CDRC_DMA_EN	0x01
63
64/* Fifo threshold and Ultra-DMA settings (4 bytes). */
65#define ACER_FTH_UDMA	0x54
66#define ACER_FTH_VAL(chan, drv, val) \
67	(((val) & 0x3) << ((drv) * 4 + (chan) * 8))
68#define ACER_FTH_OPL(chan, drv, val) \
69	(((val) & 0x3) << (2 + (drv) * 4 + (chan) * 8))
70#define ACER_UDMA_EN(chan, drv) \
71	(0x8 << (16 + (drv) * 4 + (chan) * 8))
72#define ACER_UDMA_TIM(chan, drv, val) \
73	(((val) & 0x7) << (16 + (drv) * 4 + (chan) * 8))
74
75/* drives timings setup (1 byte) */
76#define ACER_IDETIM(chan, drv) (0x5a + (drv) + (chan) * 4)
77
78/* IRQ and drive select status */
79#define ACER_CHIDS	0x75
80#define ACER_CHIDS_DRV(channel)	((0x4) << (channel))
81#define ACER_CHIDS_INT(channel)	((0x1) << (channel))
82
83/* Linux: south-bridge's enable bit (m1533) */
84#define ACER_0x79	0x79
85#define ACER_0x79_REVC2_EN	0x4
86#define ACER_0x79_EN		0x2
87
88/* OpenSolaris: channel enable/disable in the PCI-ISA bridge */
89#define ACER_PCIB_CTRL	0x58
90#define ACER_PCIB_CTRL_ENCHAN(chan) (0x4 << (chan))
91
92/*
93 * IDE bus frequency (1 byte)
94 * This should be setup by the BIOS - can we rely on this ?
95 */
96#define ACER_IDE_CLK	0x78
97
98/* acer UDMA3/4/5 from FreeBSD */
99static const int8_t acer_udma[] __unused =
100    {0x4, 0x3, 0x2, 0x1, 0x0, 0x7};
101static const int8_t acer_pio[] __unused =
102    {0x0c, 0x58, 0x44, 0x33, 0x31};
103#ifdef unused
104static const int8_t acer_dma[] __unused =
105    {0x08, 0x33, 0x31};
106#endif
107