133965Sjdp/* $NetBSD: if_liireg.h,v 1.1 2008/03/29 00:16:26 cube Exp $ */ 278828Sobrien 3218822Sdim/* 460484Sobrien * Copyright (c) 2008 The NetBSD Foundation. 533965Sjdp * All rights reserved. 633965Sjdp * 733965Sjdp * Redistribution and use in source and binary forms, with or without 833965Sjdp * modification, are permitted provided that the following conditions 933965Sjdp * are met: 1033965Sjdp * 1. Redistributions of source code must retain the above copyright 1133965Sjdp * notice, this list of conditions and the following disclaimer. 1233965Sjdp * 2. Redistributions in binary form must reproduce the above copyright 1333965Sjdp * notice, this list of conditions and the following disclaimer in the 1433965Sjdp * documentation and/or other materials provided with the distribution. 1533965Sjdp * 1633965Sjdp * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 1733965Sjdp * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 1833965Sjdp * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 1933965Sjdp * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 2033965Sjdp * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21218822Sdim * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2233965Sjdp * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23218822Sdim * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2433965Sjdp * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2533965Sjdp * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 2633965Sjdp * POSSIBILITY OF SUCH DAMAGE. 2733965Sjdp */ 2833965Sjdp 2977298Sobrien/* 3077298Sobrien * PCI configuration space seems to be mapped in the first 0x100 bytes of 3177298Sobrien * the register area. 3277298Sobrien */ 3377298Sobrien 3477298Sobrien/* SPI Flash Control register */ 3577298Sobrien#define ATL2_SFC 0x0200 3677298Sobrien#define SFC_STS_NON_RDY 0x00000001 3777298Sobrien#define SFC_STS_WEN 0x00000002 3877298Sobrien#define SFC_STS_WPEN 0x00000080 3977298Sobrien#define SFC_DEV_STS_MASK 0x000000ff 4077298Sobrien#define SFC_DEV_STS_SHIFT 0 4177298Sobrien#define SFC_INS_MASK 0x07 4233965Sjdp#define SFC_INS_SHIFT 8 4333965Sjdp#define SFC_START 0x00000800 4433965Sjdp#define SFC_EN_VPD 0x00002000 4533965Sjdp#define SFC_LDSTART 0x00008000 4633965Sjdp#define SFC_CS_HI_MASK 0x03 4733965Sjdp#define SFC_CS_HI_SHIFT 16 4833965Sjdp#define SFC_CS_HOLD_MASK 0x03 4933965Sjdp#define SFC_CS_HOLD_SHIFT 18 50130561Sobrien#define SFC_CLK_LO_MASK 0x03 51130561Sobrien#define SFC_CLK_LO_SHIFT 20 52130561Sobrien#define SFC_CLK_HI_MASK 0x03 53130561Sobrien#define SFC_CLK_HI_SHIFT 22 54130561Sobrien#define SFC_CS_SETUP_MASK 0x03 55130561Sobrien#define SFC_CS_SETUP_SHIFT 24 56130561Sobrien#define SFC_EROMPGSZ_MASK 0x03 5733965Sjdp#define SFC_EROMPGSZ_SHIFT 26 5833965Sjdp#define SFC_WAIT_READY 0x10000000 5933965Sjdp 6033965Sjdp/* SPI Flash Address register */ 6133965Sjdp#define ATL2_SF_ADDR 0x0204 6233965Sjdp 6333965Sjdp/* SPI Flash Data register */ 6433965Sjdp#define ATL2_SF_DATA 0x0208 6533965Sjdp 66130561Sobrien/* SPI Flash Configuration register */ 67130561Sobrien#define ATL2_SFCF 0x020c 68218822Sdim#define SFCF_LD_ADDR_MASK 0x00ffffff 69130561Sobrien#define SFCF_LD_ADDR_SHIFT 0 7033965Sjdp#define SFCF_VPD_ADDR_MASK 0x03 7133965Sjdp#define SFCF_VPD_ADDR_SHIFT 24 7233965Sjdp#define SFCF_LD_EXISTS 0x04000000 7333965Sjdp 7433965Sjdp/* SPI Flash op codes programmation registers */ 7533965Sjdp#define ATL2_SFOP_PROGRAM 0x0210 7633965Sjdp#define ATL2_SFOP_SC_ERASE 0x0211 7733965Sjdp#define ATL2_SFOP_CHIP_ERASE 0x0212 7833965Sjdp#define ATL2_SFOP_RDID 0x0213 7933965Sjdp#define ATL2_SFOP_WREN 0x0214 8033965Sjdp#define ATL2_SFOP_RDSR 0x0215 8189857Sobrien#define ATL2_SFOP_WRSR 0x0216 82218822Sdim#define ATL2_SFOP_READ 0x0217 8333965Sjdp 8433965Sjdp/* TWSI Control register, whatever that is */ 8533965Sjdp#define ATL2_TWSIC 0x0218 8689857Sobrien#define TWSIC_LD_OFFSET_MASK 0x000000ff 8733965Sjdp#define TWSIC_LD_OFFSET_SHIFT 0 8833965Sjdp#define TWSIC_LD_SLV_ADDR_MASK 0x07 8977298Sobrien#define TWSIC_LD_SLV_ADDR_SHIFT 8 9089857Sobrien#define TWSIC_SW_LDSTART 0x00000800 9133965Sjdp#define TWSIC_HW_LDSTART 0x00001000 9233965Sjdp#define TWSIC_SMB_SLV_ADDR_MASK 0x7F 9333965Sjdp#define TWSIC_SMB_SLV_ADDR_SHIFT 15 9433965Sjdp#define TWSIC_LD_EXIST 0x00400000 9533965Sjdp#define TWSIC_READ_FREQ_SEL_MASK 0x03 9633965Sjdp#define TWSIC_READ_FREQ_SEL_SHIFT 23 9733965Sjdp#define TWSIC_FREQ_SEL_100K 0 9833965Sjdp#define TWSIC_FREQ_SEL_200K 1 9977298Sobrien#define TWSIC_FREQ_SEL_300K 2 10033965Sjdp#define TWSIC_FREQ_SEL_400K 3 10133965Sjdp#define TWSIC_WRITE_FREQ_SEL_MASK 0x03 10233965Sjdp#define TWSIC_WRITE_FREQ_SEL_SHIFT 24 10333965Sjdp 10433965Sjdp/* PCI-Express Device Misc. Control register? (size unknown) */ 10533965Sjdp#define ATL2_PCEDMC 0x021c 10633965Sjdp#define PCEDMC_RETRY_BUFDIS 0x01 10733965Sjdp#define PCEDMC_EXT_PIPE 0x02 10833965Sjdp#define PCEDMC_SPIROM_EXISTS 0x04 10933965Sjdp#define PCEDMC_SERDES_ENDIAN 0x08 11033965Sjdp#define PCEDMC_SERDES_SEL_DIN 0x10 11133965Sjdp 11233965Sjdp/* PCI-Express PHY Miscellaneous register (size unknown) */ 113218822Sdim#define ATL2_PCEPM 0x1000 114218822Sdim#define PCEPM_FORCE_RCV_DET 0x04 11533965Sjdp 116218822Sdim/* PCI-Express DLL TX Control register */ 117218822Sdim#define ATL2_PCEDTXC 0x1104 11833965Sjdp#define PCEDTX_SEL_NOR_CLK 0x00000400 119218822Sdim#define PCEDTX_DEF 0x00000568 12033965Sjdp 121218822Sdim/* PCI-Express-related register (LTSSM test mode) */ 122218822Sdim#define ATL2_PCELTM 0x12fc 12333965Sjdp#define PCELTM_DEF 0x00006500 12460484Sobrien 12533965Sjdp/* Selene Master Control register */ 12633965Sjdp#define ATL2_SMC 0x1400 12733965Sjdp#define SMC_SOFT_RST 0x00000001 128218822Sdim#define SMC_MTIMER_EN 0x00000002 12933965Sjdp#define SMC_ITIMER_EN 0x00000004 13033965Sjdp#define SMC_MANUAL_INT 0x00000008 131218822Sdim#define SMC_REV_NUM_MASK 0xff 13233965Sjdp#define SMC_REV_NUM_SHIFT 16 133218822Sdim#define SMC_DEV_ID_MASK 0xff 134218822Sdim#define SMC_DEV_ID_SHIFT 24 13533965Sjdp 13633965Sjdp/* Timer Initial Value register */ 13733965Sjdp#define ATL2_TIV 0x1404 13833965Sjdp 13933965Sjdp/* IRQ Moderator Timer Initial Value register */ 14033965Sjdp#define ATL2_IMTIV 0x1408 14133965Sjdp 14233965Sjdp/* PHY Control register */ 14333965Sjdp#define ATL2_PHYC 0x140c 14433965Sjdp#define PHYC_ENABLE 0x0001 14533965Sjdp 14633965Sjdp/* IRQ Anti-Lost Timer Initial Value register 14733965Sjdp --> Time allowed for software to clear the interrupt */ 14889857Sobrien#define ATL2_IALTIV 0x140e 14989857Sobrien 15033965Sjdp/* Block Idle Status register 15133965Sjdp --> Bit set if matching state machine is not idle */ 15277298Sobrien#define ATL2_BIS 0x1410 15333965Sjdp#define BIS_RXMAC 0x00000001 15433965Sjdp#define BIS_TXMAC 0x00000002 15533965Sjdp#define BIS_DMAR 0x00000004 15633965Sjdp#define BIS_DMAW 0x00000008 15789857Sobrien 15833965Sjdp/* MDIO Control register */ 159218822Sdim#define ATL2_MDIOC 0x1414 160218822Sdim#define MDIOC_DATA_MASK 0x0000ffff 161218822Sdim#define MDIOC_DATA_SHIFT 0 16233965Sjdp#define MDIOC_REG_MASK 0x1f 16389857Sobrien#define MDIOC_REG_SHIFT 16 164218822Sdim#define MDIOC_WRITE 0x00000000 165218822Sdim#define MDIOC_READ 0x00200000 16633965Sjdp#define MDIOC_SUP_PREAMBLE 0x00400000 16789857Sobrien#define MDIOC_START 0x00800000 168218822Sdim#define MDIOC_CLK_SEL_MASK 0x07 169218822Sdim#define MDIOC_CLK_SEL_SHIFT 24 17033965Sjdp#define MDIOC_CLK_25_4 0 17189857Sobrien#define MDIOC_CLK_25_6 2 17233965Sjdp#define MDIOC_CLK_25_8 3 173218822Sdim#define MDIOC_CLK_25_10 4 17433965Sjdp#define MDIOC_CLK_25_14 5 17533965Sjdp#define MDIOC_CLK_25_20 6 17633965Sjdp#define MDIOC_CLK_25_28 7 17733965Sjdp#define MDIOC_BUSY 0x08000000 178218822Sdim/* Time to wait for MDIO, waiting for 2us in-between */ 179218822Sdim#define MDIO_WAIT_TIMES 10 18033965Sjdp 18133965Sjdp/* SerDes Lock Detect Control and Status register */ 18233965Sjdp#define ATL2_SERDES 0x1424 18333965Sjdp#define SERDES_LOCK_DETECT 0x01 18433965Sjdp#define SERDES_LOCK_DETECT_EN 0x02 18533965Sjdp 18633965Sjdp/* MAC Control register */ 18733965Sjdp#define ATL2_MACC 0x1480 18833965Sjdp#define MACC_TX_EN 0x00000001 18933965Sjdp#define MACC_RX_EN 0x00000002 19033965Sjdp#define MACC_TX_FLOW_EN 0x00000004 19133965Sjdp#define MACC_RX_FLOW_EN 0x00000008 19233965Sjdp#define MACC_LOOPBACK 0x00000010 19333965Sjdp#define MACC_FDX 0x00000020 19433965Sjdp#define MACC_ADD_CRC 0x00000040 19533965Sjdp#define MACC_PAD 0x00000080 19633965Sjdp#define MACC_PREAMBLE_LEN_MASK 0x0f 19733965Sjdp#define MACC_PREAMBLE_LEN_SHIFT 10 19833965Sjdp#define MACC_STRIP_VLAN 0x00004000 19933965Sjdp#define MACC_PROMISC_EN 0x00008000 20033965Sjdp#define MACC_DBG_TX_BKPRESSURE 0x00100000 20133965Sjdp#define MACC_ALLMULTI_EN 0x02000000 20277298Sobrien#define MACC_BCAST_EN 0x04000000 20333965Sjdp#define MACC_MACLP_CLK_PHY 0x08000000 20433965Sjdp#define MACC_HDX_LEFT_BUF_MASK 0x0f 20533965Sjdp#define MACC_HDX_LEFT_BUF_SHIFT 28 20633965Sjdp 20733965Sjdp/* MAC IPG/IFG Control register */ 20877298Sobrien#define ATL2_MIPFG 0x1484 20991041Sobrien#define MIPFG_IPGT_MASK 0x0000007f 21033965Sjdp#define MIPFG_IPGT_SHIFT 0 21133965Sjdp#define MIPFG_MIFG_MASK 0xff 21233965Sjdp#define MIPFG_MIFG_SHIFT 8 21333965Sjdp#define MIPFG_IPGR1_MASK 0x7f 21433965Sjdp#define MIPFG_IPGR1_SHIFT 16 21533965Sjdp#define MIPFG_IPGR2_MASK 0x7f 21633965Sjdp#define MIPFG_IPGR2_SHIFT 24 21733965Sjdp 21833965Sjdp/* MAC Address registers */ 21933965Sjdp#define ATL2_MAC_ADDR_0 0x1488 22033965Sjdp#define ATL2_MAC_ADDR_1 0x148c 22133965Sjdp 22233965Sjdp/* Multicast Hash Table register */ 22333965Sjdp#define ATL2_MHT 0x1490 22489857Sobrien 22533965Sjdp/* MAC Half-Duplex Control register */ 22689857Sobrien#define ATL2_MHDC 0x1498 22789857Sobrien#define MHDC_LCOL_MASK 0x000003ff 22889857Sobrien#define MHDC_LCOL_SHIFT 0 22989857Sobrien#define MHDC_RETRY_MASK 0x0f 23089857Sobrien#define MHDC_RETRY_SHIFT 12 23133965Sjdp#define MHDC_EXC_DEF_EN 0x00010000 23233965Sjdp#define MHDC_NO_BACK_C 0x00020000 23333965Sjdp#define MHDC_NO_BACK_P 0x00040000 23433965Sjdp#define MHDC_ABEDE 0x00080000 23533965Sjdp#define MHDC_ABEBT_MASK 0x0f 23633965Sjdp#define MHDC_ABEBT_SHIFT 20 23733965Sjdp#define MHDC_JAMIPG_MASK 0x0f 23833965Sjdp#define MHDC_JAMIPG_SHIFT 24 23933965Sjdp 24033965Sjdp/* MTU Control register */ 24133965Sjdp#define ATL2_MTU 0x149c 24233965Sjdp 24333965Sjdp/* WOL Control register */ 24433965Sjdp#define ATL2_WOLC 24533965Sjdp#define WOLC_PATTERN_EN 0x00000001 24633965Sjdp#define WOLC_PATTERN_PME_EN 0x00000002 24733965Sjdp#define WOLC_MAGIC_EN 0x00000004 24860484Sobrien#define WOLC_MAGIC_PME_EN 0x00000008 24933965Sjdp#define WOLC_LINK_CHG_EN 0x00000010 25033965Sjdp#define WOLC_LINK_CHG_PME_EN 0x00000020 25133965Sjdp#define WOLC_PATTERN_ST 0x00000100 25233965Sjdp#define WOLC_MAGIC_ST 0x00000200 25333965Sjdp#define WOLC_LINK_CHG_ST 0x00000400 25433965Sjdp#define WOLC_PT0_EN 0x00010000 25533965Sjdp#define WOLC_PT1_EN 0x00020000 25633965Sjdp#define WOLC_PT2_EN 0x00040000 25733965Sjdp#define WOLC_PT3_EN 0x00080000 25833965Sjdp#define WOLC_PT4_EN 0x00100000 25977298Sobrien#define WOLC_PT0_MATCH 0x01000000 26033965Sjdp#define WOLC_PT1_MATCH 0x02000000 26177298Sobrien#define WOLC_PT2_MATCH 0x04000000 26233965Sjdp#define WOLC_PT3_MATCH 0x08000000 26333965Sjdp#define WOLC_PT4_MATCH 0x10000000 264130561Sobrien 265130561Sobrien/* Internal SRAM Partition register */ 266130561Sobrien#define ATL2_SRAM_TXRAM_END 0x1500 267130561Sobrien#define ATL2_SRAM_RXRAM_END 0x1502 268130561Sobrien 269130561Sobrien/* Descriptor Control registers */ 270130561Sobrien#define ATL2_DESC_BASE_ADDR_HI 0x1540 27133965Sjdp#define ATL2_TXD_BASE_ADDR_LO 0x1544 27233965Sjdp#define ATL2_TXD_BUFFER_SIZE 0x1548 27333965Sjdp#define ATL2_TXS_BASE_ADDR_LO 0x154c 27433965Sjdp#define ATL2_TXS_NUM_ENTRIES 0x1550 27533965Sjdp#define ATL2_RXD_BASE_ADDR_LO 0x1554 27633965Sjdp#define ATL2_RXD_NUM_ENTRIES 0x1558 27733965Sjdp 27833965Sjdp/* DMAR Control register */ 27933965Sjdp#define ATL2_DMAR 0x1580 28033965Sjdp#define DMAR_EN 0x01 28133965Sjdp 28233965Sjdp/* TX Cur-Through Control register */ 28333965Sjdp#define ATL2_TX_CUT_THRESH 0x1590 284130561Sobrien 285130561Sobrien/* DMAW Control register */ 286130561Sobrien#define ATL2_DMAW 0x15a0 287130561Sobrien#define DMAW_EN 0x01 288130561Sobrien 289130561Sobrien/* Flow Control registers */ 29033965Sjdp#define ATL2_PAUSE_ON_TH 0x15a8 29133965Sjdp#define ATL2_PAUSE_OFF_TH 0x15aa 292130561Sobrien 293130561Sobrien/* Mailbox registers */ 294130561Sobrien#define ATL2_MB_TXD_WR_IDX 0x15f0 295130561Sobrien#define ATL2_MB_RXD_RD_IDX 0x15f4 29633965Sjdp 29733965Sjdp/* Interrupt Status register */ 298130561Sobrien#define ATL2_ISR 0x1600 299130561Sobrien#define ISR_TIMER 0x00000001 30033965Sjdp#define ISR_MANUAL 0x00000002 30133965Sjdp#define ISR_RXF_OV 0x00000004 302130561Sobrien#define ISR_TXF_UR 0x00000008 303130561Sobrien#define ISR_TXS_OV 0x00000010 30433965Sjdp#define ISR_RXS_OV 0x00000020 30577298Sobrien#define ISR_LINK_CHG 0x00000040 306130561Sobrien#define ISR_HOST_TXD_UR 0x00000080 307130561Sobrien#define ISR_HOST_RXD_OV 0x00000100 308130561Sobrien#define ISR_DMAR_TO_RST 0x00000200 309130561Sobrien#define ISR_DMAW_TO_RST 0x00000400 310130561Sobrien#define ISR_PHY 0x00000800 311130561Sobrien#define ISR_TS_UPDATE 0x00010000 312130561Sobrien#define ISR_RS_UPDATE 0x00020000 313130561Sobrien#define ISR_TX_EARLY 0x00040000 314130561Sobrien#define ISR_UR_DETECTED 0x01000000 31533965Sjdp#define ISR_FERR_DETECTED 0x02000000 31660484Sobrien#define ISR_NFERR_DETECTED 0x04000000 31777298Sobrien#define ISR_CERR_DETECTED 0x08000000 31833965Sjdp#define ISR_PHY_LINKDOWN 0x10000000 319130561Sobrien#define ISR_DIS_INT 0x80000000 320 321#define ISR_TX_EVENT (ISR_TXF_UR | ISR_TXS_OV | \ 322 ISR_HOST_TXD_UR | ISR_TS_UPDATE | \ 323 ISR_TX_EARLY) 324#define ISR_RX_EVENT (ISR_RXF_OV | ISR_RXS_OV | \ 325 ISR_HOST_RXD_OV | ISR_RS_UPDATE) 326 327/* Interrupt Mask register */ 328#define ATL2_IMR 0x1604 329#define IMR_NORMAL_MASK (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST | \ 330 ISR_PHY | ISR_PHY_LINKDOWN | \ 331 ISR_TS_UPDATE | ISR_RS_UPDATE | \ 332 ISR_MANUAL) 333 334/* MAC RX Statistics registers */ 335#define ATL2_STS_RX_PAUSE 0x1700 336#define ATL2_STS_RXD_OV 0x1704 337#define ATL2_STS_RXS_OV 0x1708 338#define ATL2_STS_RX_FILTER 0x170c 339 340struct tx_pkt_header { 341 uint16_t txph_size; 342#define ATL2_TXH_ADD_VLAN_TAG 0x8000 343 uint16_t txph_vlan; 344} __packed; 345 346struct tx_pkt_status { 347 uint16_t txps_size; 348 uint16_t txps_flags :15; 349#define ATL2_TXF_SUCCESS 0x0001 350#define ATL2_TXF_BCAST 0x0002 351#define ATL2_TXF_MCAST 0x0004 352#define ATL2_TXF_PAUSE 0x0008 353#define ATL2_TXF_CTRL 0x0010 354#define ATL2_TXF_DEFER 0x0020 355#define ATL2_TXF_EXC_DEFER 0x0040 356#define ATL2_TXF_SINGLE_COL 0x0080 357#define ATL2_TXF_MULTI_COL 0x0100 358#define ATL2_TXF_LATE_COL 0x0200 359#define ATL2_TXF_ABORT_COL 0x0400 360#define ATL2_TXF_UNDERRUN 0x0800 361 uint16_t txps_update:1; 362} __packed; 363 364struct rx_pkt { 365 uint16_t rxp_size; 366 uint16_t rxp_flags :15; 367#define ATL2_RXF_SUCCESS 0x0001 368#define ATL2_RXF_BCAST 0x0002 369#define ATL2_RXF_MCAST 0x0004 370#define ATL2_RXF_PAUSE 0x0008 371#define ATL2_RXF_CTRL 0x0010 372#define ATL2_RXF_CRC 0x0020 373#define ATL2_RXF_CODE 0x0040 374#define ATL2_RXF_RUNT 0x0080 375#define ATL2_RXF_FRAG 0x0100 376#define ATL2_RXF_TRUNC 0x0200 377#define ATL2_RXF_ALIGN 0x0400 378#define ATL2_RXF_VLAN 0x0800 379 uint16_t rxp_update:1; 380 uint16_t rxp_vlan; 381 uint16_t __pad; 382 uint8_t rxp_data[1528]; 383} __packed; 384