1/* $NetBSD: if_iwnreg.h,v 1.9 2011/05/15 13:56:20 christos Exp $ */ 2/* $OpenBSD: if_iwnreg.h,v 1.40 2010/05/05 19:41:57 damien Exp $ */ 3 4/*- 5 * Copyright (c) 2007, 2008 6 * Damien Bergamini <damien.bergamini@free.fr> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21/* XXX Added for NetBSD */ 22#define EDCA_NUM_AC 4 23#define IEEE80211_TKIP_MICLEN 8 24 25#define IWN_TX_RING_COUNT 256 26#define IWN_TX_RING_LOMARK 192 27#define IWN_TX_RING_HIMARK 224 28#define IWN_RX_RING_COUNT_LOG 6 29#define IWN_RX_RING_COUNT (1 << IWN_RX_RING_COUNT_LOG) 30 31#define IWN4965_NTXQUEUES 16 32#define IWN5000_NTXQUEUES 20 33 34#define IWN4965_NDMACHNLS 7 35#define IWN5000_NDMACHNLS 8 36 37#define IWN_SRVC_DMACHNL 9 38 39#define IWN_ICT_SIZE 4096 40#define IWN_ICT_COUNT (IWN_ICT_SIZE / sizeof (uint32_t)) 41 42/* Maximum number of DMA segments for TX. */ 43#define IWN_MAX_SCATTER 20 44 45/* RX buffers must be large enough to hold a full 4K A-MPDU. */ 46#define IWN_RBUF_SIZE (4 * 1024) 47 48#if defined(__LP64__) 49/* HW supports 36-bit DMA addresses. */ 50#define IWN_LOADDR(paddr) ((uint32_t)(paddr)) 51#define IWN_HIADDR(paddr) (((paddr) >> 32) & 0xf) 52#else 53#define IWN_LOADDR(paddr) (paddr) 54#define IWN_HIADDR(paddr) (0) 55#endif 56 57/* Base Address Register. */ 58#define IWN_PCI_BAR0 PCI_MAPREG_START 59 60/* 61 * Control and status registers. 62 */ 63#define IWN_HW_IF_CONFIG 0x000 64#define IWN_INT_COALESCING 0x004 65#define IWN_INT_PERIODIC 0x005 /* use IWN_WRITE_1 */ 66#define IWN_INT 0x008 67#define IWN_INT_MASK 0x00c 68#define IWN_FH_INT 0x010 69#define IWN_RESET 0x020 70#define IWN_GP_CNTRL 0x024 71#define IWN_HW_REV 0x028 72#define IWN_EEPROM 0x02c 73#define IWN_EEPROM_GP 0x030 74#define IWN_OTP_GP 0x034 75#define IWN_GIO 0x03c 76#define IWN_GP_DRIVER 0x050 77#define IWN_UCODE_GP1_CLR 0x05c 78#define IWN_LED 0x094 79#define IWN_DRAM_INT_TBL 0x0a0 80#define IWN_SHADOW_REG_CTRL 0x0a8 81#define IWN_GIO_CHICKEN 0x100 82#define IWN_ANA_PLL 0x20c 83#define IWN_HW_REV_WA 0x22c 84#define IWN_DBG_HPET_MEM 0x240 85#define IWN_DBG_LINK_PWR_MGMT 0x250 86#define IWN_MEM_RADDR 0x40c 87#define IWN_MEM_WADDR 0x410 88#define IWN_MEM_WDATA 0x418 89#define IWN_MEM_RDATA 0x41c 90#define IWN_PRPH_WADDR 0x444 91#define IWN_PRPH_RADDR 0x448 92#define IWN_PRPH_WDATA 0x44c 93#define IWN_PRPH_RDATA 0x450 94#define IWN_HBUS_TARG_WRPTR 0x460 95 96/* 97 * Flow-Handler registers. 98 */ 99#define IWN_FH_TFBD_CTRL0(qid) (0x1900 + (qid) * 8) 100#define IWN_FH_TFBD_CTRL1(qid) (0x1904 + (qid) * 8) 101#define IWN_FH_KW_ADDR 0x197c 102#define IWN_FH_SRAM_ADDR(qid) (0x19a4 + (qid) * 4) 103#define IWN_FH_CBBC_QUEUE(qid) (0x19d0 + (qid) * 4) 104#define IWN_FH_STATUS_WPTR 0x1bc0 105#define IWN_FH_RX_BASE 0x1bc4 106#define IWN_FH_RX_WPTR 0x1bc8 107#define IWN_FH_RX_CONFIG 0x1c00 108#define IWN_FH_RX_STATUS 0x1c44 109#define IWN_FH_TX_CONFIG(qid) (0x1d00 + (qid) * 32) 110#define IWN_FH_TXBUF_STATUS(qid) (0x1d08 + (qid) * 32) 111#define IWN_FH_TX_CHICKEN 0x1e98 112#define IWN_FH_TX_STATUS 0x1eb0 113 114/* 115 * TX scheduler registers. 116 */ 117#define IWN_SCHED_BASE 0xa02c00 118#define IWN_SCHED_SRAM_ADDR (IWN_SCHED_BASE + 0x000) 119#define IWN5000_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x008) 120#define IWN4965_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x010) 121#define IWN5000_SCHED_TXFACT (IWN_SCHED_BASE + 0x010) 122#define IWN4965_SCHED_TXFACT (IWN_SCHED_BASE + 0x01c) 123#define IWN4965_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x064 + (qid) * 4) 124#define IWN5000_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x068 + (qid) * 4) 125#define IWN4965_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0d0) 126#define IWN4965_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x0e4) 127#define IWN5000_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0e8) 128#define IWN4965_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x104 + (qid) * 4) 129#define IWN5000_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x108) 130#define IWN5000_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x10c + (qid) * 4) 131#define IWN5000_SCHED_AGGR_SEL (IWN_SCHED_BASE + 0x248) 132 133/* 134 * Offsets in TX scheduler's SRAM. 135 */ 136#define IWN4965_SCHED_CTX_OFF 0x380 137#define IWN4965_SCHED_CTX_LEN 416 138#define IWN4965_SCHED_QUEUE_OFFSET(qid) (0x380 + (qid) * 8) 139#define IWN4965_SCHED_TRANS_TBL(qid) (0x500 + (qid) * 2) 140#define IWN5000_SCHED_CTX_OFF 0x600 141#define IWN5000_SCHED_CTX_LEN 520 142#define IWN5000_SCHED_QUEUE_OFFSET(qid) (0x600 + (qid) * 8) 143#define IWN5000_SCHED_TRANS_TBL(qid) (0x7e0 + (qid) * 2) 144 145/* 146 * NIC internal memory offsets. 147 */ 148#define IWN_APMG_CLK_CTRL 0x3000 149#define IWN_APMG_CLK_EN 0x3004 150#define IWN_APMG_CLK_DIS 0x3008 151#define IWN_APMG_PS 0x300c 152#define IWN_APMG_DIGITAL_SVR 0x3058 153#define IWN_APMG_ANALOG_SVR 0x306c 154#define IWN_APMG_PCI_STT 0x3010 155#define IWN_BSM_WR_CTRL 0x3400 156#define IWN_BSM_WR_MEM_SRC 0x3404 157#define IWN_BSM_WR_MEM_DST 0x3408 158#define IWN_BSM_WR_DWCOUNT 0x340c 159#define IWN_BSM_DRAM_TEXT_ADDR 0x3490 160#define IWN_BSM_DRAM_TEXT_SIZE 0x3494 161#define IWN_BSM_DRAM_DATA_ADDR 0x3498 162#define IWN_BSM_DRAM_DATA_SIZE 0x349c 163#define IWN_BSM_SRAM_BASE 0x3800 164 165/* Possible flags for register IWN_HW_IF_CONFIG. */ 166#define IWN_HW_IF_CONFIG_4965_R (1 << 4) 167#define IWN_HW_IF_CONFIG_MAC_SI (1 << 8) 168#define IWN_HW_IF_CONFIG_RADIO_SI (1 << 9) 169#define IWN_HW_IF_CONFIG_EEPROM_LOCKED (1 << 21) 170#define IWN_HW_IF_CONFIG_NIC_READY (1 << 22) 171#define IWN_HW_IF_CONFIG_HAP_WAKE_L1A (1 << 23) 172#define IWN_HW_IF_CONFIG_PREPARE_DONE (1 << 25) 173#define IWN_HW_IF_CONFIG_PREPARE (1 << 27) 174 175/* Possible values for register IWN_INT_PERIODIC. */ 176#define IWN_INT_PERIODIC_DIS 0x00 177#define IWN_INT_PERIODIC_ENA 0xff 178 179/* Possible flags for registers IWN_PRPH_RADDR/IWN_PRPH_WADDR. */ 180#define IWN_PRPH_DWORD ((sizeof (uint32_t) - 1) << 24) 181 182/* Possible values for IWN_BSM_WR_MEM_DST. */ 183#define IWN_FW_TEXT_BASE 0x00000000 184#define IWN_FW_DATA_BASE 0x00800000 185 186/* Possible flags for register IWN_RESET. */ 187#define IWN_RESET_NEVO (1 << 0) 188#define IWN_RESET_SW (1 << 7) 189#define IWN_RESET_MASTER_DISABLED (1 << 8) 190#define IWN_RESET_STOP_MASTER (1 << 9) 191#define IWN_RESET_LINK_PWR_MGMT_DIS (1 << 31) 192 193/* Possible flags for register IWN_GP_CNTRL. */ 194#define IWN_GP_CNTRL_MAC_ACCESS_ENA (1 << 0) 195#define IWN_GP_CNTRL_MAC_CLOCK_READY (1 << 0) 196#define IWN_GP_CNTRL_INIT_DONE (1 << 2) 197#define IWN_GP_CNTRL_MAC_ACCESS_REQ (1 << 3) 198#define IWN_GP_CNTRL_SLEEP (1 << 4) 199#define IWN_GP_CNTRL_RFKILL (1 << 27) 200 201/* Possible flags for register IWN_HW_REV. */ 202#define IWN_HW_REV_TYPE_SHIFT 4 203#define IWN_HW_REV_TYPE_MASK 0x000000f0 204#define IWN_HW_REV_TYPE_4965 0 205#define IWN_HW_REV_TYPE_5300 2 206#define IWN_HW_REV_TYPE_5350 3 207#define IWN_HW_REV_TYPE_5150 4 208#define IWN_HW_REV_TYPE_5100 5 209#define IWN_HW_REV_TYPE_1000 6 210#define IWN_HW_REV_TYPE_6000 7 211#define IWN_HW_REV_TYPE_6050 8 212#define IWN_HW_REV_TYPE_6005 11 213 214/* Possible flags for register IWN_GIO_CHICKEN. */ 215#define IWN_GIO_CHICKEN_L1A_NO_L0S_RX (1 << 23) 216#define IWN_GIO_CHICKEN_DIS_L0S_TIMER (1 << 29) 217 218/* Possible flags for register IWN_GIO. */ 219#define IWN_GIO_L0S_ENA (1 << 1) 220 221/* Possible flags for register IWN_GP_DRIVER. */ 222#define IWN_GP_DRIVER_RADIO_3X3_HYB (0 << 0) 223#define IWN_GP_DRIVER_RADIO_2X2_HYB (1 << 0) 224#define IWN_GP_DRIVER_RADIO_2X2_IPA (2 << 0) 225#define IWN_GP_DRIVER_CALIB_VER6 (1 << 2) 226#define IWN_GP_DRIVER_6050_1X2 (1 << 3) 227 228/* Possible flags for register IWN_UCODE_GP1_CLR. */ 229#define IWN_UCODE_GP1_RFKILL (1 << 1) 230#define IWN_UCODE_GP1_CMD_BLOCKED (1 << 2) 231#define IWN_UCODE_GP1_CTEMP_STOP_RF (1 << 3) 232 233/* Possible flags/values for register IWN_LED. */ 234#define IWN_LED_BSM_CTRL (1 << 5) 235#define IWN_LED_OFF 0x00000038 236#define IWN_LED_ON 0x00000078 237 238/* Possible flags for register IWN_DRAM_INT_TBL. */ 239#define IWN_DRAM_INT_TBL_WRAP_CHECK (1 << 27) 240#define IWN_DRAM_INT_TBL_ENABLE (1 << 31) 241 242/* Possible values for register IWN_ANA_PLL. */ 243#define IWN_ANA_PLL_INIT 0x00880300 244 245/* Possible flags for register IWN_FH_RX_STATUS. */ 246#define IWN_FH_RX_STATUS_IDLE (1 << 24) 247 248/* Possible flags for register IWN_BSM_WR_CTRL. */ 249#define IWN_BSM_WR_CTRL_START_EN (1 << 30) 250#define IWN_BSM_WR_CTRL_START (1 << 31) 251 252/* Possible flags for register IWN_INT. */ 253#define IWN_INT_ALIVE (1 << 0) 254#define IWN_INT_WAKEUP (1 << 1) 255#define IWN_INT_SW_RX (1 << 3) 256#define IWN_INT_CT_REACHED (1 << 6) 257#define IWN_INT_RF_TOGGLED (1 << 7) 258#define IWN_INT_SW_ERR (1 << 25) 259#define IWN_INT_SCHED (1 << 26) 260#define IWN_INT_FH_TX (1 << 27) 261#define IWN_INT_RX_PERIODIC (1 << 28) 262#define IWN_INT_HW_ERR (1 << 29) 263#define IWN_INT_FH_RX (1 << 31) 264 265/* Shortcut. */ 266#define IWN_INT_MASK_DEF \ 267 (IWN_INT_SW_ERR | IWN_INT_HW_ERR | IWN_INT_FH_TX | \ 268 IWN_INT_FH_RX | IWN_INT_ALIVE | IWN_INT_WAKEUP | \ 269 IWN_INT_SW_RX | IWN_INT_CT_REACHED | IWN_INT_RF_TOGGLED) 270 271/* Possible flags for register IWN_FH_INT. */ 272#define IWN_FH_INT_TX_CHNL(x) (1 << (x)) 273#define IWN_FH_INT_RX_CHNL(x) (1 << ((x) + 16)) 274#define IWN_FH_INT_HI_PRIOR (1 << 30) 275/* Shortcuts for the above. */ 276#define IWN_FH_INT_TX \ 277 (IWN_FH_INT_TX_CHNL(0) | IWN_FH_INT_TX_CHNL(1)) 278#define IWN_FH_INT_RX \ 279 (IWN_FH_INT_RX_CHNL(0) | IWN_FH_INT_RX_CHNL(1) | IWN_FH_INT_HI_PRIOR) 280 281/* Possible flags/values for register IWN_FH_TX_CONFIG. */ 282#define IWN_FH_TX_CONFIG_DMA_PAUSE 0 283#define IWN_FH_TX_CONFIG_DMA_ENA (1 << 31) 284#define IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD (1 << 20) 285 286/* Possible flags/values for register IWN_FH_TXBUF_STATUS. */ 287#define IWN_FH_TXBUF_STATUS_TBNUM(x) ((x) << 20) 288#define IWN_FH_TXBUF_STATUS_TBIDX(x) ((x) << 12) 289#define IWN_FH_TXBUF_STATUS_TFBD_VALID 3 290 291/* Possible flags for register IWN_FH_TX_CHICKEN. */ 292#define IWN_FH_TX_CHICKEN_SCHED_RETRY (1 << 1) 293 294/* Possible flags for register IWN_FH_TX_STATUS. */ 295#define IWN_FH_TX_STATUS_IDLE(chnl) (1 << ((chnl) + 16)) 296 297/* Possible flags for register IWN_FH_RX_CONFIG. */ 298#define IWN_FH_RX_CONFIG_ENA (1 << 31) 299#define IWN_FH_RX_CONFIG_NRBD(x) ((x) << 20) 300#define IWN_FH_RX_CONFIG_RB_SIZE_8K (1 << 16) 301#define IWN_FH_RX_CONFIG_SINGLE_FRAME (1 << 15) 302#define IWN_FH_RX_CONFIG_IRQ_DST_HOST (1 << 12) 303#define IWN_FH_RX_CONFIG_RB_TIMEOUT(x) ((x) << 4) 304#define IWN_FH_RX_CONFIG_IGN_RXF_EMPTY (1 << 2) 305 306/* Possible flags for register IWN_FH_TX_CONFIG. */ 307#define IWN_FH_TX_CONFIG_DMA_ENA (1 << 31) 308#define IWN_FH_TX_CONFIG_DMA_CREDIT_ENA (1 << 3) 309 310/* Possible flags for register IWN_EEPROM. */ 311#define IWN_EEPROM_READ_VALID (1 << 0) 312#define IWN_EEPROM_CMD (1 << 1) 313 314/* Possible flags for register IWN_EEPROM_GP. */ 315#define IWN_EEPROM_GP_IF_OWNER 0x00000180 316 317/* Possible flags for register IWN_OTP_GP. */ 318#define IWN_OTP_GP_DEV_SEL_OTP (1 << 16) 319#define IWN_OTP_GP_RELATIVE_ACCESS (1 << 17) 320#define IWN_OTP_GP_ECC_CORR_STTS (1 << 20) 321#define IWN_OTP_GP_ECC_UNCORR_STTS (1 << 21) 322 323/* Possible flags for register IWN_SCHED_QUEUE_STATUS. */ 324#define IWN4965_TXQ_STATUS_ACTIVE 0x0007fc01 325#define IWN4965_TXQ_STATUS_INACTIVE 0x0007fc00 326#define IWN4965_TXQ_STATUS_AGGR_ENA (1 << 5 | 1 << 8) 327#define IWN4965_TXQ_STATUS_CHGACT (1 << 10) 328#define IWN5000_TXQ_STATUS_ACTIVE 0x00ff0018 329#define IWN5000_TXQ_STATUS_INACTIVE 0x00ff0010 330#define IWN5000_TXQ_STATUS_CHGACT (1 << 19) 331 332/* Possible flags for registers IWN_APMG_CLK_*. */ 333#define IWN_APMG_CLK_CTRL_DMA_CLK_RQT (1 << 9) 334#define IWN_APMG_CLK_CTRL_BSM_CLK_RQT (1 << 11) 335 336/* Possible flags for register IWN_APMG_PS. */ 337#define IWN_APMG_PS_EARLY_PWROFF_DIS (1 << 22) 338#define IWN_APMG_PS_PWR_SRC(x) ((x) << 24) 339#define IWN_APMG_PS_PWR_SRC_VMAIN 0 340#define IWN_APMG_PS_PWR_SRC_VAUX 2 341#define IWN_APMG_PS_PWR_SRC_MASK IWN_APMG_PS_PWR_SRC(3) 342#define IWN_APMG_PS_RESET_REQ (1 << 26) 343 344/* Possible flags for register IWN_APMG_DIGITAL_SVR. */ 345#define IWN_APMG_DIGITAL_SVR_VOLTAGE(x) (((x) & 0xf) << 5) 346#define IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK \ 347 IWN_APMG_DIGITAL_SVR_VOLTAGE(0xf) 348#define IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32 \ 349 IWN_APMG_DIGITAL_SVR_VOLTAGE(3) 350 351/* Possible flags for IWN_APMG_PCI_STT. */ 352#define IWN_APMG_PCI_STT_L1A_DIS (1 << 11) 353 354/* Possible flags for register IWN_BSM_DRAM_TEXT_SIZE. */ 355#define IWN_FW_UPDATED (1 << 31) 356 357#define IWN_SCHED_WINSZ 64 358#define IWN_SCHED_LIMIT 64 359#define IWN4965_SCHED_COUNT 512 360#define IWN5000_SCHED_COUNT (IWN_TX_RING_COUNT + IWN_SCHED_WINSZ) 361#define IWN4965_SCHEDSZ (IWN4965_NTXQUEUES * IWN4965_SCHED_COUNT * 2) 362#define IWN5000_SCHEDSZ (IWN5000_NTXQUEUES * IWN5000_SCHED_COUNT * 2) 363 364struct iwn_tx_desc { 365 uint8_t reserved1[3]; 366 uint8_t nsegs; 367 struct { 368 uint32_t addr; 369 uint16_t len; 370 } __packed segs[IWN_MAX_SCATTER]; 371 /* Pad to 128 bytes. */ 372 uint32_t reserved2; 373} __packed; 374 375struct iwn_rx_status { 376 uint16_t closed_count; 377 uint16_t closed_rx_count; 378 uint16_t finished_count; 379 uint16_t finished_rx_count; 380 uint32_t reserved[2]; 381} __packed; 382 383struct iwn_rx_desc { 384 uint32_t len; 385 uint8_t type; 386#define IWN_UC_READY 1 387#define IWN_ADD_NODE_DONE 24 388#define IWN_TX_DONE 28 389#define IWN5000_CALIBRATION_RESULT 102 390#define IWN5000_CALIBRATION_DONE 103 391#define IWN_START_SCAN 130 392#define IWN_STOP_SCAN 132 393#define IWN_RX_STATISTICS 156 394#define IWN_BEACON_STATISTICS 157 395#define IWN_STATE_CHANGED 161 396#define IWN_BEACON_MISSED 162 397#define IWN_RX_PHY 192 398#define IWN_MPDU_RX_DONE 193 399#define IWN_RX_DONE 195 400#define IWN_RX_COMPRESSED_BA 197 401 402 uint8_t flags; 403 uint8_t idx; 404 uint8_t qid; 405} __packed; 406 407/* Possible RX status flags. */ 408#define IWN_RX_NO_CRC_ERR (1 << 0) 409#define IWN_RX_NO_OVFL_ERR (1 << 1) 410/* Shortcut for the above. */ 411#define IWN_RX_NOERROR (IWN_RX_NO_CRC_ERR | IWN_RX_NO_OVFL_ERR) 412#define IWN_RX_MPDU_MIC_OK (1 << 6) 413#define IWN_RX_CIPHER_MASK (7 << 8) 414#define IWN_RX_CIPHER_CCMP (2 << 8) 415#define IWN_RX_MPDU_DEC (1 << 11) 416#define IWN_RX_DECRYPT_MASK (3 << 11) 417#define IWN_RX_DECRYPT_OK (3 << 11) 418 419struct iwn_tx_cmd { 420 uint8_t code; 421#define IWN_CMD_RXON 16 422#define IWN_CMD_RXON_ASSOC 17 423#define IWN_CMD_EDCA_PARAMS 19 424#define IWN_CMD_TIMING 20 425#define IWN_CMD_ADD_NODE 24 426#define IWN_CMD_TX_DATA 28 427#define IWN_CMD_LINK_QUALITY 78 428#define IWN_CMD_SET_LED 72 429#define IWN5000_CMD_WIMAX_COEX 90 430#define IWN5000_CMD_CALIB_CONFIG 101 431#define IWN_CMD_SET_POWER_MODE 119 432#define IWN_CMD_SCAN 128 433#define IWN_CMD_TXPOWER_DBM 149 434#define IWN_CMD_TXPOWER 151 435#define IWN5000_CMD_TX_ANT_CONFIG 152 436#define IWN_CMD_BT_COEX 155 437#define IWN_CMD_GET_STATISTICS 156 438#define IWN_CMD_SET_CRITICAL_TEMP 164 439#define IWN_CMD_SET_SENSITIVITY 168 440#define IWN_CMD_PHY_CALIB 176 441 442 uint8_t flags; 443 uint8_t idx; 444 uint8_t qid; 445 uint8_t data[136]; 446} __packed; 447 448/* Antenna flags, used in various commands. */ 449#define IWN_ANT_A (1 << 0) 450#define IWN_ANT_B (1 << 1) 451#define IWN_ANT_C (1 << 2) 452/* Shortcuts. */ 453#define IWN_ANT_AB (IWN_ANT_A | IWN_ANT_B) 454#define IWN_ANT_BC (IWN_ANT_B | IWN_ANT_C) 455#define IWN_ANT_ABC (IWN_ANT_A | IWN_ANT_B | IWN_ANT_C) 456 457/* Structure for command IWN_CMD_RXON. */ 458struct iwn_rxon { 459 uint8_t myaddr[IEEE80211_ADDR_LEN]; 460 uint16_t reserved1; 461 uint8_t bssid[IEEE80211_ADDR_LEN]; 462 uint16_t reserved2; 463 uint8_t wlap[IEEE80211_ADDR_LEN]; 464 uint16_t reserved3; 465 uint8_t mode; 466#define IWN_MODE_HOSTAP 1 467#define IWN_MODE_STA 3 468#define IWN_MODE_IBSS 4 469#define IWN_MODE_MONITOR 6 470 471 uint8_t air; 472 uint16_t rxchain; 473#define IWN_RXCHAIN_DRIVER_FORCE (1 << 0) 474#define IWN_RXCHAIN_VALID(x) (((x) & IWN_ANT_ABC) << 1) 475#define IWN_RXCHAIN_FORCE_SEL(x) (((x) & IWN_ANT_ABC) << 4) 476#define IWN_RXCHAIN_FORCE_MIMO_SEL(x) (((x) & IWN_ANT_ABC) << 7) 477#define IWN_RXCHAIN_IDLE_COUNT(x) ((x) << 10) 478#define IWN_RXCHAIN_MIMO_COUNT(x) ((x) << 12) 479#define IWN_RXCHAIN_MIMO_FORCE (1 << 14) 480 481 uint8_t ofdm_mask; 482 uint8_t cck_mask; 483 uint16_t associd; 484 uint32_t flags; 485#define IWN_RXON_24GHZ (1 << 0) 486#define IWN_RXON_CCK (1 << 1) 487#define IWN_RXON_AUTO (1 << 2) 488#define IWN_RXON_SHSLOT (1 << 4) 489#define IWN_RXON_SHPREAMBLE (1 << 5) 490#define IWN_RXON_NODIVERSITY (1 << 7) 491#define IWN_RXON_ANTENNA_A (1 << 8) 492#define IWN_RXON_ANTENNA_B (1 << 9) 493#define IWN_RXON_TSF (1 << 15) 494#define IWN_RXON_CTS_TO_SELF (1 << 30) 495 496 uint32_t filter; 497#define IWN_FILTER_PROMISC (1 << 0) 498#define IWN_FILTER_CTL (1 << 1) 499#define IWN_FILTER_MULTICAST (1 << 2) 500#define IWN_FILTER_NODECRYPT (1 << 3) 501#define IWN_FILTER_BSS (1 << 5) 502#define IWN_FILTER_BEACON (1 << 6) 503 504 uint8_t chan; 505 uint8_t reserved4; 506 uint8_t ht_single_mask; 507 uint8_t ht_dual_mask; 508 /* The following fields are for >=5000 Series only. */ 509 uint8_t ht_triple_mask; 510 uint8_t reserved5; 511 uint16_t acquisition; 512 uint16_t reserved6; 513} __packed; 514 515#define IWN4965_RXONSZ (sizeof (struct iwn_rxon) - 6) 516#define IWN5000_RXONSZ (sizeof (struct iwn_rxon)) 517 518/* Structure for command IWN_CMD_ASSOCIATE. */ 519struct iwn_assoc { 520 uint32_t flags; 521 uint32_t filter; 522 uint8_t ofdm_mask; 523 uint8_t cck_mask; 524 uint16_t reserved; 525} __packed; 526 527/* Structure for command IWN_CMD_EDCA_PARAMS. */ 528struct iwn_edca_params { 529 uint32_t flags; 530#define IWN_EDCA_UPDATE (1 << 0) 531#define IWN_EDCA_TXOP (1 << 4) 532 533 struct { 534 uint16_t cwmin; 535 uint16_t cwmax; 536 uint8_t aifsn; 537 uint8_t reserved; 538 uint16_t txoplimit; 539 } __packed ac[EDCA_NUM_AC]; 540} __packed; 541 542/* Structure for command IWN_CMD_TIMING. */ 543struct iwn_cmd_timing { 544 uint64_t tstamp; 545 uint16_t bintval; 546 uint16_t atim; 547 uint32_t binitval; 548 uint16_t lintval; 549 uint16_t reserved; 550} __packed; 551 552/* Structure for command IWN_CMD_ADD_NODE. */ 553struct iwn_node_info { 554 uint8_t control; 555#define IWN_NODE_UPDATE (1 << 0) 556 557 uint8_t reserved1[3]; 558 559 uint8_t macaddr[IEEE80211_ADDR_LEN]; 560 uint16_t reserved2; 561 uint8_t id; 562#define IWN_ID_BSS 0 563#define IWN5000_ID_BROADCAST 15 564#define IWN4965_ID_BROADCAST 31 565 566 uint8_t flags; 567#define IWN_FLAG_SET_KEY (1 << 0) 568#define IWN_FLAG_SET_DISABLE_TID (1 << 1) 569#define IWN_FLAG_SET_TXRATE (1 << 2) 570#define IWN_FLAG_SET_ADDBA (1 << 3) 571#define IWN_FLAG_SET_DELBA (1 << 4) 572 573 uint16_t reserved3; 574 uint16_t kflags; 575#define IWN_KFLAG_CCMP (1 << 1) 576#define IWN_KFLAG_MAP (1 << 3) 577#define IWN_KFLAG_KID(kid) ((kid) << 8) 578#define IWN_KFLAG_INVALID (1 << 11) 579#define IWN_KFLAG_GROUP (1 << 14) 580 581 uint8_t tsc2; /* TKIP TSC2 */ 582 uint8_t reserved4; 583 uint16_t ttak[5]; 584 uint8_t kid; 585 uint8_t reserved5; 586 uint8_t key[16]; 587 /* The following 3 fields are for 5000 Series only. */ 588 uint64_t tsc; 589 uint8_t rxmic[IEEE80211_TKIP_MICLEN]; 590 uint8_t txmic[IEEE80211_TKIP_MICLEN]; 591 592 uint32_t htflags; 593#define IWN_AMDPU_SIZE_FACTOR(x) ((x) << 19) 594#define IWN_AMDPU_DENSITY(x) ((x) << 23) 595 596 uint32_t mask; 597 uint16_t disable_tid; 598 uint16_t reserved6; 599 uint8_t addba_tid; 600 uint8_t delba_tid; 601 uint16_t addba_ssn; 602 uint32_t reserved7; 603} __packed; 604 605struct iwn4965_node_info { 606 uint8_t control; 607 uint8_t reserved1[3]; 608 uint8_t macaddr[IEEE80211_ADDR_LEN]; 609 uint16_t reserved2; 610 uint8_t id; 611 uint8_t flags; 612 uint16_t reserved3; 613 uint16_t kflags; 614 uint8_t tsc2; /* TKIP TSC2 */ 615 uint8_t reserved4; 616 uint16_t ttak[5]; 617 uint8_t kid; 618 uint8_t reserved5; 619 uint8_t key[16]; 620 uint32_t htflags; 621 uint32_t mask; 622 uint16_t disable_tid; 623 uint16_t reserved6; 624 uint8_t addba_tid; 625 uint8_t delba_tid; 626 uint16_t addba_ssn; 627 uint32_t reserved7; 628} __packed; 629 630#define IWN_RFLAG_CCK (1 << 1) 631#define IWN_RFLAG_ANT(x) ((x) << 6) 632 633/* Structure for command IWN_CMD_TX_DATA. */ 634struct iwn_cmd_data { 635 uint16_t len; 636 uint16_t lnext; 637 uint32_t flags; 638#define IWN_TX_NEED_PROTECTION (1 << 0) /* 5000 only */ 639#define IWN_TX_NEED_RTS (1 << 1) 640#define IWN_TX_NEED_CTS (1 << 2) 641#define IWN_TX_NEED_ACK (1 << 3) 642#define IWN_TX_LINKQ (1 << 4) 643#define IWN_TX_IMM_BA (1 << 6) 644#define IWN_TX_FULL_TXOP (1 << 7) 645#define IWN_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */ 646#define IWN_TX_AUTO_SEQ (1 << 13) 647#define IWN_TX_MORE_FRAG (1 << 14) 648#define IWN_TX_INSERT_TSTAMP (1 << 16) 649#define IWN_TX_NEED_PADDING (1 << 20) 650 651 uint32_t scratch; 652 uint8_t plcp; 653 uint8_t rflags; 654 uint16_t xrflags; 655 656 uint8_t id; 657 uint8_t security; 658#define IWN_CIPHER_WEP40 1 659#define IWN_CIPHER_CCMP 2 660#define IWN_CIPHER_TKIP 3 661#define IWN_CIPHER_WEP104 9 662 663 uint8_t linkq; 664 uint8_t reserved2; 665 uint8_t key[16]; 666 uint16_t fnext; 667 uint16_t reserved3; 668 uint32_t lifetime; 669#define IWN_LIFETIME_INFINITE 0xffffffff 670 671 uint32_t loaddr; 672 uint8_t hiaddr; 673 uint8_t rts_ntries; 674 uint8_t data_ntries; 675 uint8_t tid; 676 uint16_t timeout; 677 uint16_t txop; 678} __packed; 679 680/* Structure for command IWN_CMD_LINK_QUALITY. */ 681#define IWN_MAX_TX_RETRIES 16 682struct iwn_cmd_link_quality { 683 uint8_t id; 684 uint8_t reserved1; 685 uint16_t ctl; 686 uint8_t flags; 687 uint8_t mimo; 688 uint8_t antmsk_1stream; 689 uint8_t antmsk_2stream; 690 uint8_t ridx[EDCA_NUM_AC]; 691 uint16_t ampdu_limit; 692 uint8_t ampdu_threshold; 693 uint8_t ampdu_max; 694 uint32_t reserved2; 695 struct { 696 uint8_t plcp; 697 uint8_t rflags; 698 uint16_t xrflags; 699 } __packed retry[IWN_MAX_TX_RETRIES]; 700 uint32_t reserved3; 701} __packed; 702 703/* Structure for command IWN_CMD_SET_LED. */ 704struct iwn_cmd_led { 705 uint32_t unit; /* multiplier (in usecs) */ 706 uint8_t which; 707#define IWN_LED_ACTIVITY 1 708#define IWN_LED_LINK 2 709 710 uint8_t off; 711 uint8_t on; 712 uint8_t reserved; 713} __packed; 714 715/* Structure for command IWN5000_CMD_WIMAX_COEX. */ 716struct iwn5000_wimax_coex { 717 uint32_t flags; 718#define IWN_WIMAX_COEX_STA_TABLE_VALID (1 << 0) 719#define IWN_WIMAX_COEX_UNASSOC_WA_UNMASK (1 << 2) 720#define IWN_WIMAX_COEX_ASSOC_WA_UNMASK (1 << 3) 721#define IWN_WIMAX_COEX_ENABLE (1 << 7) 722 723 struct iwn5000_wimax_event { 724 uint8_t request; 725 uint8_t window; 726 uint8_t reserved; 727 uint8_t flags; 728 } __packed events[16]; 729} __packed; 730 731/* Structures for command IWN5000_CMD_CALIB_CONFIG. */ 732struct iwn5000_calib_elem { 733 uint32_t enable; 734 uint32_t start; 735#define IWN5000_CALIB_DC (1 << 1) 736 uint32_t send; 737 uint32_t apply; 738 uint32_t reserved; 739} __packed; 740 741struct iwn5000_calib_status { 742 struct iwn5000_calib_elem once; 743 struct iwn5000_calib_elem perd; 744 uint32_t flags; 745} __packed; 746 747struct iwn5000_calib_config { 748 struct iwn5000_calib_status ucode; 749 struct iwn5000_calib_status driver; 750 uint32_t reserved; 751} __packed; 752 753/* Structure for command IWN_CMD_SET_POWER_MODE. */ 754struct iwn_pmgt_cmd { 755 uint16_t flags; 756#define IWN_PS_ALLOW_SLEEP (1 << 0) 757#define IWN_PS_NOTIFY (1 << 1) 758#define IWN_PS_SLEEP_OVER_DTIM (1 << 2) 759#define IWN_PS_PCI_PMGT (1 << 3) 760#define IWN_PS_FAST_PD (1 << 4) 761 762 uint8_t keepalive; 763 uint8_t debug; 764 uint32_t rxtimeout; 765 uint32_t txtimeout; 766 uint32_t intval[5]; 767 uint32_t beacons; 768} __packed; 769 770/* Structures for command IWN_CMD_SCAN. */ 771struct iwn_scan_essid { 772 uint8_t id; 773 uint8_t len; 774 uint8_t data[IEEE80211_NWID_LEN]; 775} __packed; 776 777struct iwn_scan_hdr { 778 uint16_t len; 779 uint8_t reserved1; 780 uint8_t nchan; 781 uint16_t quiet_time; 782 uint16_t quiet_threshold; 783 uint16_t crc_threshold; 784 uint16_t rxchain; 785 uint32_t max_svc; /* background scans */ 786 uint32_t pause_svc; /* background scans */ 787 uint32_t flags; 788 uint32_t filter; 789 790 /* Followed by a struct iwn_cmd_data. */ 791 /* Followed by an array of 20 structs iwn_scan_essid. */ 792 /* Followed by probe request body. */ 793 /* Followed by an array of ``nchan'' structs iwn_scan_chan. */ 794} __packed; 795 796struct iwn_scan_chan { 797 uint32_t flags; 798#define IWN_CHAN_ACTIVE (1 << 0) 799#define IWN_CHAN_NPBREQS(x) (((1 << (x)) - 1) << 1) 800 801 uint16_t chan; 802 uint8_t rf_gain; 803 uint8_t dsp_gain; 804 uint16_t active; /* msecs */ 805 uint16_t passive; /* msecs */ 806} __packed; 807 808/* Maximum size of a scan command. */ 809#define IWN_SCAN_MAXSZ (MCLBYTES - 4) 810 811/* Structure for command IWN_CMD_TXPOWER (4965AGN only.) */ 812#define IWN_RIDX_MAX 32 813struct iwn4965_cmd_txpower { 814 uint8_t band; 815 uint8_t reserved1; 816 uint8_t chan; 817 uint8_t reserved2; 818 struct { 819 uint8_t rf_gain[2]; 820 uint8_t dsp_gain[2]; 821 } __packed power[IWN_RIDX_MAX + 1]; 822} __packed; 823 824/* Structure for command IWN_CMD_TXPOWER_DBM (5000 Series only.) */ 825struct iwn5000_cmd_txpower { 826 int8_t global_limit; /* in half-dBm */ 827#define IWN5000_TXPOWER_AUTO 0x7f 828#define IWN5000_TXPOWER_MAX_DBM 16 829 830 uint8_t flags; 831#define IWN5000_TXPOWER_NO_CLOSED (1 << 6) 832 833 int8_t srv_limit; /* in half-dBm */ 834 uint8_t reserved; 835} __packed; 836 837/* Structure for command IWN_CMD_BLUETOOTH. */ 838struct iwn_bluetooth { 839 uint8_t flags; 840#define IWN_BT_COEX_CHAN_ANN (1 << 0) 841#define IWN_BT_COEX_BT_PRIO (1 << 1) 842#define IWN_BT_COEX_2_WIRE (1 << 2) 843 844 uint8_t lead_time; 845#define IWN_BT_LEAD_TIME_DEF 30 846 847 uint8_t max_kill; 848#define IWN_BT_MAX_KILL_DEF 5 849 850 uint8_t reserved; 851 uint32_t kill_ack; 852 uint32_t kill_cts; 853} __packed; 854 855/* Structure for command IWN_CMD_SET_CRITICAL_TEMP. */ 856struct iwn_critical_temp { 857 uint32_t reserved; 858 uint32_t tempM; 859 uint32_t tempR; 860/* degK <-> degC conversion macros. */ 861#define IWN_CTOK(c) ((c) + 273) 862#define IWN_KTOC(k) ((k) - 273) 863#define IWN_CTOMUK(c) (((c) * 1000000) + 273150000) 864} __packed; 865 866/* Structures for command IWN_CMD_SET_SENSITIVITY. */ 867struct iwn_sensitivity_cmd { 868 uint16_t which; 869#define IWN_SENSITIVITY_DEFAULTTBL 0 870#define IWN_SENSITIVITY_WORKTBL 1 871 872 uint16_t energy_cck; 873 uint16_t energy_ofdm; 874 uint16_t corr_ofdm_x1; 875 uint16_t corr_ofdm_mrc_x1; 876 uint16_t corr_cck_mrc_x4; 877 uint16_t corr_ofdm_x4; 878 uint16_t corr_ofdm_mrc_x4; 879 uint16_t corr_barker; 880 uint16_t corr_barker_mrc; 881 uint16_t corr_cck_x4; 882 uint16_t energy_ofdm_th; 883} __packed; 884 885struct iwn_enhanced_sensitivity_cmd { 886 uint16_t which; 887 uint16_t energy_cck; 888 uint16_t energy_ofdm; 889 uint16_t corr_ofdm_x1; 890 uint16_t corr_ofdm_mrc_x1; 891 uint16_t corr_cck_mrc_x4; 892 uint16_t corr_ofdm_x4; 893 uint16_t corr_ofdm_mrc_x4; 894 uint16_t corr_barker; 895 uint16_t corr_barker_mrc; 896 uint16_t corr_cck_x4; 897 uint16_t energy_ofdm_th; 898 /* "Enhanced" part. */ 899 uint16_t ina_det_ofdm; 900 uint16_t ina_det_cck; 901 uint16_t corr_11_9_en; 902 uint16_t ofdm_det_slope_mrc; 903 uint16_t ofdm_det_icept_mrc; 904 uint16_t ofdm_det_slope; 905 uint16_t ofdm_det_icept; 906 uint16_t cck_det_slope_mrc; 907 uint16_t cck_det_icept_mrc; 908 uint16_t cck_det_slope; 909 uint16_t cck_det_icept; 910 uint16_t reserved; 911} __packed; 912 913/* Structures for command IWN_CMD_PHY_CALIB. */ 914struct iwn_phy_calib { 915 uint8_t code; 916#define IWN4965_PHY_CALIB_DIFF_GAIN 7 917#define IWN5000_PHY_CALIB_DC 8 918#define IWN5000_PHY_CALIB_LO 9 919#define IWN5000_PHY_CALIB_TX_IQ 11 920#define IWN5000_PHY_CALIB_CRYSTAL 15 921#define IWN5000_PHY_CALIB_BASE_BAND 16 922#define IWN5000_PHY_CALIB_TX_IQ_PERIODIC 17 923#define IWN5000_PHY_CALIB_TEMP_OFFSET 18 924 925#define IWN5000_PHY_CALIB_RESET_NOISE_GAIN 18 926#define IWN5000_PHY_CALIB_NOISE_GAIN 19 927 928 uint8_t group; 929 uint8_t ngroups; 930 uint8_t isvalid; 931} __packed; 932 933struct iwn5000_phy_calib_crystal { 934 uint8_t code; 935 uint8_t group; 936 uint8_t ngroups; 937 uint8_t isvalid; 938 939 uint8_t cap_pin[2]; 940 uint8_t reserved[2]; 941} __packed; 942 943struct iwn5000_phy_calib_temp_offset { 944 uint8_t code; 945 uint8_t group; 946 uint8_t ngroups; 947 uint8_t isvalid; 948 int16_t offset; 949#define IWN_DEFAULT_TEMP_OFFSET 2700 950 951 uint16_t reserved; 952} __packed; 953 954struct iwn_phy_calib_gain { 955 uint8_t code; 956 uint8_t group; 957 uint8_t ngroups; 958 uint8_t isvalid; 959 960 int8_t gain[3]; 961 uint8_t reserved; 962} __packed; 963 964/* Structure for command IWN_CMD_SPECTRUM_MEASUREMENT. */ 965struct iwn_spectrum_cmd { 966 uint16_t len; 967 uint8_t token; 968 uint8_t id; 969 uint8_t origin; 970 uint8_t periodic; 971 uint16_t timeout; 972 uint32_t start; 973 uint32_t reserved1; 974 uint32_t flags; 975 uint32_t filter; 976 uint16_t nchan; 977 uint16_t reserved2; 978 struct { 979 uint32_t duration; 980 uint8_t chan; 981 uint8_t type; 982#define IWN_MEASUREMENT_BASIC (1 << 0) 983#define IWN_MEASUREMENT_CCA (1 << 1) 984#define IWN_MEASUREMENT_RPI_HISTOGRAM (1 << 2) 985#define IWN_MEASUREMENT_NOISE_HISTOGRAM (1 << 3) 986#define IWN_MEASUREMENT_FRAME (1 << 4) 987#define IWN_MEASUREMENT_IDLE (1 << 7) 988 989 uint16_t reserved; 990 } __packed chan[10]; 991} __packed; 992 993/* Structure for IWN_UC_READY notification. */ 994#define IWN_NATTEN_GROUPS 5 995struct iwn_ucode_info { 996 uint8_t minor; 997 uint8_t major; 998 uint16_t reserved1; 999 uint8_t revision[8]; 1000 uint8_t type; 1001 uint8_t subtype; 1002#define IWN_UCODE_RUNTIME 0 1003#define IWN_UCODE_INIT 9 1004 1005 uint16_t reserved2; 1006 uint32_t logptr; 1007 uint32_t errptr; 1008 uint32_t tstamp; 1009 uint32_t valid; 1010 1011 /* The following fields are for UCODE_INIT only. */ 1012 int32_t volt; 1013 struct { 1014 int32_t chan20MHz; 1015 int32_t chan40MHz; 1016 } __packed temp[4]; 1017 int32_t atten[IWN_NATTEN_GROUPS][2]; 1018} __packed; 1019 1020/* Structures for IWN_TX_DONE notification. */ 1021struct iwn4965_tx_stat { 1022 uint8_t nframes; 1023 uint8_t btkillcnt; 1024 uint8_t rtsfailcnt; 1025 uint8_t ackfailcnt; 1026 uint8_t rate; 1027 uint8_t rflags; 1028 uint16_t xrflags; 1029 uint16_t duration; 1030 uint16_t reserved; 1031 uint32_t power[2]; 1032 uint32_t status; 1033} __packed; 1034 1035struct iwn5000_tx_stat { 1036 uint8_t nframes; 1037 uint8_t btkillcnt; 1038 uint8_t rtsfailcnt; 1039 uint8_t ackfailcnt; 1040 uint8_t rate; 1041 uint8_t rflags; 1042 uint16_t xrflags; 1043 uint16_t duration; 1044 uint16_t reserved; 1045 uint32_t power[2]; 1046 uint32_t info; 1047 uint16_t seq; 1048 uint16_t len; 1049 uint8_t tlc; 1050 uint8_t ratid; 1051 uint8_t fc[2]; 1052 uint16_t status; 1053 uint16_t sequence; 1054} __packed; 1055 1056/* Structure for IWN_BEACON_MISSED notification. */ 1057struct iwn_beacon_missed { 1058 uint32_t consecutive; 1059 uint32_t total; 1060 uint32_t expected; 1061 uint32_t received; 1062} __packed; 1063 1064/* Structure for IWN_MPDU_RX_DONE notification. */ 1065struct iwn_rx_mpdu { 1066 uint16_t len; 1067 uint16_t reserved; 1068} __packed; 1069 1070/* Structures for IWN_RX_DONE and IWN_MPDU_RX_DONE notifications. */ 1071struct iwn4965_rx_phystat { 1072 uint16_t antenna; 1073 uint16_t agc; 1074 uint8_t rssi[6]; 1075} __packed; 1076 1077struct iwn5000_rx_phystat { 1078 uint32_t reserved1; 1079 uint32_t agc; 1080 uint16_t rssi[3]; 1081} __packed; 1082 1083struct iwn_rx_stat { 1084 uint8_t phy_len; 1085 uint8_t cfg_phy_len; 1086#define IWN_STAT_MAXLEN 20 1087 1088 uint8_t id; 1089 uint8_t reserved1; 1090 uint64_t tstamp; 1091 uint32_t beacon; 1092 uint16_t flags; 1093#define IWN_STAT_FLAG_SHPREAMBLE (1 << 2) 1094 1095 uint16_t chan; 1096 uint8_t phybuf[32]; 1097 uint8_t rate; 1098 uint8_t rflags; 1099 uint16_t xrflags; 1100 uint16_t len; 1101 uint16_t reserve3; 1102} __packed; 1103 1104#define IWN_RSSI_TO_DBM 44 1105 1106/* Structure for IWN_RX_COMPRESSED_BA notification. */ 1107struct iwn_compressed_ba { 1108 uint8_t macaddr[IEEE80211_ADDR_LEN]; 1109 uint16_t reserved; 1110 uint8_t id; 1111 uint8_t tid; 1112 uint16_t seq; 1113 uint64_t bitmap; 1114 uint16_t qid; 1115 uint16_t ssn; 1116} __packed; 1117 1118/* Structure for IWN_START_SCAN notification. */ 1119struct iwn_start_scan { 1120 uint64_t tstamp; 1121 uint32_t tbeacon; 1122 uint8_t chan; 1123 uint8_t band; 1124 uint16_t reserved; 1125 uint32_t status; 1126} __packed; 1127 1128/* Structure for IWN_STOP_SCAN notification. */ 1129struct iwn_stop_scan { 1130 uint8_t nchan; 1131 uint8_t status; 1132 uint8_t reserved; 1133 uint8_t chan; 1134 uint64_t tsf; 1135} __packed; 1136 1137/* Structure for IWN_SPECTRUM_MEASUREMENT notification. */ 1138struct iwn_spectrum_notif { 1139 uint8_t id; 1140 uint8_t token; 1141 uint8_t idx; 1142 uint8_t state; 1143#define IWN_MEASUREMENT_START 0 1144#define IWN_MEASUREMENT_STOP 1 1145 1146 uint32_t start; 1147 uint8_t band; 1148 uint8_t chan; 1149 uint8_t type; 1150 uint8_t reserved1; 1151 uint32_t cca_ofdm; 1152 uint32_t cca_cck; 1153 uint32_t cca_time; 1154 uint8_t basic; 1155 uint8_t reserved2[3]; 1156 uint32_t ofdm[8]; 1157 uint32_t cck[8]; 1158 uint32_t stop; 1159 uint32_t status; 1160#define IWN_MEASUREMENT_OK 0 1161#define IWN_MEASUREMENT_CONCURRENT 1 1162#define IWN_MEASUREMENT_CSA_CONFLICT 2 1163#define IWN_MEASUREMENT_TGH_CONFLICT 3 1164#define IWN_MEASUREMENT_STOPPED 6 1165#define IWN_MEASUREMENT_TIMEOUT 7 1166#define IWN_MEASUREMENT_FAILED 8 1167} __packed; 1168 1169/* Structures for IWN_{RX,BEACON}_STATISTICS notification. */ 1170struct iwn_rx_phy_stats { 1171 uint32_t ina; 1172 uint32_t fina; 1173 uint32_t bad_plcp; 1174 uint32_t bad_crc32; 1175 uint32_t overrun; 1176 uint32_t eoverrun; 1177 uint32_t good_crc32; 1178 uint32_t fa; 1179 uint32_t bad_fina_sync; 1180 uint32_t sfd_timeout; 1181 uint32_t fina_timeout; 1182 uint32_t no_rts_ack; 1183 uint32_t rxe_limit; 1184 uint32_t ack; 1185 uint32_t cts; 1186 uint32_t ba_resp; 1187 uint32_t dsp_kill; 1188 uint32_t bad_mh; 1189 uint32_t rssi_sum; 1190 uint32_t reserved; 1191} __packed; 1192 1193struct iwn_rx_general_stats { 1194 uint32_t bad_cts; 1195 uint32_t bad_ack; 1196 uint32_t not_bss; 1197 uint32_t filtered; 1198 uint32_t bad_chan; 1199 uint32_t beacons; 1200 uint32_t missed_beacons; 1201 uint32_t adc_saturated; /* time in 0.8us */ 1202 uint32_t ina_searched; /* time in 0.8us */ 1203 uint32_t noise[3]; 1204 uint32_t flags; 1205 uint32_t load; 1206 uint32_t fa; 1207 uint32_t rssi[3]; 1208 uint32_t energy[3]; 1209} __packed; 1210 1211struct iwn_rx_ht_phy_stats { 1212 uint32_t bad_plcp; 1213 uint32_t overrun; 1214 uint32_t eoverrun; 1215 uint32_t good_crc32; 1216 uint32_t bad_crc32; 1217 uint32_t bad_mh; 1218 uint32_t good_ampdu_crc32; 1219 uint32_t ampdu; 1220 uint32_t fragment; 1221 uint32_t reserved; 1222} __packed; 1223 1224struct iwn_rx_stats { 1225 struct iwn_rx_phy_stats ofdm; 1226 struct iwn_rx_phy_stats cck; 1227 struct iwn_rx_general_stats general; 1228 struct iwn_rx_ht_phy_stats ht; 1229} __packed; 1230 1231struct iwn_tx_stats { 1232 uint32_t preamble; 1233 uint32_t rx_detected; 1234 uint32_t bt_defer; 1235 uint32_t bt_kill; 1236 uint32_t short_len; 1237 uint32_t cts_timeout; 1238 uint32_t ack_timeout; 1239 uint32_t exp_ack; 1240 uint32_t ack; 1241 uint32_t msdu; 1242 uint32_t busrt_err1; 1243 uint32_t burst_err2; 1244 uint32_t cts_collision; 1245 uint32_t ack_collision; 1246 uint32_t ba_timeout; 1247 uint32_t ba_resched; 1248 uint32_t query_ampdu; 1249 uint32_t query; 1250 uint32_t query_ampdu_frag; 1251 uint32_t query_mismatch; 1252 uint32_t not_ready; 1253 uint32_t underrun; 1254 uint32_t bt_ht_kill; 1255 uint32_t rx_ba_resp; 1256 uint32_t reserved[2]; 1257} __packed; 1258 1259struct iwn_general_stats { 1260 uint32_t temp; 1261 uint32_t temp_m; 1262 uint32_t burst_check; 1263 uint32_t burst; 1264 uint32_t reserved1[4]; 1265 uint32_t sleep; 1266 uint32_t slot_out; 1267 uint32_t slot_idle; 1268 uint32_t ttl_tstamp; 1269 uint32_t tx_ant_a; 1270 uint32_t tx_ant_b; 1271 uint32_t exec; 1272 uint32_t probe; 1273 uint32_t reserved2[2]; 1274 uint32_t rx_enabled; 1275 uint32_t reserved3[3]; 1276} __packed; 1277 1278struct iwn_stats { 1279 uint32_t flags; 1280 struct iwn_rx_stats rx; 1281 struct iwn_tx_stats tx; 1282 struct iwn_general_stats general; 1283} __packed; 1284 1285 1286/* Firmware error dump. */ 1287struct iwn_fw_dump { 1288 uint32_t valid; 1289 uint32_t id; 1290 uint32_t pc; 1291 uint32_t branch_link[2]; 1292 uint32_t interrupt_link[2]; 1293 uint32_t error_data[2]; 1294 uint32_t src_line; 1295 uint32_t tsf; 1296 uint32_t time[2]; 1297} __packed; 1298 1299/* TLV firmware header. */ 1300struct iwn_fw_tlv_hdr { 1301 uint32_t zero; /* Always 0, to differentiate from legacy. */ 1302 uint32_t signature; 1303#define IWN_FW_SIGNATURE 0x0a4c5749 /* "IWL\n" */ 1304 1305 uint8_t descr[64]; 1306 uint32_t rev; 1307#define IWN_FW_API(x) (((x) >> 8) & 0xff) 1308 1309 uint32_t build; 1310 uint64_t altmask; 1311} __packed; 1312 1313/* TLV header. */ 1314struct iwn_fw_tlv { 1315 uint16_t type; 1316#define IWN_FW_TLV_MAIN_TEXT 1 1317#define IWN_FW_TLV_MAIN_DATA 2 1318#define IWN_FW_TLV_INIT_TEXT 3 1319#define IWN_FW_TLV_INIT_DATA 4 1320#define IWN_FW_TLV_BOOT_TEXT 5 1321#define IWN_FW_TLV_PBREQ_MAXLEN 6 1322 1323 uint16_t alt; 1324 uint32_t len; 1325} __packed; 1326 1327#define IWN4965_FW_TEXT_MAXSZ ( 96 * 1024) 1328#define IWN4965_FW_DATA_MAXSZ ( 40 * 1024) 1329#define IWN5000_FW_TEXT_MAXSZ (256 * 1024) 1330#define IWN5000_FW_DATA_MAXSZ ( 80 * 1024) 1331#define IWN_FW_BOOT_TEXT_MAXSZ 1024 1332#define IWN4965_FWSZ (IWN4965_FW_TEXT_MAXSZ + IWN4965_FW_DATA_MAXSZ) 1333#define IWN5000_FWSZ IWN5000_FW_TEXT_MAXSZ 1334 1335/* 1336 * Offsets into EEPROM. 1337 */ 1338#define IWN_EEPROM_MAC 0x015 1339#define IWN_EEPROM_SKU_CAP 0x045 1340#define IWN_EEPROM_RFCFG 0x048 1341#define IWN4965_EEPROM_DOMAIN 0x060 1342#define IWN4965_EEPROM_BAND1 0x063 1343#define IWN5000_EEPROM_REG 0x066 1344#define IWN5000_EEPROM_CAL 0x067 1345#define IWN4965_EEPROM_BAND2 0x072 1346#define IWN4965_EEPROM_BAND3 0x080 1347#define IWN4965_EEPROM_BAND4 0x08d 1348#define IWN4965_EEPROM_BAND5 0x099 1349#define IWN4965_EEPROM_BAND6 0x0a0 1350#define IWN4965_EEPROM_BAND7 0x0a8 1351#define IWN4965_EEPROM_MAXPOW 0x0e8 1352#define IWN4965_EEPROM_VOLTAGE 0x0e9 1353#define IWN4965_EEPROM_BANDS 0x0ea 1354/* Indirect offsets. */ 1355#define IWN5000_EEPROM_DOMAIN 0x001 1356#define IWN5000_EEPROM_BAND1 0x004 1357#define IWN5000_EEPROM_BAND2 0x013 1358#define IWN5000_EEPROM_BAND3 0x021 1359#define IWN5000_EEPROM_BAND4 0x02e 1360#define IWN5000_EEPROM_BAND5 0x03a 1361#define IWN5000_EEPROM_BAND6 0x041 1362#define IWN5000_EEPROM_BAND7 0x049 1363#define IWN6000_EEPROM_ENHINFO 0x054 1364#define IWN5000_EEPROM_CRYSTAL 0x128 1365#define IWN5000_EEPROM_TEMP 0x12a 1366#define IWN5000_EEPROM_VOLT 0x12b 1367 1368/* Possible flags for IWN_EEPROM_SKU_CAP. */ 1369#define IWN_EEPROM_SKU_CAP_11N (1 << 6) 1370#define IWN_EEPROM_SKU_CAP_AMT (1 << 7) 1371#define IWN_EEPROM_SKU_CAP_IPAN (1 << 8) 1372 1373/* Possible flags for IWN_EEPROM_RFCFG. */ 1374#define IWN_RFCFG_TYPE(x) (((x) >> 0) & 0x3) 1375#define IWN_RFCFG_STEP(x) (((x) >> 2) & 0x3) 1376#define IWN_RFCFG_DASH(x) (((x) >> 4) & 0x3) 1377#define IWN_RFCFG_TXANTMSK(x) (((x) >> 8) & 0xf) 1378#define IWN_RFCFG_RXANTMSK(x) (((x) >> 12) & 0xf) 1379 1380struct iwn_eeprom_chan { 1381 uint8_t flags; 1382#define IWN_EEPROM_CHAN_VALID (1 << 0) 1383#define IWN_EEPROM_CHAN_IBSS (1 << 1) 1384#define IWN_EEPROM_CHAN_ACTIVE (1 << 3) 1385#define IWN_EEPROM_CHAN_RADAR (1 << 4) 1386 1387 int8_t maxpwr; 1388} __packed; 1389 1390struct iwn_eeprom_enhinfo { 1391 uint16_t chan; 1392 int8_t chain[3]; /* max power in half-dBm */ 1393 uint8_t reserved; 1394 int8_t mimo2; /* max power in half-dBm */ 1395 int8_t mimo3; /* max power in half-dBm */ 1396} __packed; 1397 1398struct iwn5000_eeprom_calib_hdr { 1399 uint8_t version; 1400 uint8_t pa_type; 1401 uint16_t volt; 1402} __packed; 1403 1404#define IWN_NSAMPLES 3 1405struct iwn4965_eeprom_chan_samples { 1406 uint8_t num; 1407 struct { 1408 uint8_t temp; 1409 uint8_t gain; 1410 uint8_t power; 1411 int8_t pa_det; 1412 } samples[2][IWN_NSAMPLES]; 1413} __packed; 1414 1415#define IWN_NBANDS 8 1416struct iwn4965_eeprom_band { 1417 uint8_t lo; /* low channel number */ 1418 uint8_t hi; /* high channel number */ 1419 struct iwn4965_eeprom_chan_samples chans[2]; 1420} __packed; 1421 1422/* 1423 * Offsets of channels descriptions in EEPROM. 1424 */ 1425static const uint32_t iwn4965_regulatory_bands[IWN_NBANDS] = { 1426 IWN4965_EEPROM_BAND1, 1427 IWN4965_EEPROM_BAND2, 1428 IWN4965_EEPROM_BAND3, 1429 IWN4965_EEPROM_BAND4, 1430 IWN4965_EEPROM_BAND5, 1431 IWN4965_EEPROM_BAND6, 1432 IWN4965_EEPROM_BAND7 1433}; 1434 1435static const uint32_t iwn5000_regulatory_bands[IWN_NBANDS] = { 1436 IWN5000_EEPROM_BAND1, 1437 IWN5000_EEPROM_BAND2, 1438 IWN5000_EEPROM_BAND3, 1439 IWN5000_EEPROM_BAND4, 1440 IWN5000_EEPROM_BAND5, 1441 IWN5000_EEPROM_BAND6, 1442 IWN5000_EEPROM_BAND7 1443}; 1444 1445#define IWN_CHAN_BANDS_COUNT 7 1446#define IWN_MAX_CHAN_PER_BAND 14 1447static const struct iwn_chan_band { 1448 uint8_t nchan; 1449 uint8_t chan[IWN_MAX_CHAN_PER_BAND]; 1450} iwn_bands[] = { 1451 /* 20MHz channels, 2GHz band. */ 1452 { 14, { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 } }, 1453 /* 20MHz channels, 5GHz band. */ 1454 { 13, { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 } }, 1455 { 12, { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 } }, 1456 { 11, { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } }, 1457 { 6, { 145, 149, 153, 157, 161, 165 } }, 1458 /* 40MHz channels (primary channels), 2GHz band. */ 1459 { 7, { 1, 2, 3, 4, 5, 6, 7 } }, 1460 /* 40MHz channels (primary channels), 5GHz band. */ 1461 { 11, { 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157 } } 1462}; 1463 1464#define IWN1000_OTP_NBLOCKS 3 1465#define IWN6000_OTP_NBLOCKS 4 1466#define IWN6050_OTP_NBLOCKS 7 1467 1468/* HW rate indices. */ 1469#define IWN_RIDX_CCK1 0 1470#define IWN_RIDX_OFDM6 4 1471 1472static const struct iwn_rate { 1473 uint8_t rate; 1474 uint8_t plcp; 1475 uint8_t flags; 1476} iwn_rates[IWN_RIDX_MAX + 1] = { 1477 { 2, 10, IWN_RFLAG_CCK }, 1478 { 4, 20, IWN_RFLAG_CCK }, 1479 { 11, 55, IWN_RFLAG_CCK }, 1480 { 22, 110, IWN_RFLAG_CCK }, 1481 { 12, 0xd, 0 }, 1482 { 18, 0xf, 0 }, 1483 { 24, 0x5, 0 }, 1484 { 36, 0x7, 0 }, 1485 { 48, 0x9, 0 }, 1486 { 72, 0xb, 0 }, 1487 { 96, 0x1, 0 }, 1488 { 108, 0x3, 0 }, 1489 { 120, 0x3, 0 } 1490}; 1491 1492#define IWN4965_MAX_PWR_INDEX 107 1493 1494/* 1495 * RF Tx gain values from highest to lowest power (values obtained from 1496 * the reference driver.) 1497 */ 1498static const uint8_t iwn4965_rf_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1499 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c, 1500 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 0x39, 0x38, 1501 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 0x35, 0x35, 1502 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x31, 0x31, 1503 0x31, 0x30, 0x30, 0x30, 0x06, 0x06, 0x06, 0x05, 0x05, 0x05, 0x04, 1504 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01, 1505 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1506 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1507 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1508 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1509}; 1510 1511static const uint8_t iwn4965_rf_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1512 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 1513 0x3c, 0x3c, 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 1514 0x39, 0x38, 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 1515 0x35, 0x35, 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 1516 0x31, 0x31, 0x31, 0x30, 0x30, 0x30, 0x25, 0x25, 0x25, 0x24, 0x24, 1517 0x24, 0x23, 0x23, 0x23, 0x22, 0x18, 0x18, 0x17, 0x17, 0x17, 0x16, 1518 0x16, 0x16, 0x15, 0x15, 0x15, 0x14, 0x14, 0x14, 0x13, 0x13, 0x13, 1519 0x12, 0x08, 0x08, 0x07, 0x07, 0x07, 0x06, 0x06, 0x06, 0x05, 0x05, 1520 0x05, 0x04, 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 1521 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1522}; 1523 1524/* 1525 * DSP pre-DAC gain values from highest to lowest power (values obtained 1526 * from the reference driver.) 1527 */ 1528static const uint8_t iwn4965_dsp_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1529 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1530 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1531 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1532 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1533 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1534 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1535 0x6e, 0x68, 0x62, 0x61, 0x60, 0x5f, 0x5e, 0x5d, 0x5c, 0x5b, 0x5a, 1536 0x59, 0x58, 0x57, 0x56, 0x55, 0x54, 0x53, 0x52, 0x51, 0x50, 0x4f, 1537 0x4e, 0x4d, 0x4c, 0x4b, 0x4a, 0x49, 0x48, 0x47, 0x46, 0x45, 0x44, 1538 0x43, 0x42, 0x41, 0x40, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b 1539}; 1540 1541static const uint8_t iwn4965_dsp_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1542 0x7b, 0x75, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1543 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1544 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1545 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1546 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1547 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1548 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1549 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1550 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1551 0x68, 0x62, 0x6e, 0x68, 0x62, 0x5d, 0x58, 0x53, 0x4e 1552}; 1553 1554/* 1555 * Power saving settings (values obtained from the reference driver.) 1556 */ 1557#define IWN_NDTIMRANGES 3 1558#define IWN_NPOWERLEVELS 6 1559static const struct iwn_pmgt { 1560 uint32_t rxtimeout; 1561 uint32_t txtimeout; 1562 uint32_t intval[5]; 1563 int skip_dtim; 1564} iwn_pmgt[IWN_NDTIMRANGES][IWN_NPOWERLEVELS] = { 1565 /* DTIM <= 2 */ 1566 { 1567 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1568 { 200, 500, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 1 */ 1569 { 200, 300, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 2 */ 1570 { 50, 100, { 2, 2, 2, 2, -1 }, 0 }, /* PS level 3 */ 1571 { 50, 25, { 2, 2, 4, 4, -1 }, 1 }, /* PS level 4 */ 1572 { 25, 25, { 2, 2, 4, 6, -1 }, 2 } /* PS level 5 */ 1573 }, 1574 /* 3 <= DTIM <= 10 */ 1575 { 1576 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1577 { 200, 500, { 1, 2, 3, 4, 4 }, 0 }, /* PS level 1 */ 1578 { 200, 300, { 1, 2, 3, 4, 7 }, 0 }, /* PS level 2 */ 1579 { 50, 100, { 2, 4, 6, 7, 9 }, 0 }, /* PS level 3 */ 1580 { 50, 25, { 2, 4, 6, 9, 10 }, 1 }, /* PS level 4 */ 1581 { 25, 25, { 2, 4, 7, 10, 10 }, 2 } /* PS level 5 */ 1582 }, 1583 /* DTIM >= 11 */ 1584 { 1585 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1586 { 200, 500, { 1, 2, 3, 4, -1 }, 0 }, /* PS level 1 */ 1587 { 200, 300, { 2, 4, 6, 7, -1 }, 0 }, /* PS level 2 */ 1588 { 50, 100, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 3 */ 1589 { 50, 25, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 4 */ 1590 { 25, 25, { 4, 7, 10, 10, -1 }, 0 } /* PS level 5 */ 1591 } 1592}; 1593 1594struct iwn_sensitivity_limits { 1595 uint32_t min_ofdm_x1; 1596 uint32_t max_ofdm_x1; 1597 uint32_t min_ofdm_mrc_x1; 1598 uint32_t max_ofdm_mrc_x1; 1599 uint32_t min_ofdm_x4; 1600 uint32_t max_ofdm_x4; 1601 uint32_t min_ofdm_mrc_x4; 1602 uint32_t max_ofdm_mrc_x4; 1603 uint32_t min_cck_x4; 1604 uint32_t max_cck_x4; 1605 uint32_t min_cck_mrc_x4; 1606 uint32_t max_cck_mrc_x4; 1607 uint32_t min_energy_cck; 1608 uint32_t energy_cck; 1609 uint32_t energy_ofdm; 1610}; 1611 1612/* 1613 * RX sensitivity limits (values obtained from the reference driver.) 1614 */ 1615static const struct iwn_sensitivity_limits iwn4965_sensitivity_limits = { 1616 105, 140, 1617 220, 270, 1618 85, 120, 1619 170, 210, 1620 125, 200, 1621 200, 400, 1622 97, 1623 100, 1624 100 1625}; 1626 1627static const struct iwn_sensitivity_limits iwn5000_sensitivity_limits = { 1628 120, 120, /* min = max for performance bug in DSP. */ 1629 240, 240, /* min = max for performance bug in DSP. */ 1630 90, 120, 1631 170, 210, 1632 125, 200, 1633 170, 400, 1634 95, 1635 95, 1636 95 1637}; 1638 1639static const struct iwn_sensitivity_limits iwn5150_sensitivity_limits = { 1640 105, 105, /* min = max for performance bug in DSP. */ 1641 220, 220, /* min = max for performance bug in DSP. */ 1642 90, 120, 1643 170, 210, 1644 125, 200, 1645 170, 400, 1646 95, 1647 95, 1648 95 1649}; 1650 1651static const struct iwn_sensitivity_limits iwn1000_sensitivity_limits = { 1652 120, 155, 1653 240, 290, 1654 90, 120, 1655 170, 210, 1656 125, 200, 1657 170, 400, 1658 95, 1659 95, 1660 95 1661}; 1662 1663static const struct iwn_sensitivity_limits iwn6000_sensitivity_limits = { 1664 105, 110, 1665 192, 232, 1666 80, 145, 1667 128, 232, 1668 125, 175, 1669 160, 310, 1670 97, 1671 97, 1672 100 1673}; 1674 1675/* Map TID to TX scheduler's FIFO. */ 1676static const uint8_t iwn_tid2fifo[] = { 1677 1, 0, 0, 1, 2, 2, 3, 3, 7, 7, 7, 7, 7, 7, 7, 7, 3 1678}; 1679 1680/* WiFi/WiMAX coexist event priority table for 6050. */ 1681static const struct iwn5000_wimax_event iwn6050_wimax_events[] = { 1682 { 0x04, 0x03, 0x00, 0x00 }, 1683 { 0x04, 0x03, 0x00, 0x03 }, 1684 { 0x04, 0x03, 0x00, 0x03 }, 1685 { 0x04, 0x03, 0x00, 0x03 }, 1686 { 0x04, 0x03, 0x00, 0x00 }, 1687 { 0x04, 0x03, 0x00, 0x07 }, 1688 { 0x04, 0x03, 0x00, 0x00 }, 1689 { 0x04, 0x03, 0x00, 0x03 }, 1690 { 0x04, 0x03, 0x00, 0x03 }, 1691 { 0x04, 0x03, 0x00, 0x00 }, 1692 { 0x06, 0x03, 0x00, 0x07 }, 1693 { 0x04, 0x03, 0x00, 0x00 }, 1694 { 0x06, 0x06, 0x00, 0x03 }, 1695 { 0x04, 0x03, 0x00, 0x07 }, 1696 { 0x04, 0x03, 0x00, 0x00 }, 1697 { 0x04, 0x03, 0x00, 0x00 } 1698}; 1699 1700/* Firmware errors. */ 1701static const char * const iwn_fw_errmsg[] = { 1702 "OK", 1703 "FAIL", 1704 "BAD_PARAM", 1705 "BAD_CHECKSUM", 1706 "NMI_INTERRUPT_WDG", 1707 "SYSASSERT", 1708 "FATAL_ERROR", 1709 "BAD_COMMAND", 1710 "HW_ERROR_TUNE_LOCK", 1711 "HW_ERROR_TEMPERATURE", 1712 "ILLEGAL_CHAN_FREQ", 1713 "VCC_NOT_STABLE", 1714 "FH_ERROR", 1715 "NMI_INTERRUPT_HOST", 1716 "NMI_INTERRUPT_ACTION_PT", 1717 "NMI_INTERRUPT_UNKNOWN", 1718 "UCODE_VERSION_MISMATCH", 1719 "HW_ERROR_ABS_LOCK", 1720 "HW_ERROR_CAL_LOCK_FAIL", 1721 "NMI_INTERRUPT_INST_ACTION_PT", 1722 "NMI_INTERRUPT_DATA_ACTION_PT", 1723 "NMI_TRM_HW_ER", 1724 "NMI_INTERRUPT_TRM", 1725 "NMI_INTERRUPT_BREAKPOINT" 1726 "DEBUG_0", 1727 "DEBUG_1", 1728 "DEBUG_2", 1729 "DEBUG_3", 1730 "ADVANCED_SYSASSERT" 1731}; 1732 1733/* Find least significant bit that is set. */ 1734#define IWN_LSB(x) ((((x) - 1) & (x)) ^ (x)) 1735 1736#define IWN_READ(sc, reg) \ 1737 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 1738 1739#define IWN_WRITE(sc, reg, val) \ 1740 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 1741 1742#define IWN_WRITE_1(sc, reg, val) \ 1743 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 1744 1745#define IWN_SETBITS(sc, reg, mask) \ 1746 IWN_WRITE(sc, reg, IWN_READ(sc, reg) | (mask)) 1747 1748#define IWN_CLRBITS(sc, reg, mask) \ 1749 IWN_WRITE(sc, reg, IWN_READ(sc, reg) & ~(mask)) 1750 1751#define IWN_BARRIER_WRITE(sc) \ 1752 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 1753 BUS_SPACE_BARRIER_WRITE) 1754 1755#define IWN_BARRIER_READ_WRITE(sc) \ 1756 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 1757 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 1758 1759