1/* $NetBSD: auichreg.h,v 1.11 2008/01/14 21:33:04 martin Exp $ */ 2 3/* 4 * Copyright (c) 2000 Michael Shalayeff 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 22 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 23 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 26 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 27 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 28 * THE POSSIBILITY OF SUCH DAMAGE. 29 * 30 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 31 */ 32 33#ifndef _DEV_PCI_AUICHREG_H_ 34#define _DEV_PCI_AUICHREG_H_ 35 36/* 37 * AC'97 audio found on Intel 810/820/440MX chipsets. 38 * http://developer.intel.com/design/chipsets/datashts/290655.htm 39 * http://developer.intel.com/design/chipsets/manuals/298028.htm 40 */ 41 42/* 12.1.10 NAMBAR - native audio mixer base address register */ 43#define ICH_NAMBAR 0x10 44/* 12.1.11 NABMBAR - native audio bus mastering base address register */ 45#define ICH_NABMBAR 0x14 46#define ICH_MMBAR 0x18 /* ICH4/ICH5/ICH6/ICH7 native audio mixer BAR */ 47#define ICH_MBBAR 0x1c /* ICH4/ICH5/ICH6/ICH7 native bus mastering BAR */ 48#define ICH_CFG 0x40 49#define ICH_CFG_IOSE 0x0100 50 51/* table 12-3. native audio bus master control registers */ 52#define ICH_BDBAR 0x00 /* 8-byte aligned address */ 53#define ICH_CIV 0x04 /* 5 bits current index value */ 54#define ICH_LVI 0x05 /* 5 bits last valid index value */ 55#define ICH_LVI_MASK 0x1f 56#define ICH_STS 0x06 /* 16 bits status */ 57#define ICH_FIFOE 0x10 /* fifo error */ 58#define ICH_BCIS 0x08 /* r- buf cmplt int sts; wr ack */ 59#define ICH_LVBCI 0x04 /* r- last valid bci, wr ack */ 60#define ICH_CELV 0x02 /* current equals last valid */ 61#define ICH_DCH 0x01 /* DMA halted */ 62#define ICH_ISTS_BITS "\020\01dch\02celv\03lvbci\04bcis\05fifoe" 63#define ICH_PICB 0x08 /* 16 bits */ 64#define ICH_PIV 0x0a /* 5 bits prefetched index value */ 65#define ICH_CTRL 0x0b /* control */ 66#define ICH_IOCE 0x10 /* int on completion enable */ 67#define ICH_FEIE 0x08 /* fifo error int enable */ 68#define ICH_LVBIE 0x04 /* last valid buf int enable */ 69#define ICH_RR 0x02 /* 1 - reset regs */ 70#define ICH_RPBM 0x01 /* 1 - run, 0 - pause */ 71 72#define ICH_CODEC_OFFSET 0x80 73 74#define ICH_PCMI 0x00 75#define ICH_PCMO 0x10 76#define ICH_MICI 0x20 77 78#define ICH_GCTRL 0x2c 79#define ICH_SSM_78 0x40000000 /* S/PDIF slots 7 and 8 */ 80#define ICH_SSM_69 0x80000000 /* S/PDIF slots 6 and 9 */ 81#define ICH_SSM_1011 0xc0000000 /* S/PDIF slots 10 and 11 */ 82#define ICH_POM16 0x000000 /* PCM out precision 16bit */ 83#define ICH_POM20 0x400000 /* PCM out precision 20bit */ 84#define ICH_PCM246_MASK 0x300000 85#define ICH_PCM2 0x000000 /* 2ch output */ 86#define ICH_PCM4 0x100000 /* 4ch output */ 87#define ICH_PCM6 0x200000 /* 6ch output */ 88#define ICH_SIS_PCM246_MASK 0x0000c0 89#define ICH_SIS_PCM2 0x000000 /* 2ch output */ 90#define ICH_SIS_PCM4 0x000040 /* 4ch output */ 91#define ICH_SIS_PCM6 0x000080 /* 6ch output */ 92#define ICH_S2RIE 0x40 /* int when tertiary codec resume */ 93#define ICH_SRIE 0x20 /* int when 2ndary codec resume */ 94#define ICH_PRIE 0x10 /* int when primary codec resume */ 95#define ICH_ACLSO 0x08 /* aclink shut off */ 96#define ICH_WRESET 0x04 /* warm reset */ 97#define ICH_CRESET 0x02 /* cold reset */ 98#define ICH_GIE 0x01 /* gpi int enable */ 99#define ICH_GSTS 0x30 100#define ICH_S2RI 0x20000000 /* tertiary resume int */ 101#define ICH_S2CR 0x10000000 /* tertiary codec ready */ 102#define ICH_BCS 0x08000000 /* bit clock stopped */ 103#define ICH_SPINT 0x04000000 /* S/PDIF int */ 104#define ICH_P2INT 0x02000000 /* PCM-In 2 int */ 105#define ICH_M2INT 0x01000000 /* mic 2 int */ 106#define ICH_SAMPLE_CAP 0x00c00000 /* sampling precision capability */ 107#define ICH_CHAN_CAP 0x00300000 /* multi-channel capability */ 108#define ICH_MD3 0x20000 /* pwr-dn semaphore for modem */ 109#define ICH_AD3 0x10000 /* pwr-dn semaphore for audio */ 110#define ICH_RCS 0x08000 /* read completion status */ 111#define ICH_B3S12 0x04000 /* bit 3 of slot 12 */ 112#define ICH_B2S12 0x02000 /* bit 2 of slot 12 */ 113#define ICH_B1S12 0x01000 /* bit 1 of slot 12 */ 114#define ICH_SRI 0x00800 /* secondary resume int */ 115#define ICH_PRI 0x00400 /* primary resume int */ 116#define ICH_SCR 0x00200 /* secondary codec ready */ 117#define ICH_PCR 0x00100 /* primary codec ready */ 118#define ICH_MINT 0x00080 /* mic in int */ 119#define ICH_POINT 0x00040 /* pcm out int */ 120#define ICH_PIINT 0x00020 /* pcm in int */ 121#define ICH_MOINT 0x00004 /* modem out int */ 122#define ICH_MIINT 0x00002 /* modem in int */ 123#define ICH_GSCI 0x00001 /* gpi status change */ 124#define ICH_GSTS_BITS "\020\01gsci\02miict\03moint\06piint\07point\010mint\011pcr\012scr\013pri\014sri\015b1s12\016b2s12\017b3s12\020rcs\021ad3\022md3" 125#define ICH_CAS 0x34 /* 1/8 bit */ 126#define ICH_SEMATIMO 1000 /* us */ 127 128#define ICH_SIS_NV_CTL 0x4c /* some SiS/nVidia register. From Linux */ 129#define ICH_SIS_CTL_UNMUTE 0x01 /* un-mute the output */ 130 131/* 132 * according to the dev/audiovar.h AU_RING_SIZE is 2^16, what fits 133 * in our limits perfectly, i.e. setting it to higher value 134 * in your kernel config would improve perfomance, still 2^21 is the max 135 */ 136#define ICH_DMALIST_MAX 32 137#define ICH_DMASEG_MAX (65536*2) /* 64k samples, 2x16 bit samples */ 138struct auich_dmalist { 139 u_int32_t base; 140 u_int32_t len; 141#define ICH_DMAF_IOC 0x80000000 /* 1-int on complete */ 142#define ICH_DMAF_BUP 0x40000000 /* 0-retrans last, 1-transmit 0 */ 143}; 144 145#endif /* _DEV_PCI_AUICHREG_H_ */ 146