1/* $NetBSD: mvpex.c,v 1.5 2011/05/17 17:34:54 dyoung Exp $ */ 2/* 3 * Copyright (c) 2008 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__KERNEL_RCSID(0, "$NetBSD: mvpex.c,v 1.5 2011/05/17 17:34:54 dyoung Exp $"); 30 31#include "opt_pci.h" 32#include "pci.h" 33 34#include <sys/param.h> 35#include <sys/bus.h> 36#include <sys/device.h> 37#include <sys/errno.h> 38#include <sys/extent.h> 39#include <sys/evcnt.h> 40#include <sys/malloc.h> 41#include <sys/systm.h> 42 43#include <prop/proplib.h> 44 45#include <dev/pci/pcivar.h> 46#include <dev/pci/pcireg.h> 47#include <dev/pci/pciconf.h> 48 49#include <dev/marvell/mvpexreg.h> 50#include <dev/marvell/mvpexvar.h> 51#include <dev/marvell/marvellreg.h> 52#include <dev/marvell/marvellvar.h> 53 54#include <machine/pci_machdep.h> 55 56#include "locators.h" 57 58 59static int mvpex_match(device_t, struct cfdata *, void *); 60static void mvpex_attach(device_t, device_t, void *); 61 62static int mvpex_intr(void *); 63 64static void mvpex_init(struct mvpex_softc *); 65#if 0 /* shall move to pchb(4)? */ 66static void mvpex_barinit(struct mvpex_softc *); 67static int mvpex_wininit(struct mvpex_softc *, int, int, int, int, uint32_t *, 68 uint32_t *); 69#else 70static void mvpex_wininit(struct mvpex_softc *); 71#endif 72#if NPCI > 0 73static void mvpex_pci_config(struct mvpex_softc *, bus_space_tag_t, 74 bus_space_tag_t, bus_dma_tag_t, pci_chipset_tag_t, 75 u_long, u_long, u_long, u_long, int); 76#endif 77 78CFATTACH_DECL_NEW(mvpex_gt, sizeof(struct mvpex_softc), 79 mvpex_match, mvpex_attach, NULL, NULL); 80CFATTACH_DECL_NEW(mvpex_mbus, sizeof(struct mvpex_softc), 81 mvpex_match, mvpex_attach, NULL, NULL); 82 83 84/* ARGSUSED */ 85static int 86mvpex_match(device_t parent, struct cfdata *match, void *aux) 87{ 88 struct marvell_attach_args *mva = aux; 89 90 if (strcmp(mva->mva_name, match->cf_name) != 0) 91 return 0; 92 if (mva->mva_offset == MVA_OFFSET_DEFAULT || 93 mva->mva_irq == MVA_IRQ_DEFAULT) 94 return 0; 95 96 mva->mva_size = MVPEX_SIZE; 97 return 1; 98} 99 100/* ARGSUSED */ 101static void 102mvpex_attach(device_t parent, device_t self, void *aux) 103{ 104 struct mvpex_softc *sc = device_private(self); 105 struct marvell_attach_args *mva = aux; 106#if NPCI > 0 107 prop_dictionary_t dict = device_properties(self); 108 prop_object_t pc, iot, memt; 109 pci_chipset_tag_t mvpex_chipset; 110 bus_space_tag_t mvpex_io_bs_tag, mvpex_mem_bs_tag; 111 uint64_t iostart = 0, ioend = 0, memstart = 0, memend = 0; 112 uint32_t cl_size = 0; 113 int i; 114#endif 115 116 aprint_normal(": Marvell PCI Express Interface\n"); 117 aprint_naive("\n"); 118 119#if NPCI > 0 120 iot = prop_dictionary_get(dict, "io-bus-tag"); 121 if (iot == NULL) { 122 aprint_error_dev(self, "no io-bus-tag property\n"); 123 return; 124 } 125 KASSERT(prop_object_type(iot) == PROP_TYPE_DATA); 126 mvpex_io_bs_tag = __UNCONST(prop_data_data_nocopy(iot)); 127 memt = prop_dictionary_get(dict, "mem-bus-tag"); 128 if (memt == NULL) { 129 aprint_error_dev(self, "no mem-bus-tag property\n"); 130 return; 131 } 132 KASSERT(prop_object_type(memt) == PROP_TYPE_DATA); 133 mvpex_mem_bs_tag = __UNCONST(prop_data_data_nocopy(memt)); 134 pc = prop_dictionary_get(dict, "pci-chipset"); 135 if (pc == NULL) { 136 aprint_error_dev(self, "no pci-chipset property\n"); 137 return; 138 } 139 KASSERT(prop_object_type(pc) == PROP_TYPE_DATA); 140 mvpex_chipset = __UNCONST(prop_data_data_nocopy(pc)); 141#ifdef PCI_NETBSD_CONFIGURE 142 if (!prop_dictionary_get_uint64(dict, "iostart", &iostart)) { 143 aprint_error_dev(self, "no iostart property\n"); 144 return; 145 } 146 if (!prop_dictionary_get_uint64(dict, "ioend", &ioend)) { 147 aprint_error_dev(self, "no ioend property\n"); 148 return; 149 } 150 if (!prop_dictionary_get_uint64(dict, "memstart", &memstart)) { 151 aprint_error_dev(self, "no memstart property\n"); 152 return; 153 } 154 if (!prop_dictionary_get_uint64(dict, "memend", &memend)) { 155 aprint_error_dev(self, "no memend property\n"); 156 return; 157 } 158 if (!prop_dictionary_get_uint32(dict, "cache-line-size", &cl_size)) { 159 aprint_error_dev(self, "no cache-line-size property\n"); 160 return; 161 } 162#endif 163#endif 164 165 sc->sc_dev = self; 166 sc->sc_model = mva->mva_model; 167 sc->sc_rev = mva->mva_revision; 168 sc->sc_offset = mva->mva_offset; 169 sc->sc_iot = mva->mva_iot; 170 171 /* Map I/O registers for mvpex */ 172 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, mva->mva_offset, 173 mva->mva_size, &sc->sc_ioh)) { 174 aprint_error_dev(self, "can't map registers\n"); 175 return; 176 } 177 mvpex_init(sc); 178 179 /* XXX: looks seem good to specify level IPL_VM. */ 180 marvell_intr_establish(mva->mva_irq, IPL_VM, mvpex_intr, sc); 181 182#if NPCI > 0 183 for (i = 0; i < PCI_INTERRUPT_PIN_MAX; i++) { 184 sc->sc_intrtab[i].intr_pin = PCI_INTERRUPT_PIN_A + i; 185 sc->sc_intrtab[i].intr_refcnt = 0; 186 LIST_INIT(&sc->sc_intrtab[i].intr_list); 187 } 188 189 mvpex_pci_config(sc, mvpex_io_bs_tag, mvpex_mem_bs_tag, mva->mva_dmat, 190 mvpex_chipset, iostart, ioend, memstart, memend, cl_size); 191#endif 192} 193 194static int 195mvpex_intr(void *arg) 196{ 197 struct mvpex_softc *sc = (struct mvpex_softc *)arg; 198 struct mvpex_intrhand *ih; 199 struct mvpex_intrtab *intrtab; 200 uint32_t ic, im; 201 int handled = 0, pin, rv, i, s; 202 203 for (;;) { 204 ic = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_IC); 205 im = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_IM); 206 ic &= im; 207 208 if (!ic) 209 break; 210 211 for (i = 0, pin = PCI_INTERRUPT_PIN_A; 212 i < PCI_INTERRUPT_PIN_MAX; pin++, i++) { 213 if ((ic & MVPEX_I_PIN(pin)) == 0) 214 continue; 215 216 intrtab = &sc->sc_intrtab[i]; 217 LIST_FOREACH(ih, &intrtab->intr_list, ih_q) { 218 s = _splraise(ih->ih_type); 219 rv = (*ih->ih_func)(ih->ih_arg); 220 splx(s); 221 if (rv) { 222 ih->ih_evcnt.ev_count++; 223 handled++; 224 } 225 } 226 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_IC, 227 ~MVPEX_I_PIN(pin)); 228 } 229 } 230 231 return handled; 232} 233 234 235static void 236mvpex_init(struct mvpex_softc *sc) 237{ 238 uint32_t reg; 239 int window; 240 241 /* 242 * First implement Guideline (GL# PCI Express-2) Wrong Default Value 243 * to Transmitter Output Current (TXAMP) Relevant for: 88F5181-A1/B0/B1 244 * and 88F5281-B0 245 */ 246 /* Write the read command */ 247 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0x1b00, 0x80820000); 248 reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 0x1b00); 249 /* Prepare new data for write */ 250 reg &= ~0x7; /* Clear bits [2:0] */ 251 reg |= 0x4; /* Set the new value */ 252 reg &= ~0x80000000; /* Set "write" command */ 253 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0x1b00, reg); 254 255 for (window = 0; window < MVPEX_NWINDOW; window++) 256 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_WC(window), 0); 257 258#if 0 /* shall move to pchb(4)? */ 259 mvpex_barinit(sc); 260#else 261 mvpex_wininit(sc); 262#endif 263 264 /* Clear Interrupt Cause and Mask registers */ 265 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_IC, 0); 266 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_IM, 0); 267 268 /* now wait 60 ns to be sure the link is valid (spec compliant) */ 269 delay(1); 270} 271 272#if 0 273static int 274mvpex_wininit(struct mvpex_softc *sc, int window, int tbegin, int tend, 275 int barmap, uint32_t *barbase, uint32_t *barsize) 276{ 277 uint32_t target, attr, base, size; 278 int targetid; 279 280 for (targetid = tbegin; targetid <= tend && window < MVPEX_NWINDOW; 281 targetid++) { 282 if (orion_target(targetid, &target, &attr, &base, &size) == -1) 283 continue; 284 if (size == 0) 285 continue; 286 287 if (base < *barbase) 288 *barbase = base; 289 *barsize += size; 290 291 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_WC(window), 292 MVPEX_WC_WINEN | 293 barmap | 294 MVPEX_WC_TARGET(target) | 295 MVPEX_WC_ATTR(attr) | 296 MVPEX_WC_SIZE(size)); 297 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_WB(window), 298 MVPEX_WB_BASE(base)); 299 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_WR(window), 0); 300 window++; 301 } 302 303 return window; 304} 305 306/* shall move to pchb(4)? */ 307static void 308mvpex_barinit(struct mvpex_softc *sc) 309{ 310 const uint32_t barflag = 311 PCI_MAPREG_MEM_PREFETCHABLE_MASK | PCI_MAPREG_MEM_TYPE_64BIT; 312 uint32_t base, size; 313 int window = 0; 314 315 marvell_winparams_by_tag(device_parent(sc->sc_dev), 316 ORION_TARGETID_INTERNALREG, NULL, NULL, &base, &size); 317 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_BAR0INTERNAL, 318 barflag | (base & MVPEX_BAR0INTERNAL_MASK)); 319 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_BAR0INTERNALH, 0); 320 321 base = size = 0; 322 window = mvpex_wininit(sc, window, ORION_TARGETID_SDRAM_CS0, 323 ORION_TARGETID_SDRAM_CS3, MVPEX_WC_BARMAP_BAR1, &base, &size); 324 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_BAR1, 325 barflag | (base & MVPEX_BAR_MASK)); 326 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_BAR1H, 0); 327 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_BAR1C, 328 MVPEX_BARC_BARSIZE(size) | MVPEX_BARC_BAREN); 329 330#if 0 331 base = size = 0; 332 if (sc->sc_model == MARVELL_ORION_1_88F1181) 333 window = mvpex_wininit(sc, window, ORION_TARGETID_FLASH_CS, 334 ORION_TARGETID_DEVICE_BOOTCS, 335 MVPEX_WC_BARMAP_BAR2, &base, &size); 336 else { 337 window = mvpex_wininit(sc, window, 338 ORION_TARGETID_DEVICE_CS0, ORION_TARGETID_DEVICE_CS2, 339 MVPEX_WC_BARMAP_BAR2, &base, &size); 340 window = mvpex_wininit(sc, window, 341 ORION_TARGETID_DEVICE_BOOTCS, ORION_TARGETID_DEVICE_BOOTCS, 342 MVPEX_WC_BARMAP_BAR2, &base, &size); 343 } 344 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_BAR2, 345 barflag | (base & MVPEX_BAR_MASK)); 346 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_BAR2H, 0); 347 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_BAR2C, 348 MVPEX_BARC_BARSIZE(size) | MVPEX_BARC_BAREN); 349#else 350 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_BAR2C, 0); 351#endif 352} 353#else 354static void 355mvpex_wininit(struct mvpex_softc *sc) 356{ 357 device_t pdev = device_parent(sc->sc_dev); 358 uint64_t base; 359 uint32_t size; 360 int target, attr, window, rv, i; 361 static struct { 362 int tag; 363 int bar; 364 } tags[] = { 365 { MARVELL_TAG_SDRAM_CS0, MVPEX_WC_BARMAP_BAR1 }, 366 { MARVELL_TAG_SDRAM_CS1, MVPEX_WC_BARMAP_BAR1 }, 367 { MARVELL_TAG_SDRAM_CS2, MVPEX_WC_BARMAP_BAR1 }, 368 { MARVELL_TAG_SDRAM_CS3, MVPEX_WC_BARMAP_BAR1 }, 369 370 { MARVELL_TAG_UNDEFINED, 0 }, 371 }; 372 373 for (window = 0, i = 0; 374 tags[i].tag != MARVELL_TAG_UNDEFINED && window < MVPEX_NWINDOW; 375 i++) { 376 rv = marvell_winparams_by_tag(pdev, tags[i].tag, 377 &target, &attr, &base, &size); 378 if (rv != 0 || size == 0) 379 continue; 380 381 if (base > 0xffffffffULL) { 382 aprint_error_dev(sc->sc_dev, 383 "tag %d address 0x%llx not support\n", 384 tags[i].tag, base); 385 continue; 386 } 387 388 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_WC(window), 389 MVPEX_WC_WINEN | 390 tags[i].bar | 391 MVPEX_WC_TARGET(target) | 392 MVPEX_WC_ATTR(attr) | 393 MVPEX_WC_SIZE(size)); 394 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_WB(window), 395 MVPEX_WB_BASE(base)); 396 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_WR(window), 0); 397 window++; 398 } 399 for ( ; window < MVPEX_NWINDOW; window++) 400 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_WC(window), 0); 401} 402#endif 403 404#if NPCI > 0 405static void 406mvpex_pci_config(struct mvpex_softc *sc, bus_space_tag_t iot, 407 bus_space_tag_t memt, bus_dma_tag_t dmat, pci_chipset_tag_t pc, 408 u_long iostart, u_long ioend, u_long memstart, u_long memend, 409 int cacheline_size) 410{ 411 struct pcibus_attach_args pba; 412#ifdef PCI_NETBSD_CONFIGURE 413 struct extent *ioext = NULL, *memext = NULL; 414#endif 415 uint32_t stat; 416 417 stat = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_STAT); 418 419#ifdef PCI_NETBSD_CONFIGURE 420 ioext = extent_create("pexio", iostart, ioend, NULL, 0, EX_NOWAIT); 421 memext = extent_create("pexmem", memstart, memend, NULL, 0, EX_NOWAIT); 422 if (ioext != NULL && memext != NULL) 423 pci_configure_bus(pc, ioext, memext, NULL, 424 MVPEX_STAT_PEXBUSNUM(stat), cacheline_size); 425 else 426 aprint_error_dev(sc->sc_dev, "can't create extent %s%s%s\n", 427 ioext == NULL ? "io" : "", 428 ioext == NULL && memext == NULL ? " and " : "", 429 memext == NULL ? "mem" : ""); 430 if (ioext != NULL) 431 extent_destroy(ioext); 432 if (memext != NULL) 433 extent_destroy(memext); 434#endif 435 436 pba.pba_iot = iot; 437 pba.pba_memt = memt; 438 pba.pba_dmat = dmat; 439 pba.pba_dmat64 = NULL; 440 pba.pba_pc = pc; 441 pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY; 442 pba.pba_bus = MVPEX_STAT_PEXBUSNUM(stat); 443 pba.pba_bridgetag = NULL; 444 config_found_ia(sc->sc_dev, "pcibus", &pba, NULL); 445} 446 447 448/* 449 * PCI-Express CPU dependent code 450 */ 451 452/* ARGSUSED */ 453void 454mvpex_attach_hook(device_t parent, device_t self, 455 struct pcibus_attach_args *pba) 456{ 457 458 /* Nothing */ 459} 460 461/* 462 * Bit map for configuration register: 463 * [31] ConfigEn 464 * [30:28] Reserved 465 * [27:24] ExtRegNum (PCI Express only) 466 * [23:16] BusNum 467 * [15:11] DevNum 468 * [10: 8] FunctNum 469 * [ 7: 2] RegNum 470 * [ 1: 0] reserved 471 */ 472 473/* ARGSUSED */ 474int 475mvpex_bus_maxdevs(void *v, int busno) 476{ 477 478 return 32; /* 32 device/bus */ 479} 480 481/* ARGSUSED */ 482pcitag_t 483mvpex_make_tag(void *v, int bus, int dev, int func) 484{ 485 486 return (bus << 16) | (dev << 11) | (func << 8); 487} 488 489/* ARGSUSED */ 490void 491mvpex_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 492{ 493 494 if (bp != NULL) 495 *bp = (tag >> 16) & 0xff; 496 if (dp != NULL) 497 *dp = (tag >> 11) & 0x1f; 498 if (fp != NULL) 499 *fp = (tag >> 8) & 0x07; 500} 501 502pcireg_t 503mvpex_conf_read(void *v, pcitag_t tag, int reg) 504{ 505 struct mvpex_softc *sc = v; 506 pcireg_t addr, pci_cs; 507 uint32_t stat; 508 int bus, dev, func, pexbus, pexdev; 509 510 mvpex_decompose_tag(v, tag, &bus, &dev, &func); 511 512 stat = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_STAT); 513 pexbus = MVPEX_STAT_PEXBUSNUM(stat); 514 pexdev = MVPEX_STAT_PEXDEVNUM(stat); 515 if (bus != pexbus || dev != pexdev) 516 if (stat & MVPEX_STAT_DLDOWN) 517 return -1; 518 519 if (bus == pexbus) { 520 if (pexdev == 0) { 521 if (dev != 1 && dev != pexdev) 522 return -1; 523 } else { 524 if (dev != 0 && dev != pexdev) 525 return -1; 526 } 527 if (func != 0) 528 return -1; 529 } 530 531 addr = ((reg & 0xf00) << 24) | tag | (reg & 0xfc); 532 533 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_CA, 534 addr | MVPEX_CA_CONFIGEN); 535 if ((addr | MVPEX_CA_CONFIGEN) != 536 bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_CA)) 537 return -1; 538 539 pci_cs = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 540 PCI_COMMAND_STATUS_REG); 541 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 542 PCI_COMMAND_STATUS_REG, pci_cs | PCI_STATUS_MASTER_ABORT); 543 544 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_CD); 545} 546 547void 548mvpex_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data) 549{ 550 struct mvpex_softc *sc = v; 551 pcireg_t addr; 552 uint32_t stat; 553 int bus, dev, func, pexbus, pexdev; 554 555 mvpex_decompose_tag(v, tag, &bus, &dev, &func); 556 557 stat = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_STAT); 558 pexbus = MVPEX_STAT_PEXBUSNUM(stat); 559 pexdev = MVPEX_STAT_PEXDEVNUM(stat); 560 if (bus != pexbus || dev != pexdev) 561 if (stat & MVPEX_STAT_DLDOWN) 562 return; 563 564 if (bus == pexbus) { 565 if (pexdev == 0) { 566 if (dev != 1 && dev != pexdev) 567 return; 568 } else { 569 if (dev != 0 && dev != pexdev) 570 return; 571 } 572 if (func != 0) 573 return; 574 } 575 576 addr = ((reg & 0xf00) << 24) | tag | (reg & 0xfc); 577 578 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_CA, 579 addr | MVPEX_CA_CONFIGEN); 580 if ((addr | MVPEX_CA_CONFIGEN) != 581 bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_CA)) 582 return; 583 584 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_CD, data); 585} 586 587/* ARGSUSED */ 588int 589mvpex_conf_hook(pci_chipset_tag_t pc, int bus, int dev, int func, pcireg_t id) 590{ 591 592 if (bus == 0 && dev == 0) /* don't configure GT */ 593 return 0; 594 595 return PCI_CONF_DEFAULT; 596} 597 598int 599mvpex_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 600{ 601 602 switch (pa->pa_intrpin) { 603 case PCI_INTERRUPT_PIN_A: 604 case PCI_INTERRUPT_PIN_B: 605 case PCI_INTERRUPT_PIN_C: 606 case PCI_INTERRUPT_PIN_D: 607 *ihp = pa->pa_intrpin; 608 return 0; 609 } 610 return -1; 611} 612 613/* ARGSUSED */ 614const char * 615mvpex_intr_string(void *v, pci_intr_handle_t pin) 616{ 617 static char intrstr[32]; 618 619 switch (pin) { 620 case PCI_INTERRUPT_PIN_A: 621 case PCI_INTERRUPT_PIN_B: 622 case PCI_INTERRUPT_PIN_C: 623 case PCI_INTERRUPT_PIN_D: 624 break; 625 626 default: 627 return NULL; 628 } 629 snprintf(intrstr, sizeof(intrstr), "interrupt pin INT%c#", 630 (char)('A' - 1 + pin)); 631 632 return intrstr; 633} 634 635/* ARGSUSED */ 636const struct evcnt * 637mvpex_intr_evcnt(void *v, pci_intr_handle_t pin) 638{ 639 640 return NULL; 641} 642 643/* 644 * XXXX: Shall these functions use mutex(9) instead of spl(9)? 645 * MV78200 and MV64360 and after supports SMP. 646 */ 647 648/* ARGSUSED */ 649void * 650mvpex_intr_establish(void *v, pci_intr_handle_t pin, int ipl, 651 int (*intrhand)(void *), void *intrarg) 652{ 653 struct mvpex_softc *sc = (struct mvpex_softc *)v; 654 struct mvpex_intrtab *intrtab; 655 struct mvpex_intrhand *pexih; 656 uint32_t mask; 657 int ih = pin - 1, s; 658 659 intrtab = &sc->sc_intrtab[ih]; 660 661 KASSERT(pin == intrtab->intr_pin); 662 663 pexih = malloc(sizeof(*pexih), M_DEVBUF, M_NOWAIT); 664 if (pexih == NULL) 665 return NULL; 666 667 pexih->ih_func = intrhand; 668 pexih->ih_arg = intrarg; 669 pexih->ih_type = ipl; 670 pexih->ih_intrtab = intrtab; 671 evcnt_attach_dynamic(&pexih->ih_evcnt, EVCNT_TYPE_INTR, NULL, "mvpex", 672 mvpex_intr_string(v, pin)); 673 674 s = splhigh(); 675 676 /* First, link it into the tables. */ 677 LIST_INSERT_HEAD(&intrtab->intr_list, pexih, ih_q); 678 679 /* Now enable it. */ 680 if (intrtab->intr_refcnt++ == 0) { 681 mask = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_IM); 682 mask |= MVPEX_I_PIN(intrtab->intr_pin); 683 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_IM, mask); 684 } 685 686 splx(s); 687 688 return pexih; 689} 690 691void 692mvpex_intr_disestablish(void *v, void *ih) 693{ 694 struct mvpex_softc *sc = (struct mvpex_softc *)v; 695 struct mvpex_intrtab *intrtab; 696 struct mvpex_intrhand *pexih = ih; 697 uint32_t mask; 698 int s; 699 700 intrtab = pexih->ih_intrtab; 701 702 s = splhigh(); 703 704 /* 705 * First, remove it from the table. 706 */ 707 LIST_REMOVE(pexih, ih_q); 708 709 /* Now, disable it, if there is nothing remaining on the list. */ 710 if (intrtab->intr_refcnt-- == 1) { 711 mask = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_IM); 712 mask &= ~MVPEX_I_PIN(intrtab->intr_pin); 713 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_IM, mask); 714 } 715 splx(s); 716 717 free(pexih, M_DEVBUF); 718} 719#endif /* NPCI > 0 */ 720