1/* $NetBSD: ihareg.h,v 1.8 2005/12/11 12:21:27 christos Exp $ */ 2 3/*- 4 * Device driver for the INI-9XXXU/UW or INIC-940/950 PCI SCSI Controller. 5 * 6 * Written for 386bsd and FreeBSD by 7 * Winston Hung <winstonh@initio.com> 8 * 9 * Copyright (c) 1997-1999 Initio Corp. 10 * Copyright (c) 2000 Ken Westerback 11 * All rights reserved. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer, 18 * without modification, immediately at the beginning of the file. 19 * 2. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 31 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35/* 36 * Ported to NetBSD by Izumi Tsutsui <tsutsui@NetBSD.org> from OpenBSD: 37 * $OpenBSD: iha.h,v 1.2 2001/02/08 17:35:05 krw Exp $ 38 */ 39 40/* 41 * Tulip (aka inic-940/950) PCI Configuration Space Initio Specific Registers 42 * 43 * Offsets 0x00 through 0x3f are the standard PCI Configuration Header 44 * registers. 45 * 46 * Offsets 0x40 through 0x4f, 0x51, 0x53, 0x57, 0x5b, 0x5e and 0x5f are 47 * reserved registers. 48 * 49 * Registers 0x50 and 0x52 always read as 0. 50 * 51 * The register offset names and associated bit field names are taken 52 * from the Inic-950 Data Sheet, Version 2.1, March 1997 53 */ 54#define TUL_GCTRL0 0x54 /* R/W Global Control 0 */ 55#define EEPRG 0x04 /* Enable EEPROM Programming */ 56#define TUL_GCTRL1 0x55 /* R/W Global Control 1 */ 57#define ATDEN 0x01 /* Auto Termination Detect Enable */ 58#define TUL_GSTAT 0x56 /* R/W Global Status - connector type */ 59#define TUL_EPAD0 0x58 /* R/W External EEPROM Addr (lo byte) */ 60#define TUL_EPAD1 0x59 /* R/W External EEPROM Addr (hi byte) */ 61#define TUL_PNVPG 0x5A /* R/W Data port to external BIOS */ 62#define TUL_EPDATA 0x5C /* R/W EEPROM Data port */ 63#define TUL_NVRAM 0x5D /* R/W Non-volatile RAM port */ 64#define READ 0x80 /* Read from given NVRAM addr */ 65#define WRITE 0x40 /* Write to given NVRAM addr */ 66#define ENABLE_ERASE 0x30 /* Enable NVRAM Erase/Write */ 67#define NVRCS 0x08 /* Select external NVRAM */ 68#define NVRCK 0x04 /* NVRAM Clock */ 69#define NVRDO 0x02 /* NVRAM Write Data */ 70#define NVRDI 0x01 /* NVRAM Read Data */ 71 72/* 73 * Tulip (aka inic-940/950) SCSI Registers 74 */ 75#define TUL_STCNT0 0x80 /* R/W 24 bit SCSI Xfer Count */ 76#define TCNT 0x00ffffff /* SCSI Xfer Transfer Count */ 77#define TUL_SFIFOCNT 0x83 /* R/W 5 bit FIFO counter */ 78#define FIFOC 0x1f /* SCSI Offset Fifo Count */ 79#define TUL_SISTAT 0x84 /* R Interrupt Register */ 80#define RSELED 0x80 /* Reselected */ 81#define STIMEO 0x40 /* Selected/Reselected Timeout */ 82#define SBSRV 0x20 /* SCSI Bus Service */ 83#define SRSTD 0x10 /* SCSI Reset Detected */ 84#define DISCD 0x08 /* Disconnected Status */ 85#define SELED 0x04 /* Select Interrupt */ 86#define SCAMSCT 0x02 /* SCAM selected */ 87#define SCMDN 0x01 /* Command Complete */ 88#define TUL_SIEN 0x84 /* W Interrupt enable */ 89#define ALL_INTERRUPTS 0xff 90#define TUL_STAT0 0x85 /* R Status 0 */ 91#define INTPD 0x80 /* Interrupt pending */ 92#define SQACT 0x40 /* Sequencer active */ 93#define XFCZ 0x20 /* Xfer counter zero */ 94#define SFEMP 0x10 /* FIFO empty */ 95#define SPERR 0x08 /* SCSI parity error */ 96#define PH_MASK 0x07 /* SCSI phase mask */ 97#define TUL_SCTRL0 0x85 /* W Control 0 */ 98#define RSSQC 0x20 /* Reset sequence counter */ 99#define RSFIFO 0x10 /* Flush FIFO */ 100#define CMDAB 0x04 /* Abort command (sequence) */ 101#define RSMOD 0x02 /* Reset SCSI Chip */ 102#define RSCSI 0x01 /* Reset SCSI Bus */ 103#define TUL_STAT1 0x86 /* R Status 1 */ 104#define STRCV 0x80 /* Status received */ 105#define MSGST 0x40 /* Message sent */ 106#define CPDNE 0x20 /* Data phase done */ 107#define DPHDN 0x10 /* Data phase done */ 108#define STSNT 0x08 /* Status sent */ 109#define SXCMP 0x04 /* Xfer completed */ 110#define SLCMP 0x02 /* Selection completed */ 111#define ARBCMP 0x01 /* Arbitration completed */ 112#define TUL_SCTRL1 0x86 /* W Control 1 */ 113#define ENSCAM 0x80 /* Enable SCAM */ 114#define NIDARB 0x40 /* No ID for Arbitration */ 115#define ENLRS 0x20 /* Low Level Reselect */ 116#define PWDN 0x10 /* Power down mode */ 117#define WCPU 0x08 /* Wide CPU */ 118#define EHRSL 0x04 /* Enable HW reselect */ 119#define ESBUSOUT 0x02 /* Enable SCSI data bus out latch */ 120#define ESBUSIN 0x01 /* Enable SCSI data bus in latch */ 121#define TUL_SSTATUS2 0x87 /* R Status 2 */ 122#define SABRT 0x80 /* Command aborted */ 123#define OSCZ 0x40 /* Offset counter zero */ 124#define SFFUL 0x20 /* FIFO full */ 125#define TMCZ 0x10 /* Timeout counter zero */ 126#define BSYGN 0x08 /* Busy release */ 127#define PHMIS 0x04 /* Phase mismatch */ 128#define SBEN 0x02 /* SCSI data bus enable */ 129#define SRST 0x01 /* SCSI bus reset in progress */ 130#define TUL_SCONFIG0 0x87 /* W Configuration */ 131#define PHLAT 0x80 /* Enable phase latch */ 132#define ITMOD 0x40 /* Initiator mode */ 133#define SPCHK 0x20 /* Enable SCSI parity */ 134#define ADMA8 0x10 /* Alternate dma 8-bits mode */ 135#define ADMAW 0x08 /* Alternate dma 16-bits mode */ 136#define EDACK 0x04 /* Enable DACK in wide SCSI xfer */ 137#define ALTPD 0x02 /* Alternate sync period mode */ 138#define DSRST 0x01 /* Disable SCSI Reset signal */ 139#define SCONFIG0DEFAULT (PHLAT | ITMOD | ALTPD | DSRST) 140#define TUL_SOFSC 0x88 /* R Offset */ 141#define PERIOD_WIDE_SCSI 0x80 /* Enable Wide SCSI */ 142#define PERIOD_SYXPD 0x70 /* Synch. SCSI Xfer rate */ 143#define PERIOD_SYOFS 0x0f /* Synch. SCSI Offset */ 144#define TUL_SYNCM 0x88 /* W Sync. Xfer Period & Offset */ 145#define TUL_SBID 0x89 /* R SCSI BUS ID */ 146#define TUL_SID 0x89 /* W SCSI ID */ 147#define TUL_SALVC 0x8A /* R FIFO Avail Cnt/Identify Msg */ 148#define IHA_MSG_IDENTIFY_LUNMASK 0x07 149#define TUL_STIMO 0x8A /* W Sel/Resel Time Out Register */ 150#define STIMO_250MS 153 /* in units of 1.6385us */ 151#define TUL_SDATI 0x8B /* R SCSI Bus contents */ 152#define TUL_SDAT0 0x8B /* W SCSI Data Out */ 153#define TUL_SFIFO 0x8C /* R/W FIFO */ 154#define TUL_SSIGI 0x90 /* R SCSI signal in */ 155#define REQ 0x80 /* REQ signal */ 156#define ACK 0x40 /* ACK signal */ 157#define BSY 0x20 /* BSY signal */ 158#define SEL 0x10 /* SEL signal */ 159#define ATN 0x08 /* ATN signal */ 160#define MSG 0x04 /* MSG signal */ 161#define CD 0x02 /* C/D signal */ 162#define IO 0x01 /* I/O signal */ 163#define TUL_SSIGO 0x90 /* W SCSI signal out */ 164#define TUL_SCMD 0x91 /* R/W SCSI Command */ 165#define NO_OP 0x00 /* Place Holder for tulip_wait() */ 166#define SEL_NOATN 0x01 /* Select w/o ATN Sequence */ 167#define XF_FIFO_OUT 0x03 /* FIFO Xfer Information out */ 168#define MSG_ACCEPT 0x0F /* Message Accept */ 169#define SEL_ATN 0x11 /* Select w ATN Sequence */ 170#define SEL_ATNSTOP 0x12 /* Select w ATN & Stop Sequence */ 171#define SELATNSTOP 0x1E /* Select w ATN & Stop Sequence */ 172#define SEL_ATN3 0x31 /* Select w ATN3 Sequence */ 173#define XF_DMA_OUT 0x43 /* DMA Xfer Information out */ 174#define EN_RESEL 0x80 /* Enable Reselection */ 175#define XF_FIFO_IN 0x83 /* FIFO Xfer Information in */ 176#define CMD_COMP 0x84 /* Command Complete Sequence */ 177#define XF_DMA_IN 0xC3 /* DMA Xfer Information in */ 178#define TUL_STEST0 0x92 /* R/W Test0 */ 179#define TUL_STEST1 0x93 /* R/W Test1 */ 180 181/* 182 * Tulip (aka inic-940/950) DMA Registers 183 */ 184#define TUL_DXPA 0xC0 /* R/W DMA Xfer Physcl Addr 0-31*/ 185#define TUL_DXPAE 0xC4 /* R/W DMA Xfer Physcl Addr 32-63*/ 186#define TUL_DCXA 0xC8 /* R DMA Curr Xfer Physcl Addr 0-31*/ 187#define TUL_DCXAE 0xCC /* R DMA Curr Xfer Physcl Addr 32-63*/ 188#define TUL_DXC 0xD0 /* R/W DMA Xfer Counter */ 189#define TUL_DCXC 0xD4 /* R DMA Current Xfer Counter */ 190#define TUL_DCMD 0xD8 /* R/W DMA Command Register */ 191#define SGXFR 0x80 /* Scatter/Gather Xfer */ 192#define RSVD 0x40 /* Reserved - always reads as 0 */ 193#define XDIR 0x20 /* Xfer Direction 0/1 = out/in */ 194#define BMTST 0x10 /* Bus Master Test */ 195#define CLFIFO 0x08 /* Clear FIFO */ 196#define ABTXFR 0x04 /* Abort Xfer */ 197#define FRXFR 0x02 /* Force Xfer */ 198#define STRXFR 0x01 /* Start Xfer */ 199#define TUL_ISTUS0 0xDC /* R/W Interrupt Status Register */ 200#define DGINT 0x80 /* DMA Global Interrupt */ 201#define RSVRD0 0x40 /* Reserved */ 202#define RSVRD1 0x20 /* Reserved */ 203#define SCMP 0x10 /* SCSI Complete */ 204#define PXERR 0x08 /* PCI Xfer Error */ 205#define DABT 0x04 /* DMA Xfer Aborted */ 206#define FXCMP 0x02 /* Forced Xfer Complete */ 207#define XCMP 0x01 /* Bus Master Xfer Complete */ 208#define TUL_ISTUS1 0xDD /* R DMA status Register */ 209#define SCBSY 0x08 /* SCSI Busy */ 210#define FFULL 0x04 /* FIFO Full */ 211#define FEMPT 0x02 /* FIFO Empty */ 212#define XPEND 0x01 /* Xfer pending */ 213#define TUL_IMSK 0xE0 /* R/W Interrupt Mask Register */ 214#define MSCMP 0x10 /* Mask SCSI Complete */ 215#define MPXFER 0x08 /* Mask PCI Xfer Error */ 216#define MDABT 0x04 /* Mask Bus Master Abort */ 217#define MFCMP 0x02 /* Mask Force Xfer Complete */ 218#define MXCMP 0x01 /* Mask Bus Master Xfer Complete */ 219#define MASK_ALL (MXCMP | MFCMP | MDABT | MPXFER | MSCMP) 220#define TUL_DCTRL0 0xE4 /* R/W DMA Control Register */ 221#define SXSTP 0x80 /* SCSI Xfer Stop */ 222#define RPMOD 0x40 /* Reset PCI Module */ 223#define RSVRD2 0x20 /* SCSI Xfer Stop */ 224#define PWDWN 0x10 /* Power Down */ 225#define ENTM 0x08 /* Enable SCSI Terminator Low */ 226#define ENTMW 0x04 /* Enable SCSI Terminator High */ 227#define DISAFC 0x02 /* Disable Auto Clear */ 228#define LEDCTL 0x01 /* LED Control */ 229#define TUL_DCTRL1 0xE5 /* R/W DMA Control Register 1 */ 230#define SDWS 0x01 /* SCSI DMA Wait State */ 231#define TUL_DFIFO 0xE8 /* R/W DMA FIFO */ 232 233#define TUL_WCTRL 0xF7 /* ?/? Bus master wait state control */ 234#define TUL_DCTRL 0xFB /* ?/? DMA delay control */ 235