1/* $NetBSD$ */ 2 3/* 4 * 5 * Copyright (C) 2001 Eduardo Horvath. 6 * All rights reserved. 7 * 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 32#ifndef _IF_GEMVAR_H 33#define _IF_GEMVAR_H 34 35 36#include <sys/queue.h> 37#include <sys/callout.h> 38 39#include <sys/rnd.h> 40 41/* 42 * Misc. definitions for the Sun ``Gem'' Ethernet controller family driver. 43 */ 44 45/* 46 * Transmit descriptor list size. This is arbitrary, but allocate 47 * enough descriptors for 64 pending transmissions and 16 segments 48 * per packet. 49 */ 50#define GEM_NTXSEGS 16 51 52#define GEM_TXQUEUELEN 64 53#define GEM_NTXDESC (GEM_TXQUEUELEN * GEM_NTXSEGS) 54#define GEM_NTXDESC_MASK (GEM_NTXDESC - 1) 55#define GEM_NEXTTX(x) ((x + 1) & GEM_NTXDESC_MASK) 56 57/* 58 * Receive descriptor list size. We have one Rx buffer per incoming 59 * packet, so this logic is a little simpler. 60 */ 61#define GEM_NRXDESC 128 62#define GEM_NRXDESC_MASK (GEM_NRXDESC - 1) 63#define GEM_PREVRX(x) ((x - 1) & GEM_NRXDESC_MASK) 64#define GEM_NEXTRX(x) ((x + 1) & GEM_NRXDESC_MASK) 65 66/* 67 * Control structures are DMA'd to the GEM chip. We allocate them in 68 * a single clump that maps to a single DMA segment to make several things 69 * easier. 70 */ 71struct gem_control_data { 72 /* 73 * The transmit descriptors. 74 */ 75 struct gem_desc gcd_txdescs[GEM_NTXDESC]; 76 77 /* 78 * The receive descriptors. 79 */ 80 struct gem_desc gcd_rxdescs[GEM_NRXDESC]; 81}; 82 83#define GEM_CDOFF(x) offsetof(struct gem_control_data, x) 84#define GEM_CDTXOFF(x) GEM_CDOFF(gcd_txdescs[(x)]) 85#define GEM_CDRXOFF(x) GEM_CDOFF(gcd_rxdescs[(x)]) 86 87/* 88 * Software state for transmit jobs. 89 */ 90struct gem_txsoft { 91 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 92 bus_dmamap_t txs_dmamap; /* our DMA map */ 93 int txs_firstdesc; /* first descriptor in packet */ 94 int txs_lastdesc; /* last descriptor in packet */ 95 int txs_ndescs; /* number of descriptors */ 96 SIMPLEQ_ENTRY(gem_txsoft) txs_q; 97}; 98 99SIMPLEQ_HEAD(gem_txsq, gem_txsoft); 100 101/* 102 * Software state for receive jobs. 103 */ 104struct gem_rxsoft { 105 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 106 bus_dmamap_t rxs_dmamap; /* our DMA map */ 107}; 108 109enum gem_attach_stage { 110 GEM_ATT_BACKEND_2 = 0 111 , GEM_ATT_BACKEND_1 112 , GEM_ATT_FINISHED 113 , GEM_ATT_MII 114 , GEM_ATT_7 115 , GEM_ATT_6 116 , GEM_ATT_5 117 , GEM_ATT_4 118 , GEM_ATT_3 119 , GEM_ATT_2 120 , GEM_ATT_1 121 , GEM_ATT_0 122 , GEM_ATT_BACKEND_0 123}; 124 125/* 126 * Software state per device. 127 */ 128struct gem_softc { 129 device_t sc_dev; /* generic device information */ 130 struct ethercom sc_ethercom; /* ethernet common data */ 131 struct mii_data sc_mii; /* MII media control */ 132 struct callout sc_tick_ch; /* tick callout */ 133 struct callout sc_rx_watchdog; /* RX watchdog callout */ 134 135 /* The following bus handles are to be provided by the bus front-end */ 136 bus_space_tag_t sc_bustag; /* bus tag */ 137 bus_dma_tag_t sc_dmatag; /* bus dma tag */ 138 bus_dmamap_t sc_dmamap; /* bus dma handle */ 139 bus_space_handle_t sc_h1; /* bus space handle for bank 1 regs */ 140 bus_space_handle_t sc_h2; /* bus space handle for bank 2 regs */ 141 bus_size_t sc_size; /* bank 1 size */ 142 143 int sc_phys[2]; /* MII instance -> PHY map */ 144 145 int sc_mif_config; /* Selected MII reg setting */ 146 uint32_t sc_mii_anar; /* copy of PCS GEM_MII_ANAR register */ 147 int sc_mii_media; /* Media selected for PCS MII */ 148 149 u_int sc_variant; /* which GEM are we dealing with? */ 150#define GEM_UNKNOWN 0 /* don't know */ 151#define GEM_SUN_GEM 1 /* Sun GEM variant */ 152#define GEM_SUN_ERI 2 /* Sun ERI variant */ 153#define GEM_APPLE_GMAC 3 /* Apple GMAC variant */ 154#define GEM_APPLE_K2_GMAC 4 /* Apple K2 GMAC */ 155 156#define GEM_IS_SUN(sc) \ 157 ((sc)->sc_variant == GEM_SUN_GEM || \ 158 (sc)->sc_variant == GEM_SUN_ERI) 159#define GEM_IS_APPLE(sc) \ 160 ((sc)->sc_variant == GEM_APPLE_GMAC || \ 161 (sc)->sc_variant == GEM_APPLE_K2_GMAC) 162 163 int sc_chiprev; /* hardware revision */ 164 165 u_int sc_flags; /* */ 166 short sc_if_flags; /* copy of ifp->if_flags */ 167#define GEM_GIGABIT 0x0001 /* has a gigabit PHY */ 168#define GEM_LINK 0x0002 /* link is up */ 169#define GEM_PCI 0x0004 /* XXX PCI busses are little-endian */ 170#define GEM_SERDES 0x0008 /* use the SERDES */ 171#define GEM_SERIAL 0x0010 /* use the serial link */ 172 173 /* 174 * Ring buffer DMA stuff. 175 */ 176 bus_dma_segment_t sc_cdseg; /* control data memory */ 177 int sc_cdnseg; /* number of segments */ 178 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 179#define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 180 181 bus_dmamap_t sc_nulldmamap; /* for small packets padding */ 182 183 /* 184 * Software state for transmit and receive descriptors. 185 */ 186 struct gem_txsoft sc_txsoft[GEM_TXQUEUELEN]; 187 struct gem_rxsoft sc_rxsoft[GEM_NRXDESC]; 188 189 /* 190 * Control data structures. 191 */ 192 struct gem_control_data *sc_control_data; 193#define sc_txdescs sc_control_data->gcd_txdescs 194#define sc_rxdescs sc_control_data->gcd_rxdescs 195 196 int sc_txfree; /* number of free Tx descriptors */ 197 int sc_txnext; /* next ready Tx descriptor */ 198 int sc_txwin; /* Tx descriptors since last Tx int */ 199 200 struct gem_txsq sc_txfreeq; /* free Tx descsofts */ 201 struct gem_txsq sc_txdirtyq; /* dirty Tx descsofts */ 202 203 int sc_rxptr; /* next ready RX descriptor/descsoft */ 204 int sc_rxfifosize; /* Rx FIFO size (bytes) */ 205 206 /* ========== */ 207 int sc_inited; 208 int sc_meminited; 209 int sc_debug; 210 void *sc_sh; /* shutdownhook cookie */ 211 212 /* Special hardware hooks */ 213 void (*sc_hwreset)(struct gem_softc *); 214 void (*sc_hwinit)(struct gem_softc *); 215 216 krndsource_t rnd_source; 217 218 struct evcnt sc_ev_intr; 219#ifdef GEM_COUNTERS 220 struct evcnt sc_ev_txint; 221 struct evcnt sc_ev_rxint; 222 struct evcnt sc_ev_rxnobuf; 223 struct evcnt sc_ev_rxfull; 224 struct evcnt sc_ev_rxhist[9]; 225#endif 226 227 /* For use by the RX watchdog */ 228 u_int32_t sc_rx_fifo_wr_ptr; 229 u_int32_t sc_rx_fifo_rd_ptr; 230 231 enum gem_attach_stage sc_att_stage; 232}; 233 234#ifdef GEM_COUNTERS 235#define GEM_COUNTER_INCR(sc, ctr) ((void) (sc->ctr.ev_count++)) 236#else 237#define GEM_COUNTER_INCR(sc, ctr) ((void) sc) 238#endif 239 240 241#define GEM_DMA_READ(sc, v) \ 242 (((sc)->sc_flags & GEM_PCI) ? le64toh(v) : be64toh(v)) 243#define GEM_DMA_WRITE(sc, v) \ 244 (((sc)->sc_flags & GEM_PCI) ? htole64(v) : htobe64(v)) 245 246#define GEM_CDTXADDR(sc, x) ((sc)->sc_cddma + GEM_CDTXOFF((x))) 247#define GEM_CDRXADDR(sc, x) ((sc)->sc_cddma + GEM_CDRXOFF((x))) 248 249#define GEM_CDADDR(sc) ((sc)->sc_cddma + GEM_CDOFF) 250 251#define GEM_CDTXSYNC(sc, x, n, ops) \ 252do { \ 253 int __x, __n; \ 254 \ 255 __x = (x); \ 256 __n = (n); \ 257 \ 258 /* If it will wrap around, sync to the end of the ring. */ \ 259 if ((__x + __n) > GEM_NTXDESC) { \ 260 bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap, \ 261 GEM_CDTXOFF(__x), sizeof(struct gem_desc) * \ 262 (GEM_NTXDESC - __x), (ops)); \ 263 __n -= (GEM_NTXDESC - __x); \ 264 __x = 0; \ 265 } \ 266 \ 267 /* Now sync whatever is left. */ \ 268 bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap, \ 269 GEM_CDTXOFF(__x), sizeof(struct gem_desc) * __n, (ops)); \ 270} while (0) 271 272#define GEM_CDRXSYNC(sc, x, ops) \ 273 bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap, \ 274 GEM_CDRXOFF((x)), sizeof(struct gem_desc), (ops)) 275 276#define GEM_CDSYNC(sc, ops) \ 277 bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap, \ 278 0, sizeof(struct gem_control_data), (ops)) 279 280#define GEM_INIT_RXDESC(sc, x) \ 281do { \ 282 struct gem_rxsoft *__rxs = &sc->sc_rxsoft[(x)]; \ 283 struct gem_desc *__rxd = &sc->sc_rxdescs[(x)]; \ 284 struct mbuf *__m = __rxs->rxs_mbuf; \ 285 \ 286 __m->m_data = __m->m_ext.ext_buf; \ 287 __rxd->gd_addr = \ 288 GEM_DMA_WRITE((sc), __rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 289 __rxd->gd_flags = \ 290 GEM_DMA_WRITE((sc), \ 291 (((__m->m_ext.ext_size)<<GEM_RD_BUFSHIFT) \ 292 & GEM_RD_BUFSIZE) | GEM_RD_OWN); \ 293 GEM_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 294} while (0) 295 296#define GEM_UPDATE_RXDESC(sc, x) \ 297do { \ 298 struct gem_rxsoft *__rxs = &sc->sc_rxsoft[(x)]; \ 299 struct gem_desc *__rxd = &sc->sc_rxdescs[(x)]; \ 300 struct mbuf *__m = __rxs->rxs_mbuf; \ 301 \ 302 __rxd->gd_flags = \ 303 GEM_DMA_WRITE((sc), \ 304 (((__m->m_ext.ext_size)<<GEM_RD_BUFSHIFT) \ 305 & GEM_RD_BUFSIZE) | GEM_RD_OWN); \ 306} while (0) 307 308#ifdef _KERNEL 309bool gem_shutdown(device_t, int); 310bool gem_suspend(device_t, const pmf_qual_t *); 311bool gem_resume(device_t, const pmf_qual_t *); 312void gem_attach(struct gem_softc *, const uint8_t *); 313int gem_intr(void *); 314int gem_detach(struct gem_softc *, int); 315 316void gem_reset(struct gem_softc *); 317#endif /* _KERNEL */ 318 319 320#endif 321