1/*	$NetBSD: ad1848reg.h,v 1.9 1999/09/30 23:30:15 itohy Exp $	*/
2
3/*
4 * Copyright (c) 1994 John Brezak
5 * Copyright (c) 1991-1993 Regents of the University of California.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 *    notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 *    notice, this list of conditions and the following disclaimer in the
15 *    documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 *    must display the following acknowledgement:
18 *	This product includes software developed by the Computer Systems
19 *	Engineering Group at Lawrence Berkeley Laboratory.
20 * 4. Neither the name of the University nor of the Laboratory may be used
21 *    to endorse or promote products derived from this software without
22 *    specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * SUCH DAMAGE.
35 *
36 */
37/*
38 * Copyright (c) 1993 Analog Devices Inc. All rights reserved
39 */
40
41/* parent driver is primarily responsible for checking this */
42#define AD1848_BASE_VALID(base)	(((base) & 0x003) == 0)
43
44/* AD1848 direct registers */
45#define AD1848_IADDR		0x00
46#define AD1848_IDATA		0x01
47#define AD1848_STATUS		0x02
48#define AD1848_PIO		0x03
49
50/* Gain constants  */
51#define GAIN_0			0x00
52#define GAIN_1_5		0x01
53#define GAIN_3			0x02
54#define GAIN_4_5		0x03
55#define GAIN_6			0x04
56#define GAIN_7_5		0x05
57#define GAIN_9			0x06
58#define GAIN_10_5		0x07
59#define GAIN_12			0x08
60#define GAIN_13_5		0x09
61#define GAIN_15			0x0a
62#define GAIN_16_5		0x0b
63#define GAIN_18			0x0c
64#define GAIN_19_5		0x0d
65#define GAIN_21			0x0e
66#define GAIN_22_5		0x0f
67
68/* Attenuation constants  */
69
70#define ATTEN_0			0x00
71#define ATTEN_1_5		0x01
72#define ATTEN_3			0x02
73#define ATTEN_4_5		0x03
74#define ATTEN_6			0x04
75#define ATTEN_7_5		0x05
76#define ATTEN_9			0x06
77#define ATTEN_10_5		0x07
78#define ATTEN_12		0x08
79#define ATTEN_13_5		0x09
80#define ATTEN_15		0x0a
81#define ATTEN_16_5		0x0b
82#define ATTEN_18		0x0c
83#define ATTEN_19_5		0x0d
84#define ATTEN_21		0x0e
85#define ATTEN_22_5		0x0f
86
87/* AD1848 Index register (R0) */
88#define SP_IN_INIT		0x80
89#define MODE_CHANGE_ENABLE	0x40
90#define TRANSFER_DISABLE	0x20
91#define ADDRESS_MASK		0xe0
92
93/* Status bits - register R2 (read-only) */
94#define INTERRUPT_STATUS	0x01
95#define PLAYBACK_READY		0x02
96#define PLAYBACK_LEFT		0x04
97/* pbright is not left */
98#define PLAYBACK_UPPER		0x08
99/* bplower is not upper */
100#define SAMPLE_ERROR		0x10
101#define CAPTURE_READY		0x20
102#define CAPTURE_LEFT		0x40
103/* cpright is not left */
104#define CAPTURE_UPPER		0x80
105/* cplower is not upper */
106
107#define AD_R2_BITS	"\20\1INT\2PRDY\3PL/R\4PU/L\5SER\6CRDY\7CL/R\10CU/L"
108
109
110/* ADC Input control - registers I0 (left) and I1 (right) */
111#define LINE_INPUT		0x00
112#define AUX_INPUT		0x40
113#define MIC_INPUT		0x80
114#define MIXED_DAC_INPUT		0xc0
115#define INPUT_GAIN_MASK		0xf0
116#define INPUT_MIC_GAIN_ENABLE	0x20
117#define INPUT_SOURCE_MASK	0x3f
118
119/* Aux input control - registers I2 (channel 1,left); I3 (channel 1,right)
120				 I4 (channel 2,left); I5 (channel 2,right) */
121#define AUX_INPUT_ATTEN_BITS	0x1f
122#define AUX_INPUT_ATTEN_MASK	0xe0
123#define AUX_INPUT_MUTE		0x80
124
125/* Output bits - registers I6,I7*/
126#define OUTPUT_MUTE		0x80
127#define OUTPUT_ATTEN_BITS	0x3f
128#define OUTPUT_ATTEN_MASK	(~OUTPUT_ATTEN_BITS & 0xff)
129
130/* Clock and Data format reg bits (some also Capture Data format) - reg I8 */
131#define CLOCK_XTAL2		0x01
132#define CLOCK_XTAL1		0x00
133#define CLOCK_FREQ_MASK		0xf1
134#define FMT_MONO		0x00
135#define FMT_STEREO		0x10
136#define FORMAT_MASK		0x1f
137#define FMT_PCM8		0x00	/* 8-bit unsigned */
138#define FMT_ULAW		0x20	/* 8-bit mu-law */
139#define FMT_TWOS_COMP		0x40	/* 16-bit signed */
140#define FMT_ALAW		0x60	/* 8-bit A-law */
141#define FMT_ADPCM		0xa0	/* IMA ADPCM */
142#define FMT_TWOS_COMP_BE	0xc0	/* 16-bit signed, big endian */
143
144/* Interface Configuration reg bits - register I9 */
145#define PLAYBACK_ENABLE		0x01
146#define CAPTURE_ENABLE		0x02
147#define DUAL_DMA		0x00
148#define SINGLE_DMA		0x04
149#define AUTO_CAL_ENABLE		0x08
150#define PLAYBACK_PIO_ENABLE	0x40
151#define CAPTURE_PIO_ENABLE	0x80
152
153/* Pin control bits - register I10 */
154#define INTERRUPT_ENABLE	0x02
155#define XCTL0_ENABLE		0x40
156#define XCTL1_ENABLE		0x80
157
158/* Test and init reg bits - register I11 (read-only) */
159#define OVERRANGE_LEFT_MASK	0xfc
160#define OVERRANGE_RIGHT_MASK	0xf3
161#define DATA_REQUEST_STATUS	0x10
162#define AUTO_CAL_IN_PROG	0x20
163#define PLAYBACK_UNDERRUN	0x40
164#define CAPTURE_OVERRUN		0x80
165
166/* Miscellaneous Control reg bits - register I12 */
167#define ID_MASK			0x70
168#define MODE2			0x40
169#define MODE3			0x60
170
171/* Digital Mix Control reg bits - register I13 */
172#define DIGITAL_MIX1_ENABLE	0x01
173#define MIX_ATTEN_MASK		0x03
174
175/* AD1848 Sound Port reg defines */
176#define SP_LEFT_INPUT_CONTROL	0
177#define SP_RIGHT_INPUT_CONTROL	1
178#define SP_LEFT_AUX1_CONTROL	2
179#define SP_RIGHT_AUX1_CONTROL	3
180#define SP_LEFT_AUX2_CONTROL	4
181#define SP_RIGHT_AUX2_CONTROL	5
182#define SP_LEFT_OUTPUT_CONTROL	6
183#define SP_RIGHT_OUTPUT_CONTROL 7
184#define SP_CLOCK_DATA_FORMAT	8
185#define SP_INTERFACE_CONFIG	9
186#define SP_PIN_CONTROL		10
187#define SP_TEST_AND_INIT	11
188#define SP_MISC_INFO		12
189#define SP_DIGITAL_MIX		13
190#define SP_UPPER_BASE_COUNT	14
191#define SP_LOWER_BASE_COUNT	15
192
193#define SP_IADDR_MASK		0xaf
194