1/*	$NetBSD: gio.c,v 1.31 2009/03/18 10:22:35 cegger Exp $	*/
2
3/*
4 * Copyright (c) 2000 Soren S. Jorvang
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 *    must display the following acknowledgement:
17 *          This product includes software developed for the
18 *          NetBSD Project.  See http://www.NetBSD.org/ for
19 *          information about NetBSD.
20 * 4. The name of the author may not be used to endorse or promote products
21 *    derived from this software without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <sys/cdefs.h>
36__KERNEL_RCSID(0, "$NetBSD: gio.c,v 1.31 2009/03/18 10:22:35 cegger Exp $");
37
38#include "opt_ddb.h"
39
40#include <sys/param.h>
41#include <sys/systm.h>
42#include <sys/device.h>
43
44#define _SGIMIPS_BUS_DMA_PRIVATE
45#include <sys/bus.h>
46#include <machine/machtype.h>
47#include <machine/sysconf.h>
48
49#include <sgimips/gio/gioreg.h>
50#include <sgimips/gio/giovar.h>
51#include <sgimips/gio/giodevs_data.h>
52
53#include "locators.h"
54#include "newport.h"
55#include "grtwo.h"
56#include "light.h"
57#include "imc.h"
58#include "pic.h"
59
60#if (NNEWPORT > 0)
61#include <sgimips/gio/newportvar.h>
62#endif
63
64#if (NGRTWO > 0)
65#include <sgimips/gio/grtwovar.h>
66#endif
67
68#if (NLIGHT > 0)
69#include <sgimips/gio/lightvar.h>
70#endif
71
72#if (NIMC > 0)
73extern int imc_gio64_arb_config(int, uint32_t);
74#endif
75
76#if (NPIC > 0)
77extern int pic_gio32_arb_config(int, uint32_t);
78#endif
79
80
81struct gio_softc {
82	struct	device sc_dev;
83};
84
85static int	gio_match(struct device *, struct cfdata *, void *);
86static void	gio_attach(struct device *, struct device *, void *);
87static int	gio_print(void *, const char *);
88static int	gio_search(struct device *, struct cfdata *,
89			   const int *, void *);
90static int	gio_submatch(struct device *, struct cfdata *,
91			     const int *, void *);
92
93CFATTACH_DECL(gio, sizeof(struct gio_softc),
94    gio_match, gio_attach, NULL, NULL);
95
96struct gio_probe {
97	uint32_t slot;
98	uint32_t base;
99	uint32_t mach_type;
100	uint32_t mach_subtype;
101};
102
103/*
104 * Expansion Slot Base Addresses
105 *
106 * IP12, IP20 and IP24 have two GIO connectors: GIO_SLOT_EXP0 and
107 * GIO_SLOT_EXP1.
108 *
109 * On IP24 these slots exist on the graphics board or the IOPLUS
110 * "mezzanine" on Indy and Challenge S, respectively. The IOPLUS or
111 * graphics board connects to the mainboard via a single GIO64 connector.
112 *
113 * IP22 has either three or four physical connectors, but only two
114 * electrically distinct slots: GIO_SLOT_GFX and GIO_SLOT_EXP0.
115 *
116 * It should also be noted that DMA is (mostly) not supported in Challenge
117 * S's GIO_SLOT_EXP1. See gio(4) for the story.
118 */
119static const struct gio_probe slot_bases[] = {
120	{ GIO_SLOT_GFX,  0x1f000000, MACH_SGI_IP22, MACH_SGI_IP22_FULLHOUSE },
121
122	{ GIO_SLOT_EXP0, 0x1f400000, MACH_SGI_IP12, -1 },
123	{ GIO_SLOT_EXP0, 0x1f400000, MACH_SGI_IP20, -1 },
124	{ GIO_SLOT_EXP0, 0x1f400000, MACH_SGI_IP22, -1 },
125
126	{ GIO_SLOT_EXP1, 0x1f600000, MACH_SGI_IP12, -1 },
127	{ GIO_SLOT_EXP1, 0x1f600000, MACH_SGI_IP20, -1 },
128	{ GIO_SLOT_EXP1, 0x1f600000, MACH_SGI_IP22, MACH_SGI_IP22_GUINNESS },
129
130	{ 0, 0, 0, 0 }
131};
132
133/*
134 * Graphic Board Base Addresses
135 *
136 * Graphics boards are not treated like expansion slot cards. Their base
137 * addresses do not necessarily correspond to GIO slot addresses and they
138 * do not contain product identification words.
139 */
140static const struct gio_probe gfx_bases[] = {
141	/* grtwo, and newport on IP22 */
142	{ -1, 0x1f000000, MACH_SGI_IP12, -1 },
143	{ -1, 0x1f000000, MACH_SGI_IP20, -1 },
144	{ -1, 0x1f000000, MACH_SGI_IP22, -1 },
145
146	/* light */
147	{ -1, 0x1f3f0000, MACH_SGI_IP12, -1 },
148	{ -1, 0x1f3f0000, MACH_SGI_IP20, -1 },
149
150	/* light (dual headed) */
151	{ -1, 0x1f3f8000, MACH_SGI_IP12, -1 },
152	{ -1, 0x1f3f8000, MACH_SGI_IP20, -1 },
153
154	/* grtwo, and newport on IP22 */
155	{ -1, 0x1f400000, MACH_SGI_IP12, -1 },
156	{ -1, 0x1f400000, MACH_SGI_IP20, -1 },
157	{ -1, 0x1f400000, MACH_SGI_IP22, -1 },
158
159	/* grtwo */
160	{ -1, 0x1f600000, MACH_SGI_IP12, -1 },
161	{ -1, 0x1f600000, MACH_SGI_IP20, -1 },
162	{ -1, 0x1f600000, MACH_SGI_IP22, -1 },
163
164	/* newport */
165	{ -1, 0x1f800000, MACH_SGI_IP22, MACH_SGI_IP22_FULLHOUSE },
166
167	/* newport */
168	{ -1, 0x1fc00000, MACH_SGI_IP22, MACH_SGI_IP22_FULLHOUSE },
169
170	{ 0, 0, 0, 0 }
171};
172
173/* maximum number of graphics boards possible (arbitrarily large estimate) */
174#define MAXGFX 8
175
176static int
177gio_match(struct device *parent, struct cfdata *match, void *aux)
178{
179	if (mach_type == MACH_SGI_IP12 || mach_type == MACH_SGI_IP20 ||
180	    mach_type == MACH_SGI_IP22)
181		return 1;
182
183	return 0;
184}
185
186static void
187gio_attach(struct device *parent, struct device *self, void *aux)
188{
189	struct gio_attach_args ga;
190	uint32_t gfx[MAXGFX];
191	int i, j, ngfx;
192
193	printf("\n");
194
195	ngfx = 0;
196	memset(gfx, 0, sizeof(gfx));
197
198	/*
199	 * Attach graphics devices first. They do not contain a Product
200	 * Identification Word and have no slot number.
201	 *
202	 * Record addresses to which graphics devices attach so that
203	 * we do not confuse them with expansion slots, should the
204	 * addresses coincide.
205	 */
206	for (i = 0; gfx_bases[i].base != 0; i++) {
207		/* skip slots that don't apply to us */
208		if (gfx_bases[i].mach_type != mach_type)
209			continue;
210
211		if (gfx_bases[i].mach_subtype != -1 &&
212		    gfx_bases[i].mach_subtype != mach_subtype)
213			continue;
214
215		ga.ga_slot = -1;
216		ga.ga_addr = gfx_bases[i].base;
217		ga.ga_iot = SGIMIPS_BUS_SPACE_NORMAL;
218		ga.ga_ioh = MIPS_PHYS_TO_KSEG1(ga.ga_addr);
219		ga.ga_dmat = &sgimips_default_bus_dma_tag;
220		ga.ga_product = -1;
221
222		if (platform.badaddr((void *)ga.ga_ioh, sizeof(uint32_t)))
223			continue;
224
225		if (config_found_sm_loc(self, "gio", NULL, &ga, gio_print,
226		    gio_submatch)) {
227			if (ngfx == MAXGFX)
228				panic("gio_attach: MAXGFX");
229			gfx[ngfx++] = gfx_bases[i].base;
230		}
231	}
232
233	/*
234	 * Now attach any GIO expansion cards.
235	 *
236	 * Be sure to skip any addresses to which a graphics device has
237	 * already been attached.
238	 */
239	for (i = 0; slot_bases[i].base != 0; i++) {
240		bool skip = false;
241
242		/* skip slots that don't apply to us */
243		if (slot_bases[i].mach_type != mach_type)
244			continue;
245
246		if (slot_bases[i].mach_subtype != -1 &&
247		    slot_bases[i].mach_subtype != mach_subtype)
248			continue;
249
250		for (j = 0; j < ngfx; j++) {
251			if (slot_bases[i].base == gfx[j]) {
252				skip = true;
253				break;
254			}
255		}
256		if (skip)
257			continue;
258
259		ga.ga_slot = slot_bases[i].slot;
260		ga.ga_addr = slot_bases[i].base;
261		ga.ga_iot = SGIMIPS_BUS_SPACE_NORMAL;
262		ga.ga_ioh = MIPS_PHYS_TO_KSEG1(ga.ga_addr);
263		ga.ga_dmat = &sgimips_default_bus_dma_tag;
264
265		if (platform.badaddr((void *)ga.ga_ioh, sizeof(uint32_t)))
266			continue;
267
268		ga.ga_product = bus_space_read_4(ga.ga_iot, ga.ga_ioh, 0);
269
270		config_found_sm_loc(self, "gio", NULL, &ga, gio_print,
271		    gio_submatch);
272	}
273
274	config_search_ia(gio_search, self, "gio", &ga);
275}
276
277static int
278gio_print(void *aux, const char *pnp)
279{
280	struct gio_attach_args *ga = aux;
281	int i = 0;
282
283	/* gfx probe */
284	if (ga->ga_product == -1)
285		return (QUIET);
286
287	if (pnp != NULL) {
288	  	int product, revision;
289
290		product = GIO_PRODUCT_PRODUCTID(ga->ga_product);
291
292		if (GIO_PRODUCT_32BIT_ID(ga->ga_product))
293			revision = GIO_PRODUCT_REVISION(ga->ga_product);
294		else
295			revision = 0;
296
297		while (gio_knowndevs[i].productid != 0) {
298			if (gio_knowndevs[i].productid == product) {
299				aprint_normal("%s", gio_knowndevs[i].product);
300				break;
301			}
302			i++;
303		}
304
305		if (gio_knowndevs[i].productid == 0)
306			aprint_normal("unknown GIO card");
307
308		aprint_normal(" (product 0x%02x revision 0x%02x) at %s",
309		    product, revision, pnp);
310	}
311
312	if (ga->ga_slot != GIOCF_SLOT_DEFAULT)
313		aprint_normal(" slot %d", ga->ga_slot);
314	if (ga->ga_addr != (uint32_t) GIOCF_ADDR_DEFAULT)
315		aprint_normal(" addr 0x%x", ga->ga_addr);
316
317	return UNCONF;
318}
319
320static int
321gio_search(struct device *parent, struct cfdata *cf,
322	   const int *ldesc, void *aux)
323{
324	struct gio_attach_args *ga = aux;
325
326	do {
327		/* Handled by direct configuration, so skip here */
328		if (cf->cf_loc[GIOCF_ADDR] == GIOCF_ADDR_DEFAULT)
329			return 0;
330
331		ga->ga_slot = cf->cf_loc[GIOCF_SLOT];
332		ga->ga_addr = cf->cf_loc[GIOCF_ADDR];
333		ga->ga_iot = 0;
334		ga->ga_ioh = MIPS_PHYS_TO_KSEG1(ga->ga_addr);
335
336		if (config_match(parent, cf, ga) > 0)
337			config_attach(parent, cf, ga, gio_print);
338	} while (cf->cf_fstate == FSTATE_STAR);
339
340	return 0;
341}
342
343static int
344gio_submatch(struct device *parent, struct cfdata *cf,
345	     const int *ldesc, void *aux)
346{
347	struct gio_attach_args *ga = aux;
348
349	if (cf->cf_loc[GIOCF_SLOT] != GIOCF_SLOT_DEFAULT &&
350	    cf->cf_loc[GIOCF_SLOT] != ga->ga_slot)
351		return 0;
352
353	if (cf->cf_loc[GIOCF_ADDR] != GIOCF_ADDR_DEFAULT &&
354	    cf->cf_loc[GIOCF_ADDR] != ga->ga_addr)
355		return 0;
356
357	return config_match(parent, cf, aux);
358}
359
360int
361gio_cnattach(void)
362{
363	struct gio_attach_args ga;
364	int i;
365
366	for (i = 0; gfx_bases[i].base != 0; i++) {
367		/* skip bases that don't apply to us */
368		if (gfx_bases[i].mach_type != mach_type)
369			continue;
370
371		if (gfx_bases[i].mach_subtype != -1 &&
372		    gfx_bases[i].mach_subtype != mach_subtype)
373			continue;
374
375		ga.ga_slot = -1;
376		ga.ga_addr = gfx_bases[i].base;
377		ga.ga_iot = SGIMIPS_BUS_SPACE_NORMAL;
378		ga.ga_ioh = MIPS_PHYS_TO_KSEG1(ga.ga_addr);
379		ga.ga_dmat = &sgimips_default_bus_dma_tag;
380		ga.ga_product = -1;
381
382		if (platform.badaddr((void *)ga.ga_ioh,sizeof(uint32_t)))
383			continue;
384
385#if (NGRTWO > 0)
386		if (grtwo_cnattach(&ga) == 0)
387			return 0;
388#endif
389
390#if (NLIGHT > 0)
391		if (light_cnattach(&ga) == 0)
392			return 0;
393#endif
394
395#if (NNEWPORT > 0)
396		if (newport_cnattach(&ga) == 0)
397			return 0;
398#endif
399
400	}
401
402	return ENXIO;
403}
404
405/*
406 * Devices living in the expansion slots must enable or disable some
407 * GIO arbiter settings. This is accomplished via imc(4) or pic(4)
408 * registers, depending on the machine in question.
409 */
410int
411gio_arb_config(int slot, uint32_t flags)
412{
413
414	if (flags == 0)
415		return (EINVAL);
416
417	if (flags & ~(GIO_ARB_RT | GIO_ARB_LB | GIO_ARB_MST | GIO_ARB_SLV |
418	    GIO_ARB_PIPE | GIO_ARB_NOPIPE | GIO_ARB_32BIT | GIO_ARB_64BIT |
419	    GIO_ARB_HPC2_32BIT | GIO_ARB_HPC2_64BIT))
420		return (EINVAL);
421
422	if (((flags & GIO_ARB_RT)   && (flags & GIO_ARB_LB))  ||
423	    ((flags & GIO_ARB_MST)  && (flags & GIO_ARB_SLV)) ||
424	    ((flags & GIO_ARB_PIPE) && (flags & GIO_ARB_NOPIPE)) ||
425	    ((flags & GIO_ARB_32BIT) && (flags & GIO_ARB_64BIT)) ||
426	    ((flags & GIO_ARB_HPC2_32BIT) && (flags & GIO_ARB_HPC2_64BIT)))
427		return (EINVAL);
428
429#if (NPIC > 0)
430	if (mach_type == MACH_SGI_IP12)
431		return (pic_gio32_arb_config(slot, flags));
432#endif
433
434#if (NIMC > 0)
435	if (mach_type == MACH_SGI_IP20 || mach_type == MACH_SGI_IP22)
436		return (imc_gio64_arb_config(slot, flags));
437#endif
438
439	return (EINVAL);
440}
441
442/*
443 * Establish an interrupt handler for the specified slot.
444 *
445 * Indy and Challenge S have an interrupt per GIO slot. Indigo and Indigo2
446 * share a single interrupt, however.
447 */
448void *
449gio_intr_establish(int slot, int level, int (*func)(void *), void *arg)
450{
451	int intr;
452
453	switch (mach_type) {
454	case MACH_SGI_IP12:
455	case MACH_SGI_IP20:
456		if (slot == GIO_SLOT_GFX)
457			panic("gio_intr_establish: slot %d", slot);
458		intr = 6;
459		break;
460
461	case MACH_SGI_IP22:
462		if (mach_subtype == MACH_SGI_IP22_FULLHOUSE) {
463			if (slot == GIO_SLOT_EXP1)
464				panic("gio_intr_establish: slot %d", slot);
465			intr = 6;
466		} else {
467			if (slot == GIO_SLOT_GFX)
468				panic("gio_intr_establish: slot %d", slot);
469			intr = (slot == GIO_SLOT_EXP0) ? 22 : 23;
470		}
471		break;
472
473	default:
474		panic("gio_intr_establish: mach_type");
475	}
476
477	return (cpu_intr_establish(intr, level, func, arg));
478}
479
480const char *
481gio_product_string(int prid)
482{
483	int i;
484
485	for (i = 0; gio_knowndevs[i].product != NULL; i++)
486		if (gio_knowndevs[i].productid == prid)
487			return (gio_knowndevs[i].product);
488
489	return (NULL);
490}
491