1/* $NetBSD: imcreg.h,v 1.2.12.3 2004/09/21 13:21:13 skrll Exp $ */ 2 3/* 4 * Copyright (c) 2001 Rafal K. Boni 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30#ifndef _ARCH_SGIMIPS_DEV_IMCREG_H_ 31#define _ARCH_SGIMIPS_DEV_IMCREG_H_ 32 33#define IMC_CPUCTRL0 0x04 /* CPU control, register 0 */ 34 35#define IMC_CPUCTRL0_REFMASK 0x000f /* # lines to refresh */ 36#define IMC_CPUCTRL0_RFE 0x0010 /* refresh enable */ 37#define IMC_CPUCTRL0_GPR 0x0020 /* GIO parity enable */ 38#define IMC_CPUCTRL0_MPR 0x0040 /* memory parity enable */ 39#define IMC_CPUCTRL0_CPR 0x0080 /* cpu bus parity enable */ 40#define IMC_CPUCTRL0_WDOG 0x0100 /* watchdog enable */ 41#define IMC_CPUCTRL0_SIN 0x0200 /* reset system */ 42#define IMC_CPUCTRL0_GRR 0x0400 /* graphics reset */ 43#define IMC_CPUCTRL0_ENLOCK 0x0800 /* enable EISA memory lock */ 44#define IMC_CPUCTRL0_CMDPAR 0x1000 /* SysCmd parity enable */ 45#define IMC_CPUCTRL0_INTENA 0x2000 /* enable CPU interrupts */ 46#define IMC_CPUCTRL0_SNOOPENA 0x4000 /* enable gfx DMA snoop */ 47#define IMC_CPUCTRL0_PROM_WRENA 0x8000 /* disable buserr on PROM 48 * writes */ 49#define IMC_CPUCTRL0_WRST 0x00010000 /* warm restart (reset cpu) */ 50/* Bit 17 reserved 0x00020000 */ 51#define IMC_CPUCTRL0_LITTLE 0x00040000 /* MC little-endian toggle */ 52#define IMC_CPUCTRL0_WRRST 0x00080000 /* cpu warm reset */ 53#define IMC_CPUCTRL0_MUXHWMSK 0x01f00000 /* MUX fifo high-water mask */ 54#define IMC_CPUCTRL0_BADPAR 0x02000000 /* generate bad parity on 55 * CPU->memory writes */ 56#define IMC_CPUCTRL0_NCHKMEMPAR 0x04000000 /* disable CPU parity check 57 * on memory reads. */ 58#define IMC_CPUCTRL0_BACK2 0x08000000 /* enable back2back GIO wrt */ 59#define IMC_CPUCTRL0_BUSRTMSK 0xf0000000 /* stall cycle for berr data */ 60 61#define IMC_CPUCTRL1 0x0c /* CPU control, register 1 */ 62#define IMC_CPUCTRL1_MCHWMSK 0x0000000f /* MC FIFO high water mask */ 63#define IMC_CPUCTRL1_ABORTEN 0x00000010 /* Enable GIO bus timeouts */ 64/* Bits 5 - 11 reserved 0x00000fe0 */ 65#define IMC_CPUCTRL1_HPCFX 0x00001000 /* HPC endian fix */ 66#define IMC_CPUCTRL1_HPCLITTLE 0x00002000 /* HPC DMA is little-endian */ 67#define IMC_CPUCTRL1_EXP0FX 0x00004000 /* EXP0 endian fix */ 68#define IMC_CPUCTRL1_EXP0LITTLE 0x00008000 /* EXP0 DMA is little-endian */ 69#define IMC_CPUCTRL1_EXP1FX 0x00010000 /* EXP1 endian fix */ 70#define IMC_CPUCTRL1_EXP1LITTLE 0x00020000 /* EXP1 DMA is little-endian */ 71 72#define IMC_WDOG 0x14 /* Watchdog counter */ 73#define IMC_WDOG_MASK 0x001fffff /* counter mask */ 74 75#define IMC_SYSID 0x1c /* MC revision register */ 76#define IMC_SYSID_REVMASK 0x0000000f /* MC revision mask */ 77#define IMC_SYSID_HAVEISA 0x00000010 /* EISA present */ 78 79#define IMC_RPSSDIV 0x2c /* RPSS divider */ 80#define IMC_RPSSDIV_DIVMSK 0x000000ff /* RPC divider mask */ 81#define IMC_RPSSDIV_INCMSK 0x0000ff00 /* RPC increment mask */ 82 83#define IMC_EEPROM 0x34 /* EEPROM serial interface */ 84/* Bit 1 is reserved 0x00000001 */ 85#define IMC_EEPROM_CS 0x00000002 /* EEPROM chip select */ 86#define IMC_EEPROM_SCK 0x00000004 /* EEPROM serial clock */ 87#define IMC_EEPROM_SO 0x00000008 /* Serial data to EEPROM */ 88#define IMC_EEPROM_SI 0x00000010 /* Serial data from EEPROM */ 89 90#define IMC_CTRLD 0x44 /* Refresh counter preload */ 91#define IMC_CTRLD_MSK 0x000000ff /* Counter preload mask */ 92 93#define IMC_REFCTR 0x4c /* Refresh counter */ 94#define IMC_REFCTR_MSK 0x000000ff /* Refresh counter mask */ 95 96#define IMC_GIO64ARB 0x84 /* GIO64 arbitration params */ 97#define IMC_GIO64ARB_HPC64 0x00000001 /* HPC addr size (32/64bit) */ 98#define IMC_GIO64ARB_GRX64 0x00000002 /* Gfx addr size (32/64bit) */ 99#define IMC_GIO64ARB_EXP064 0x00000004 /* EXP0 addr size (32/64bit) */ 100#define IMC_GIO64ARB_EXP164 0x00000008 /* EXP0 addr size (32/64bit) */ 101#define IMC_GIO64ARB_EISA64 0x00000010 /* EISA addr size (32/64bit) */ 102#define IMC_GIO64ARB_HPCEXP64 0x00000020 /* HPC2 addr size (32/64bit) */ 103#define IMC_GIO64ARB_GRXRT 0x00000040 /* Gfx is realtime device */ 104#define IMC_GIO64ARB_EXP0RT 0x00000080 /* EXP0 is realtime device */ 105#define IMC_GIO64ARB_EXP1RT 0x00000100 /* EXP1 is realtime device */ 106#define IMC_GIO64ARB_EISAMST 0x00000200 /* EISA can be busmaster */ 107#define IMC_GIO64ARB_ONEGIO 0x00000400 /* One one GIO64 bus */ 108#define IMC_GIO64ARB_GRXMST 0x00000800 /* Gfx can be busmaster */ 109#define IMC_GIO64ARB_EXP0MST 0x00001000 /* EXP0 can be busmaster */ 110#define IMC_GIO64ARB_EXP1MST 0x00002000 /* EXP1 can be busmaster */ 111#define IMC_GIO64ARB_EXP0PIPE 0x00004000 /* EXP0 is pipelined */ 112#define IMC_GIO64ARB_EXP1PIPE 0x00008000 /* EXP1 is pipelined */ 113 114#define IMC_CPUTIME 0x8c /* Arbiter CPU time period */ 115 116#define IMC_LBTIME 0x9c /* Arbiter long-burst time */ 117 118#define IMC_MEMCFG0 0xc4 /* Mem config, regsiter 0 */ 119 120#define IMC_MEMCFG1 0xcc /* Mem config, regsiter 1 */ 121 122#define IMC_CPU_MEMACC 0xd4 /* CPU mem access config */ 123 124#define IMC_GIO_MEMACC 0xdc /* GIO mem access config */ 125 126#define IMC_CPU_ERRADDR 0xe4 /* CPU error address */ 127 128#define IMC_CPU_ERRSTAT 0xec /* CPU error status */ 129 130#define IMC_GIO_ERRADDR 0xf4 /* GIO error address */ 131 132#define IMC_GIO_ERRSTAT 0xfc /* GIO error status */ 133 134#endif /* _ARCH_SGIMIPS_DEV_IMCREG_H_ */ 135 136