1/*	$NetBSD: e500_timer.c,v 1.3 2011/06/25 00:07:10 matt Exp $	*/
2/*-
3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
4 * All rights reserved.
5 *
6 * This code is derived from software contributed to The NetBSD Foundation
7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects
8 * Agency and which was developed by Matt Thomas of 3am Software Foundry.
9 *
10 * This material is based upon work supported by the Defense Advanced Research
11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under
12 * Contract No. N66001-09-C-2073.
13 * Approved for Public Release, Distribution Unlimited
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 * 1. Redistributions of source code must retain the above copyright
19 *    notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 *    notice, this list of conditions and the following disclaimer in the
22 *    documentation and/or other materials provided with the distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#include <sys/cdefs.h>
38__KERNEL_RCSID(0, "$NetBSD: e500_timer.c,v 1.3 2011/06/25 00:07:10 matt Exp $");
39
40#include <sys/param.h>
41#include <sys/kernel.h>
42#include <sys/systm.h>
43#include <sys/timetc.h>
44#include <sys/intr.h>
45#include <sys/cpu.h>
46
47#include <uvm/uvm_extern.h>
48
49#include <powerpc/spr.h>
50#include <powerpc/booke/spr.h>
51#include <powerpc/booke/cpuvar.h>
52#include <powerpc/booke/e500reg.h>
53#include <powerpc/booke/e500var.h>
54#include <powerpc/booke/openpicreg.h>
55
56static u_long ns_per_tick;
57
58static void init_ppcbooke_tc(void);
59static u_int get_ppcbooke_timecount(struct timecounter *);
60
61static struct timecounter ppcbooke_timecounter = {
62	get_ppcbooke_timecount,	/* get_timecount */
63	0,			/* no poll_pps */
64	~0u,			/* counter_mask */
65	0,			/* frequency */
66	"ppc_timebase",		/* name */
67	100,			/* quality */
68	NULL,			/* tc_priv */
69	NULL			/* tc_next */
70};
71
72static inline uint32_t
73openpic_read(struct cpu_softc *cpu, bus_size_t offset)
74{
75
76	return bus_space_read_4(cpu->cpu_bst, cpu->cpu_bsh,
77	    OPENPIC_BASE + offset);
78}
79
80static inline void
81openpic_write(struct cpu_softc *cpu, bus_size_t offset, uint32_t val)
82{
83
84	return bus_space_write_4(cpu->cpu_bst, cpu->cpu_bsh,
85	    OPENPIC_BASE + offset, val);
86}
87
88int
89e500_clock_intr(void *v)
90{
91	struct trapframe * const tf = v;
92	struct cpu_info * const ci = curcpu();
93	struct cpu_softc * const cpu = ci->ci_softc;
94	u_int nticks;
95
96	/*
97	 * Check whether we are initialized.
98	 */
99	if (!cpu->cpu_ticks_per_clock_intr)
100		return 0;
101
102	/*
103	 * Now let's how delayed the clock interrupt was.  Obviously it must
104	 * at least one clock tick since the clock interrupt.  But it might
105	 * be more if interrupts were blocked for a long time.  We keep
106	 * suubtracting an interrupts We should be
107	 * [well] within a single tick.
108	 * We add back one tick (which should put us back above 0).  If we
109	 * are still below 0, keep adding ticks until we are above 0.
110	 */
111	const uint64_t now = mftb();
112	uint64_t latency = now - (ci->ci_lastintr + cpu->cpu_ticks_per_clock_intr);
113#if 0
114	uint64_t orig_latency = latency;
115#endif
116	if (now < ci->ci_lastintr + cpu->cpu_ticks_per_clock_intr)
117		latency = 0;
118
119	nticks = 1 + latency / cpu->cpu_ticks_per_clock_intr;
120	latency %= cpu->cpu_ticks_per_clock_intr;
121#if 0
122	for (nticks = 1; latency >= cpu->cpu_ticks_per_clock_intr; nticks++)  {
123		latency -= cpu->cpu_ticks_per_clock_intr;
124	}
125#endif
126
127	ci->ci_ev_clock.ev_count++;
128	cpu->cpu_ev_late_clock.ev_count += nticks - 1;
129
130	/*
131	 * lasttb is used during microtime. Set it to the virtual
132	 * start of this tick interval.
133	 */
134#if 0
135	if (nticks > 10 || now - ci->ci_lastintr < 7 * cpu->cpu_ticks_per_clock_intr / 8)
136	printf("%s: nticks=%u lastintr=%#"PRIx64"(%#"PRIx64") now=%#"PRIx64" latency=%#"PRIx64" orig=%#"PRIx64"\n", __func__,
137	    nticks, ci->ci_lastintr, now - latency, now, latency, orig_latency);
138#endif
139	ci->ci_lastintr = now - latency;
140	ci->ci_lasttb = now;
141
142	wrtee(PSL_EE);	/* Reenable interrupts */
143
144	/*
145	 * Do standard timer interrupt stuff.
146	 */
147	while (nticks-- > 0) {
148		hardclock(&tf->tf_cf);
149	}
150
151	wrtee(0);	/* turn off interrupts */
152
153	tf->tf_srr1 &= ~PSL_POW;	/* make cpu_idle exit */
154
155	return 1;
156}
157
158void
159cpu_initclocks(void)
160{
161	struct cpu_info * const ci = curcpu();
162	struct cpu_softc * const cpu = ci->ci_softc;
163
164	cpu->cpu_ticks_per_clock_intr = (ci->ci_data.cpu_cc_freq + hz/2 - 1) / hz;
165
166	/* interrupt established in e500_intr_cpu_init */
167
168	ci->ci_lastintr = ci->ci_lasttb = mftb();
169	openpic_write(cpu, cpu->cpu_clock_gtbcr,
170	     GTBCR_CI | cpu->cpu_ticks_per_clock_intr);
171	openpic_write(cpu, cpu->cpu_clock_gtbcr,
172	     cpu->cpu_ticks_per_clock_intr);
173
174	if (CPU_IS_PRIMARY(ci))
175		init_ppcbooke_tc();
176}
177
178void
179calc_delayconst(void)
180{
181	struct cpu_info * const ci = curcpu();
182
183	ci->ci_data.cpu_cc_freq = board_info_get_number("timebase-frequency");
184	ns_per_tick = 1000000000 / (u_int)ci->ci_data.cpu_cc_freq;
185}
186
187static u_int
188get_ppcbooke_timecount(struct timecounter *tc)
189{
190	return mftbl();
191}
192
193/*
194 * Wait for about n microseconds (at least!).
195 */
196void
197delay(unsigned int n)
198{
199	uint64_t tb;
200	u_long tbh, tbl, scratch;
201
202	tb = mftb();
203	/* use 1000ULL to force 64 bit math to avoid 32 bit overflows */
204	tb += (n * 1000ULL + ns_per_tick - 1) / ns_per_tick;
205	tbh = tb >> 32;
206	tbl = tb;
207	__asm volatile (
208		"1:	mfspr	%0,%4"	"\n"
209		"	cmplw	%0,%1"	"\n"
210		"	blt	1b"	"\n"
211		"	bgt	2f"	"\n"
212		"	mfspr	%0,%3"	"\n"
213		"	cmplw	%0,%2"	"\n"
214		"	blt	1b"	"\n"
215		"2:" 			"\n"
216	    : "=&r"(scratch)
217	    : "r"(tbh), "r"(tbl), "n"(SPR_TBL), "n"(SPR_TBU)
218	     : "cr0");
219}
220
221/*
222 * Nothing to do.
223 */
224void
225setstatclockrate(int arg)
226{
227
228	/* Do nothing */
229}
230
231static void
232init_ppcbooke_tc(void)
233{
234	/* from machdep initialization */
235	ppcbooke_timecounter.tc_frequency = curcpu()->ci_data.cpu_cc_freq;
236	tc_init(&ppcbooke_timecounter);
237}
238