1/* $NetBSD: e500_intr.c,v 1.16.8.1 2012/06/13 19:41:28 riz Exp $ */ 2/*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37#include "opt_mpc85xx.h" 38 39#define __INTR_PRIVATE 40 41#include <sys/cdefs.h> 42__KERNEL_RCSID(0, "$NetBSD: e500_intr.c,v 1.16.8.1 2012/06/13 19:41:28 riz Exp $"); 43 44#include <sys/param.h> 45#include <sys/proc.h> 46#include <sys/intr.h> 47#include <sys/cpu.h> 48#include <sys/kmem.h> 49#include <sys/atomic.h> 50#include <sys/bus.h> 51#include <sys/xcall.h> 52#include <sys/bitops.h> 53 54#include <uvm/uvm_extern.h> 55 56#ifdef __HAVE_FAST_SOFTINTS 57#include <powerpc/softint.h> 58#endif 59 60#include <powerpc/spr.h> 61#include <powerpc/booke/spr.h> 62 63#include <powerpc/booke/cpuvar.h> 64#include <powerpc/booke/e500reg.h> 65#include <powerpc/booke/e500var.h> 66#include <powerpc/booke/openpicreg.h> 67 68#define IPL2CTPR(ipl) ((ipl) + 15 - IPL_HIGH) 69#define CTPR2IPL(ctpr) ((ctpr) - (15 - IPL_HIGH)) 70 71#define IST_PERCPU_P(ist) ((ist) >= IST_TIMER) 72 73struct e500_intr_irq_info { 74 bus_addr_t irq_vpr; 75 bus_addr_t irq_dr; 76 u_int irq_vector; 77}; 78 79struct intr_source { 80 int (*is_func)(void *); 81 void *is_arg; 82 int8_t is_ipl; 83 uint8_t is_ist; 84 uint8_t is_irq; 85 bus_size_t is_vpr; 86 bus_size_t is_dr; 87}; 88 89#define INTR_SOURCE_INITIALIZER \ 90 { .is_func = e500_intr_spurious, .is_arg = NULL, \ 91 .is_irq = -1, .is_ipl = IPL_NONE, .is_ist = IST_NONE, } 92 93struct e500_intr_name { 94 uint8_t in_irq; 95 const char in_name[15]; 96}; 97 98static const struct e500_intr_name e500_onchip_intr_names[] = { 99 { ISOURCE_L2, "l2" }, 100 { ISOURCE_ECM, "ecm" }, 101 { ISOURCE_DDR, "ddr" }, 102 { ISOURCE_LBC, "lbc" }, 103 { ISOURCE_DMA_CHAN1, "dma-chan1" }, 104 { ISOURCE_DMA_CHAN2, "dma-chan2" }, 105 { ISOURCE_DMA_CHAN3, "dma-chan3" }, 106 { ISOURCE_DMA_CHAN4, "dma-chan4" }, 107 { ISOURCE_PCI1, "pci1" }, 108 { ISOURCE_PCIEX2, "pcie2" }, 109 { ISOURCE_PCIEX , "pcie1" }, 110 { ISOURCE_PCIEX3, "pcie3" }, 111 { ISOURCE_USB1, "usb1" }, 112 { ISOURCE_ETSEC1_TX, "etsec1-tx" }, 113 { ISOURCE_ETSEC1_RX, "etsec1-rx" }, 114 { ISOURCE_ETSEC3_TX, "etsec3-tx" }, 115 { ISOURCE_ETSEC3_RX, "etsec3-rx" }, 116 { ISOURCE_ETSEC3_ERR, "etsec3-err" }, 117 { ISOURCE_ETSEC1_ERR, "etsec1-err" }, 118 { ISOURCE_ETSEC2_TX, "etsec2-tx" }, 119 { ISOURCE_ETSEC2_RX, "etsec2-rx" }, 120 { ISOURCE_ETSEC4_TX, "etsec4-tx" }, 121 { ISOURCE_ETSEC4_RX, "etsec4-rx" }, 122 { ISOURCE_ETSEC4_ERR, "etsec4-err" }, 123 { ISOURCE_ETSEC2_ERR, "etsec2-err" }, 124 { ISOURCE_DUART, "duart" }, 125 { ISOURCE_I2C, "i2c" }, 126 { ISOURCE_PERFMON, "perfmon" }, 127 { ISOURCE_SECURITY1, "sec1" }, 128 { ISOURCE_GPIO, "gpio" }, 129 { ISOURCE_SRIO_EWPU, "srio-ewpu" }, 130 { ISOURCE_SRIO_ODBELL, "srio-odbell" }, 131 { ISOURCE_SRIO_IDBELL, "srio-idbell" }, 132 { ISOURCE_SRIO_OMU1, "srio-omu1" }, 133 { ISOURCE_SRIO_IMU1, "srio-imu1" }, 134 { ISOURCE_SRIO_OMU2, "srio-omu2" }, 135 { ISOURCE_SRIO_IMU2, "srio-imu2" }, 136 { ISOURCE_SECURITY2, "sec2" }, 137 { ISOURCE_SPI, "spi" }, 138 { ISOURCE_ETSEC1_PTP, "etsec1-ptp" }, 139 { ISOURCE_ETSEC2_PTP, "etsec2-ptp" }, 140 { ISOURCE_ETSEC3_PTP, "etsec3-ptp" }, 141 { ISOURCE_ETSEC4_PTP, "etsec4-ptp" }, 142 { ISOURCE_ESDHC, "esdhc" }, 143 { 0, "" }, 144}; 145 146const struct e500_intr_name default_external_intr_names[] = { 147 { 0, "" }, 148}; 149 150static const struct e500_intr_name e500_msigroup_intr_names[] = { 151 { 0, "msigroup0" }, 152 { 1, "msigroup1" }, 153 { 2, "msigroup2" }, 154 { 3, "msigroup3" }, 155 { 4, "msigroup4" }, 156 { 5, "msigroup5" }, 157 { 6, "msigroup6" }, 158 { 7, "msigroup7" }, 159 { 0, "" }, 160}; 161 162static const struct e500_intr_name e500_timer_intr_names[] = { 163 { 0, "timer0" }, 164 { 1, "timer1" }, 165 { 2, "timer2" }, 166 { 3, "timer3" }, 167 { 0, "" }, 168}; 169 170static const struct e500_intr_name e500_ipi_intr_names[] = { 171 { 0, "ipi0" }, 172 { 1, "ipi1" }, 173 { 2, "ipi2" }, 174 { 3, "ipi3" }, 175 { 0, "" }, 176}; 177 178static const struct e500_intr_name e500_mi_intr_names[] = { 179 { 0, "mi0" }, 180 { 1, "mi1" }, 181 { 2, "mi2" }, 182 { 3, "mi3" }, 183 { 0, "" }, 184}; 185 186struct e500_intr_info { 187 u_int ii_external_sources; 188 uint32_t ii_onchip_bitmap[2]; 189 u_int ii_onchip_sources; 190 u_int ii_msigroup_sources; 191 u_int ii_ipi_sources; /* per-cpu */ 192 u_int ii_timer_sources; /* per-cpu */ 193 u_int ii_mi_sources; /* per-cpu */ 194 u_int ii_percpu_sources; 195 const struct e500_intr_name *ii_external_intr_names; 196 const struct e500_intr_name *ii_onchip_intr_names; 197 u_int8_t ii_ist_vectors[IST_MAX+1]; 198}; 199 200static kmutex_t e500_intr_lock __cacheline_aligned; 201static struct e500_intr_info e500_intr_info; 202 203#define INTR_INFO_DECL(lc_chip, UC_CHIP) \ 204static const struct e500_intr_info lc_chip##_intr_info = { \ 205 .ii_external_sources = UC_CHIP ## _EXTERNALSOURCES, \ 206 .ii_onchip_bitmap = UC_CHIP ## _ONCHIPBITMAP, \ 207 .ii_onchip_sources = UC_CHIP ## _ONCHIPSOURCES, \ 208 .ii_msigroup_sources = UC_CHIP ## _MSIGROUPSOURCES, \ 209 .ii_timer_sources = UC_CHIP ## _TIMERSOURCES, \ 210 .ii_ipi_sources = UC_CHIP ## _IPISOURCES, \ 211 .ii_mi_sources = UC_CHIP ## _MISOURCES, \ 212 .ii_percpu_sources = UC_CHIP ## _TIMERSOURCES \ 213 + UC_CHIP ## _IPISOURCES + UC_CHIP ## _MISOURCES, \ 214 .ii_external_intr_names = lc_chip ## _external_intr_names, \ 215 .ii_onchip_intr_names = lc_chip ## _onchip_intr_names, \ 216 .ii_ist_vectors = { \ 217 [IST_NONE] = ~0, \ 218 [IST_EDGE] = 0, \ 219 [IST_LEVEL_LOW] = 0, \ 220 [IST_LEVEL_HIGH] = 0, \ 221 [IST_PULSE] = 0, \ 222 [IST_ONCHIP] = UC_CHIP ## _EXTERNALSOURCES, \ 223 [IST_MSIGROUP] = UC_CHIP ## _EXTERNALSOURCES \ 224 + UC_CHIP ## _ONCHIPSOURCES, \ 225 [IST_TIMER] = UC_CHIP ## _EXTERNALSOURCES \ 226 + UC_CHIP ## _ONCHIPSOURCES \ 227 + UC_CHIP ## _MSIGROUPSOURCES, \ 228 [IST_IPI] = UC_CHIP ## _EXTERNALSOURCES \ 229 + UC_CHIP ## _ONCHIPSOURCES \ 230 + UC_CHIP ## _MSIGROUPSOURCES \ 231 + UC_CHIP ## _TIMERSOURCES, \ 232 [IST_MI] = UC_CHIP ## _EXTERNALSOURCES \ 233 + UC_CHIP ## _ONCHIPSOURCES \ 234 + UC_CHIP ## _MSIGROUPSOURCES \ 235 + UC_CHIP ## _TIMERSOURCES \ 236 + UC_CHIP ## _IPISOURCES, \ 237 [IST_MAX] = UC_CHIP ## _EXTERNALSOURCES \ 238 + UC_CHIP ## _ONCHIPSOURCES \ 239 + UC_CHIP ## _MSIGROUPSOURCES \ 240 + UC_CHIP ## _TIMERSOURCES \ 241 + UC_CHIP ## _IPISOURCES \ 242 + UC_CHIP ## _MISOURCES, \ 243 }, \ 244} 245 246#ifdef MPC8536 247#define mpc8536_external_intr_names default_external_intr_names 248const struct e500_intr_name mpc8536_onchip_intr_names[] = { 249 { ISOURCE_SATA2, "sata2" }, 250 { ISOURCE_USB2, "usb2" }, 251 { ISOURCE_USB3, "usb3" }, 252 { ISOURCE_SATA1, "sata1" }, 253 { 0, "" }, 254}; 255 256INTR_INFO_DECL(mpc8536, MPC8536); 257#endif 258 259#ifdef MPC8544 260#define mpc8544_external_intr_names default_external_intr_names 261const struct e500_intr_name mpc8544_onchip_intr_names[] = { 262 { 0, "" }, 263}; 264 265INTR_INFO_DECL(mpc8544, MPC8544); 266#endif 267#ifdef MPC8548 268#define mpc8548_external_intr_names default_external_intr_names 269const struct e500_intr_name mpc8548_onchip_intr_names[] = { 270 { ISOURCE_PCI1, "pci1" }, 271 { ISOURCE_PCI2, "pci2" }, 272 { 0, "" }, 273}; 274 275INTR_INFO_DECL(mpc8548, MPC8548); 276#endif 277#ifdef MPC8555 278#define mpc8555_external_intr_names default_external_intr_names 279const struct e500_intr_name mpc8555_onchip_intr_names[] = { 280 { ISOURCE_PCI2, "pci2" }, 281 { ISOURCE_CPM, "CPM" }, 282 { 0, "" }, 283}; 284 285INTR_INFO_DECL(mpc8555, MPC8555); 286#endif 287#ifdef MPC8568 288#define mpc8568_external_intr_names default_external_intr_names 289const struct e500_intr_name mpc8568_onchip_intr_names[] = { 290 { ISOURCE_QEB_LOW, "QEB low" }, 291 { ISOURCE_QEB_PORT, "QEB port" }, 292 { ISOURCE_QEB_IECC, "QEB iram ecc" }, 293 { ISOURCE_QEB_MUECC, "QEB ram ecc" }, 294 { ISOURCE_TLU1, "tlu1" }, 295 { ISOURCE_QEB_HIGH, "QEB high" }, 296 { 0, "" }, 297}; 298 299INTR_INFO_DECL(mpc8568, MPC8568); 300#endif 301#ifdef MPC8572 302#define mpc8572_external_intr_names default_external_intr_names 303const struct e500_intr_name mpc8572_onchip_intr_names[] = { 304 { ISOURCE_PCIEX3_MPC8572, "pcie3" }, 305 { ISOURCE_FEC, "fec" }, 306 { ISOURCE_PME_GENERAL, "pme" }, 307 { ISOURCE_TLU1, "tlu1" }, 308 { ISOURCE_TLU2, "tlu2" }, 309 { ISOURCE_PME_CHAN1, "pme-chan1" }, 310 { ISOURCE_PME_CHAN2, "pme-chan2" }, 311 { ISOURCE_PME_CHAN3, "pme-chan3" }, 312 { ISOURCE_PME_CHAN4, "pme-chan4" }, 313 { ISOURCE_DMA2_CHAN1, "dma2-chan1" }, 314 { ISOURCE_DMA2_CHAN2, "dma2-chan2" }, 315 { ISOURCE_DMA2_CHAN3, "dma2-chan3" }, 316 { ISOURCE_DMA2_CHAN4, "dma2-chan4" }, 317 { 0, "" }, 318}; 319 320INTR_INFO_DECL(mpc8572, MPC8572); 321#endif 322#ifdef P2020 323#define p20x0_external_intr_names default_external_intr_names 324const struct e500_intr_name p20x0_onchip_intr_names[] = { 325 { ISOURCE_PCIEX3_MPC8572, "pcie3" }, 326 { ISOURCE_DMA2_CHAN1, "dma2-chan1" }, 327 { ISOURCE_DMA2_CHAN2, "dma2-chan2" }, 328 { ISOURCE_DMA2_CHAN3, "dma2-chan3" }, 329 { ISOURCE_DMA2_CHAN4, "dma2-chan4" }, 330 { 0, "" }, 331}; 332 333INTR_INFO_DECL(p20x0, P20x0); 334#endif 335 336static const char ist_names[][12] = { 337 [IST_NONE] = "none", 338 [IST_EDGE] = "edge", 339 [IST_LEVEL_LOW] = "level-", 340 [IST_LEVEL_HIGH] = "level+", 341 [IST_PULSE] = "pulse", 342 [IST_MSI] = "msi", 343 [IST_ONCHIP] = "onchip", 344 [IST_MSIGROUP] = "msigroup", 345 [IST_TIMER] = "timer", 346 [IST_IPI] = "ipi", 347 [IST_MI] = "msgint", 348}; 349 350static struct intr_source *e500_intr_sources; 351static const struct intr_source *e500_intr_last_source; 352 353static void *e500_intr_establish(int, int, int, int (*)(void *), void *); 354static void e500_intr_disestablish(void *); 355static void e500_intr_cpu_attach(struct cpu_info *ci); 356static void e500_intr_cpu_hatch(struct cpu_info *ci); 357static void e500_intr_cpu_send_ipi(cpuid_t, uintptr_t); 358static void e500_intr_init(void); 359static const char *e500_intr_string(int, int); 360static const char *e500_intr_typename(int); 361static void e500_critintr(struct trapframe *tf); 362static void e500_decrintr(struct trapframe *tf); 363static void e500_extintr(struct trapframe *tf); 364static void e500_fitintr(struct trapframe *tf); 365static void e500_wdogintr(struct trapframe *tf); 366static void e500_spl0(void); 367static int e500_splraise(int); 368static void e500_splx(int); 369 370const struct intrsw e500_intrsw = { 371 .intrsw_establish = e500_intr_establish, 372 .intrsw_disestablish = e500_intr_disestablish, 373 .intrsw_init = e500_intr_init, 374 .intrsw_cpu_attach = e500_intr_cpu_attach, 375 .intrsw_cpu_hatch = e500_intr_cpu_hatch, 376 .intrsw_cpu_send_ipi = e500_intr_cpu_send_ipi, 377 .intrsw_string = e500_intr_string, 378 .intrsw_typename = e500_intr_typename, 379 380 .intrsw_critintr = e500_critintr, 381 .intrsw_decrintr = e500_decrintr, 382 .intrsw_extintr = e500_extintr, 383 .intrsw_fitintr = e500_fitintr, 384 .intrsw_wdogintr = e500_wdogintr, 385 386 .intrsw_splraise = e500_splraise, 387 .intrsw_splx = e500_splx, 388 .intrsw_spl0 = e500_spl0, 389 390#ifdef __HAVE_FAST_SOFTINTS 391 .intrsw_softint_init_md = powerpc_softint_init_md, 392 .intrsw_softint_trigger = powerpc_softint_trigger, 393#endif 394}; 395 396static inline uint32_t 397openpic_read(struct cpu_softc *cpu, bus_size_t offset) 398{ 399 400 return bus_space_read_4(cpu->cpu_bst, cpu->cpu_bsh, 401 OPENPIC_BASE + offset); 402} 403 404static inline void 405openpic_write(struct cpu_softc *cpu, bus_size_t offset, uint32_t val) 406{ 407 408 return bus_space_write_4(cpu->cpu_bst, cpu->cpu_bsh, 409 OPENPIC_BASE + offset, val); 410} 411 412static const char * 413e500_intr_external_name_lookup(int irq) 414{ 415 prop_array_t extirqs = board_info_get_object("external-irqs"); 416 prop_string_t irqname = prop_array_get(extirqs, irq); 417 KASSERT(irqname != NULL); 418 KASSERT(prop_object_type(irqname) == PROP_TYPE_STRING); 419 420 return prop_string_cstring_nocopy(irqname); 421} 422 423static const char * 424e500_intr_name_lookup(const struct e500_intr_name *names, int irq) 425{ 426 for (; names->in_name[0] != '\0'; names++) { 427 if (names->in_irq == irq) 428 return names->in_name; 429 } 430 431 return NULL; 432} 433 434static const char * 435e500_intr_onchip_name_lookup(int irq) 436{ 437 const char *name; 438 439 name = e500_intr_name_lookup(e500_intr_info.ii_onchip_intr_names, irq); 440 if (name == NULL) 441 name = e500_intr_name_lookup(e500_onchip_intr_names, irq); 442 443 return name; 444} 445 446static inline void 447e500_splset(struct cpu_info *ci, int ipl) 448{ 449 struct cpu_softc * const cpu = ci->ci_softc; 450 451 //KASSERT(!cpu_intr_p() || ipl >= IPL_VM); 452 KASSERT((curlwp->l_pflag & LP_INTR) == 0 || ipl != IPL_NONE); 453#if 0 454 u_int ctpr = ipl; 455 KASSERT(openpic_read(cpu, OPENPIC_CTPR) == ci->ci_cpl); 456#elif 0 457 u_int old_ctpr = (ci->ci_cpl >= IPL_VM ? 15 : ci->ci_cpl); 458 u_int ctpr = (ipl >= IPL_VM ? 15 : ipl); 459 KASSERT(openpic_read(cpu, OPENPIC_CTPR) == old_ctpr); 460#else 461 const u_int ctpr = IPL2CTPR(ipl); 462 KASSERT(openpic_read(cpu, OPENPIC_CTPR) == IPL2CTPR(ci->ci_cpl)); 463#endif 464 openpic_write(cpu, OPENPIC_CTPR, ctpr); 465 KASSERT(openpic_read(cpu, OPENPIC_CTPR) == ctpr); 466 ci->ci_cpl = ipl; 467} 468 469static void 470e500_spl0(void) 471{ 472 wrtee(0); 473 474 struct cpu_info * const ci = curcpu(); 475 476#ifdef __HAVE_FAST_SOFTINTS 477 if (__predict_false(ci->ci_data.cpu_softints != 0)) { 478 e500_splset(ci, IPL_HIGH); 479 powerpc_softint(ci, IPL_NONE, 480 (vaddr_t)__builtin_return_address(0)); 481 } 482#endif /* __HAVE_FAST_SOFTINTS */ 483 e500_splset(ci, IPL_NONE); 484 485 wrtee(PSL_EE); 486} 487 488static void 489e500_splx(int ipl) 490{ 491 struct cpu_info * const ci = curcpu(); 492 const int old_ipl = ci->ci_cpl; 493 494 /* if we paniced because of watchdog, PSL_CE will be clear. */ 495 KASSERT(panicstr != NULL || (mfmsr() & PSL_CE)); 496 497 if (ipl == old_ipl) 498 return; 499 500 if (__predict_false(ipl > old_ipl)) { 501 printf("%s: %p: cpl=%u: ignoring splx(%u) to raise ipl\n", 502 __func__, __builtin_return_address(0), old_ipl, ipl); 503 if (old_ipl == IPL_NONE) 504 Debugger(); 505 } 506 507 // const 508 register_t msr = wrtee(0); 509#ifdef __HAVE_FAST_SOFTINTS 510 const u_int softints = ci->ci_data.cpu_softints & (IPL_SOFTMASK << ipl); 511 if (__predict_false(softints != 0)) { 512 e500_splset(ci, IPL_HIGH); 513 powerpc_softint(ci, ipl, 514 (vaddr_t)__builtin_return_address(0)); 515 } 516#endif /* __HAVE_FAST_SOFTINTS */ 517 e500_splset(ci, ipl); 518#if 1 519 if (ipl < IPL_VM && old_ipl >= IPL_VM) 520 msr = PSL_EE; 521#endif 522 wrtee(msr); 523} 524 525static int 526e500_splraise(int ipl) 527{ 528 struct cpu_info * const ci = curcpu(); 529 const int old_ipl = ci->ci_cpl; 530 531 /* if we paniced because of watchdog, PSL_CE will be clear. */ 532 KASSERT(panicstr != NULL || (mfmsr() & PSL_CE)); 533 534 if (old_ipl < ipl) { 535 //const 536 register_t msr = wrtee(0); 537 e500_splset(ci, ipl); 538#if 1 539 if (old_ipl < IPL_VM && ipl >= IPL_VM) 540 msr = 0; 541#endif 542 wrtee(msr); 543 } else if (ipl == IPL_NONE) { 544 panic("%s: %p: cpl=%u: attempt to splraise(IPL_NONE)", 545 __func__, __builtin_return_address(0), old_ipl); 546#if 0 547 } else if (old_ipl > ipl) { 548 printf("%s: %p: cpl=%u: ignoring splraise(%u) to lower ipl\n", 549 __func__, __builtin_return_address(0), old_ipl, ipl); 550#endif 551 } 552 553 return old_ipl; 554} 555 556static int 557e500_intr_spurious(void *arg) 558{ 559 return 0; 560} 561 562static bool 563e500_intr_irq_info_get(struct cpu_info *ci, u_int irq, int ipl, int ist, 564 struct e500_intr_irq_info *ii) 565{ 566 const struct e500_intr_info * const info = &e500_intr_info; 567 bool ok; 568 569#if DEBUG > 2 570 printf("%s(%p,irq=%u,ipl=%u,ist=%u,%p)\n", __func__, ci, irq, ipl, ist, ii); 571#endif 572 573 if (ipl < IPL_VM || ipl > IPL_HIGH) { 574#if DEBUG > 2 575 printf("%s:%d ipl=%u\n", __func__, __LINE__, ipl); 576#endif 577 return false; 578 } 579 580 if (ist <= IST_NONE || ist >= IST_MAX) { 581#if DEBUG > 2 582 printf("%s:%d ist=%u\n", __func__, __LINE__, ist); 583#endif 584 return false; 585 } 586 587 ii->irq_vector = irq + info->ii_ist_vectors[ist]; 588 if (IST_PERCPU_P(ist) && ist != IST_IPI) 589 ii->irq_vector += ci->ci_cpuid * info->ii_percpu_sources; 590 591 switch (ist) { 592 default: 593 ii->irq_vpr = OPENPIC_EIVPR(irq); 594 ii->irq_dr = OPENPIC_EIDR(irq); 595 ok = irq < info->ii_external_sources 596 && (ist == IST_EDGE 597 || ist == IST_LEVEL_LOW 598 || ist == IST_LEVEL_HIGH); 599 break; 600 case IST_PULSE: 601 ok = false; 602 break; 603 case IST_ONCHIP: 604 ii->irq_vpr = OPENPIC_IIVPR(irq); 605 ii->irq_dr = OPENPIC_IIDR(irq); 606 ok = irq < 32 * __arraycount(info->ii_onchip_bitmap); 607#if DEBUG > 2 608 printf("%s: irq=%u: ok=%u\n", __func__, irq, ok); 609#endif 610 ok = ok && (info->ii_onchip_bitmap[irq/32] & (1 << (irq & 31))); 611#if DEBUG > 2 612 printf("%s: %08x%08x -> %08x%08x: ok=%u\n", __func__, 613 irq < 32 ? 0 : (1 << irq), irq < 32 ? (1 << irq) : 0, 614 info->ii_onchip_bitmap[1], info->ii_onchip_bitmap[0], 615 ok); 616#endif 617 break; 618 case IST_MSIGROUP: 619 ii->irq_vpr = OPENPIC_MSIVPR(irq); 620 ii->irq_dr = OPENPIC_MSIDR(irq); 621 ok = irq < info->ii_msigroup_sources 622 && ipl == IPL_VM; 623 break; 624 case IST_TIMER: 625 ii->irq_vpr = OPENPIC_GTVPR(ci->ci_cpuid, irq); 626 ii->irq_dr = OPENPIC_GTDR(ci->ci_cpuid, irq); 627 ok = irq < info->ii_timer_sources; 628#if DEBUG > 2 629 printf("%s: IST_TIMER irq=%u: ok=%u\n", __func__, irq, ok); 630#endif 631 break; 632 case IST_IPI: 633 ii->irq_vpr = OPENPIC_IPIVPR(irq); 634 ii->irq_dr = OPENPIC_IPIDR(irq); 635 ok = irq < info->ii_ipi_sources; 636 break; 637 case IST_MI: 638 ii->irq_vpr = OPENPIC_MIVPR(irq); 639 ii->irq_dr = OPENPIC_MIDR(irq); 640 ok = irq < info->ii_mi_sources; 641 break; 642 } 643 644 return ok; 645} 646 647static const char * 648e500_intr_string(int irq, int ist) 649{ 650 struct cpu_info * const ci = curcpu(); 651 struct cpu_softc * const cpu = ci->ci_softc; 652 struct e500_intr_irq_info ii; 653 654 if (!e500_intr_irq_info_get(ci, irq, IPL_VM, ist, &ii)) 655 return NULL; 656 657 return cpu->cpu_evcnt_intrs[ii.irq_vector].ev_name; 658} 659 660__CTASSERT(__arraycount(ist_names) == IST_MAX); 661 662static const char * 663e500_intr_typename(int ist) 664{ 665 if (IST_NONE <= ist && ist < IST_MAX) 666 return ist_names[ist]; 667 668 return NULL; 669} 670 671static void * 672e500_intr_cpu_establish(struct cpu_info *ci, int irq, int ipl, int ist, 673 int (*handler)(void *), void *arg) 674{ 675 struct cpu_softc * const cpu = ci->ci_softc; 676 struct e500_intr_irq_info ii; 677 678 KASSERT(ipl >= IPL_VM && ipl <= IPL_HIGH); 679 KASSERT(ist > IST_NONE && ist < IST_MAX && ist != IST_MSI); 680 681 if (!e500_intr_irq_info_get(ci, irq, ipl, ist, &ii)) { 682 printf("%s: e500_intr_irq_info_get(%p,%u,%u,%u,%p) failed\n", 683 __func__, ci, irq, ipl, ist, &ii); 684 return NULL; 685 } 686 687 struct intr_source * const is = &e500_intr_sources[ii.irq_vector]; 688 mutex_enter(&e500_intr_lock); 689 if (is->is_ipl != IPL_NONE) 690 return NULL; 691 692 is->is_func = handler; 693 is->is_arg = arg; 694 is->is_ipl = ipl; 695 is->is_ist = ist; 696 is->is_irq = irq; 697 is->is_vpr = ii.irq_vpr; 698 is->is_dr = ii.irq_dr; 699 700 uint32_t vpr = VPR_PRIORITY_MAKE(IPL2CTPR(ipl)) 701 | VPR_VECTOR_MAKE(((ii.irq_vector + 1) << 4) | ipl) 702 | (ist == IST_LEVEL_LOW 703 ? VPR_LEVEL_LOW 704 : (ist == IST_LEVEL_HIGH 705 ? VPR_LEVEL_HIGH 706 : (ist == IST_ONCHIP 707 ? VPR_P_HIGH 708 : 0))); 709 710 /* 711 * All interrupts go to the primary except per-cpu interrupts which get 712 * routed to the appropriate cpu. 713 */ 714 uint32_t dr = openpic_read(cpu, ii.irq_dr); 715 716 dr |= 1 << (IST_PERCPU_P(ist) ? ci->ci_cpuid : 0); 717 718 /* 719 * Update the vector/priority and destination registers keeping the 720 * interrupt masked. 721 */ 722 const register_t msr = wrtee(0); /* disable interrupts */ 723 openpic_write(cpu, ii.irq_vpr, vpr | VPR_MSK); 724 openpic_write(cpu, ii.irq_dr, dr); 725 726 /* 727 * Now unmask the interrupt. 728 */ 729 openpic_write(cpu, ii.irq_vpr, vpr); 730 731 wrtee(msr); /* re-enable interrupts */ 732 733 mutex_exit(&e500_intr_lock); 734 735 return is; 736} 737 738static void * 739e500_intr_establish(int irq, int ipl, int ist, 740 int (*handler)(void *), void *arg) 741{ 742 return e500_intr_cpu_establish(curcpu(), irq, ipl, ist, handler, arg); 743} 744 745static void 746e500_intr_disestablish(void *vis) 747{ 748 struct cpu_softc * const cpu = curcpu()->ci_softc; 749 struct intr_source * const is = vis; 750 struct e500_intr_irq_info ii; 751 752 KASSERT(e500_intr_sources <= is); 753 KASSERT(is < e500_intr_last_source); 754 KASSERT(!cpu_intr_p()); 755 756 bool ok = e500_intr_irq_info_get(curcpu(), is->is_irq, is->is_ipl, 757 is->is_ist, &ii); 758 (void)ok; /* appease gcc */ 759 KASSERT(ok); 760 KASSERT(is - e500_intr_sources == ii.irq_vector); 761 762 mutex_enter(&e500_intr_lock); 763 /* 764 * Mask the source using the mask (MSK) bit in the vector/priority reg. 765 */ 766 uint32_t vpr = openpic_read(cpu, ii.irq_vpr); 767 openpic_write(cpu, ii.irq_vpr, VPR_MSK | vpr); 768 769 /* 770 * Wait for the Activity (A) bit for the source to be cleared. 771 */ 772 while (openpic_read(cpu, ii.irq_vpr) & VPR_A) 773 ; 774 775 /* 776 * Now the source can be modified. 777 */ 778 openpic_write(cpu, ii.irq_dr, 0); /* stop delivery */ 779 openpic_write(cpu, ii.irq_vpr, VPR_MSK); /* mask/reset it */ 780 781 *is = (struct intr_source)INTR_SOURCE_INITIALIZER; 782 783 mutex_exit(&e500_intr_lock); 784} 785 786static void 787e500_critintr(struct trapframe *tf) 788{ 789 panic("%s: srr0/srr1=%#lx/%#lx", __func__, tf->tf_srr0, tf->tf_srr1); 790} 791 792static void 793e500_decrintr(struct trapframe *tf) 794{ 795 panic("%s: srr0/srr1=%#lx/%#lx", __func__, tf->tf_srr0, tf->tf_srr1); 796} 797 798static void 799e500_fitintr(struct trapframe *tf) 800{ 801 panic("%s: srr0/srr1=%#lx/%#lx", __func__, tf->tf_srr0, tf->tf_srr1); 802} 803 804static void 805e500_wdogintr(struct trapframe *tf) 806{ 807 mtspr(SPR_TSR, TSR_ENW|TSR_WIS); 808 panic("%s: tf=%p tb=%"PRId64" srr0/srr1=%#lx/%#lx", __func__, tf, 809 mftb(), tf->tf_srr0, tf->tf_srr1); 810} 811 812static void 813e500_extintr(struct trapframe *tf) 814{ 815 struct cpu_info * const ci = curcpu(); 816 struct cpu_softc * const cpu = ci->ci_softc; 817 const int old_ipl = ci->ci_cpl; 818 819 /* if we paniced because of watchdog, PSL_CE will be clear. */ 820 KASSERT(panicstr != NULL || (mfmsr() & PSL_CE)); 821 822#if 0 823// printf("%s(%p): idepth=%d enter\n", __func__, tf, ci->ci_idepth); 824 if ((register_t)tf >= (register_t)curlwp->l_addr + USPACE 825 || (register_t)tf < (register_t)curlwp->l_addr + NBPG) { 826 printf("%s(entry): pid %d.%d (%s): srr0/srr1=%#lx/%#lx: invalid tf addr %p\n", 827 __func__, curlwp->l_proc->p_pid, curlwp->l_lid, 828 curlwp->l_proc->p_comm, tf->tf_srr0, tf->tf_srr1, tf); 829 } 830#endif 831 832 833 ci->ci_data.cpu_nintr++; 834 tf->tf_cf.cf_idepth = ci->ci_idepth++; 835 cpu->cpu_pcpls[ci->ci_idepth] = old_ipl; 836#if 1 837 if (mfmsr() & PSL_EE) 838 panic("%s(%p): MSR[EE] is on (%#lx)!", __func__, tf, mfmsr()); 839 if (old_ipl == IPL_HIGH 840 || IPL2CTPR(old_ipl) != openpic_read(cpu, OPENPIC_CTPR)) 841 panic("%s(%p): old_ipl(%u) == IPL_HIGH(%u) " 842 "|| old_ipl + %u != OPENPIC_CTPR (%u)", 843 __func__, tf, old_ipl, IPL_HIGH, 844 15 - IPL_HIGH, openpic_read(cpu, OPENPIC_CTPR)); 845#else 846 if (old_ipl >= IPL_VM) 847 panic("%s(%p): old_ipl(%u) >= IPL_VM(%u) CTPR=%u", 848 __func__, tf, old_ipl, IPL_VM, openpic_read(cpu, OPENPIC_CTPR)); 849#endif 850 851 for (;;) { 852 /* 853 * Find out the pending interrupt. 854 */ 855 if (mfmsr() & PSL_EE) 856 panic("%s(%p): MSR[EE] turned on (%#lx)!", __func__, tf, mfmsr()); 857 if (IPL2CTPR(old_ipl) != openpic_read(cpu, OPENPIC_CTPR)) 858 panic("%s(%p): %d: old_ipl(%u) + %u != OPENPIC_CTPR (%u)", 859 __func__, tf, __LINE__, old_ipl, 860 15 - IPL_HIGH, openpic_read(cpu, OPENPIC_CTPR)); 861 const uint32_t iack = openpic_read(cpu, OPENPIC_IACK); 862#ifdef DIAGNOSTIC 863 const int ipl = iack & 0xf; 864#endif 865 const int irq = (iack >> 4) - 1; 866#if 0 867 printf("%s: iack=%d ipl=%d irq=%d <%s>\n", 868 __func__, iack, ipl, irq, 869 (iack != IRQ_SPURIOUS ? 870 cpu->cpu_evcnt_intrs[irq].ev_name : "spurious")); 871#endif 872 if (IPL2CTPR(old_ipl) != openpic_read(cpu, OPENPIC_CTPR)) 873 panic("%s(%p): %d: old_ipl(%u) + %u != OPENPIC_CTPR (%u)", 874 __func__, tf, __LINE__, old_ipl, 875 15 - IPL_HIGH, openpic_read(cpu, OPENPIC_CTPR)); 876 if (iack == IRQ_SPURIOUS) 877 break; 878 879 struct intr_source * const is = &e500_intr_sources[irq]; 880 if (__predict_true(is < e500_intr_last_source)) { 881 /* 882 * Timer interrupts get their argument overriden with 883 * the pointer to the trapframe. 884 */ 885 KASSERT(is->is_ipl == ipl); 886 void *arg = (is->is_ist == IST_TIMER ? tf : is->is_arg); 887 if (is->is_ipl <= old_ipl) 888 panic("%s(%p): %s (%u): is->is_ipl (%u) <= old_ipl (%u)\n", 889 __func__, tf, 890 cpu->cpu_evcnt_intrs[irq].ev_name, irq, 891 is->is_ipl, old_ipl); 892 KASSERT(is->is_ipl > old_ipl); 893 e500_splset(ci, is->is_ipl); /* change IPL */ 894 if (__predict_false(is->is_func == NULL)) { 895 aprint_error_dev(ci->ci_dev, 896 "interrupt from unestablished irq %d\n", 897 irq); 898 } else { 899 int (*func)(void *) = is->is_func; 900 wrtee(PSL_EE); 901 int rv = (*func)(arg); 902 wrtee(0); 903#if DEBUG > 2 904 printf("%s: %s handler %p(%p) returned %d\n", 905 __func__, 906 cpu->cpu_evcnt_intrs[irq].ev_name, 907 func, arg, rv); 908#endif 909 if (rv == 0) 910 cpu->cpu_evcnt_spurious_intr.ev_count++; 911 } 912 e500_splset(ci, old_ipl); /* restore IPL */ 913 cpu->cpu_evcnt_intrs[irq].ev_count++; 914 } else { 915 aprint_error_dev(ci->ci_dev, 916 "interrupt from illegal irq %d\n", irq); 917 cpu->cpu_evcnt_spurious_intr.ev_count++; 918 } 919 /* 920 * If this is a nested interrupt, simply ack it and exit 921 * because the loop we interrupted will complete looking 922 * for interrupts. 923 */ 924 if (mfmsr() & PSL_EE) 925 panic("%s(%p): MSR[EE] left on (%#lx)!", __func__, tf, mfmsr()); 926 if (IPL2CTPR(old_ipl) != openpic_read(cpu, OPENPIC_CTPR)) 927 panic("%s(%p): %d: old_ipl(%u) + %u != OPENPIC_CTPR (%u)", 928 __func__, tf, __LINE__, old_ipl, 929 15 - IPL_HIGH, openpic_read(cpu, OPENPIC_CTPR)); 930 931 openpic_write(cpu, OPENPIC_EOI, 0); 932 if (IPL2CTPR(old_ipl) != openpic_read(cpu, OPENPIC_CTPR)) 933 panic("%s(%p): %d: old_ipl(%u) + %u != OPENPIC_CTPR (%u)", 934 __func__, tf, __LINE__, old_ipl, 935 15 - IPL_HIGH, openpic_read(cpu, OPENPIC_CTPR)); 936 if (ci->ci_idepth > 0) 937 break; 938 } 939 940 ci->ci_idepth--; 941 942#ifdef __HAVE_FAST_SOFTINTS 943 /* 944 * Before exiting, deal with any softints that need to be dealt with. 945 */ 946 const u_int softints = ci->ci_data.cpu_softints & (IPL_SOFTMASK << old_ipl); 947 if (__predict_false(softints != 0)) { 948 KASSERT(old_ipl < IPL_VM); 949 e500_splset(ci, IPL_HIGH); /* pop to high */ 950 powerpc_softint(ci, old_ipl, /* deal with them */ 951 tf->tf_srr0); 952 e500_splset(ci, old_ipl); /* and drop back */ 953 } 954#endif /* __HAVE_FAST_SOFTINTS */ 955#if 1 956 KASSERT(ci->ci_cpl == old_ipl); 957#else 958 e500_splset(ci, old_ipl); /* and drop back */ 959#endif 960 961 /* 962 * If we interrupted while power-saving and we need to exit idle, 963 * we need to clear PSL_POW so we won't go back into power-saving. 964 */ 965 if (__predict_false(tf->tf_srr1 & PSL_POW) && ci->ci_want_resched) 966 tf->tf_srr1 &= ~PSL_POW; 967 968// printf("%s(%p): idepth=%d exit\n", __func__, tf, ci->ci_idepth); 969} 970 971static void 972e500_intr_init(void) 973{ 974 struct cpu_info * const ci = curcpu(); 975 struct cpu_softc * const cpu = ci->ci_softc; 976 const uint32_t frr = openpic_read(cpu, OPENPIC_FRR); 977 const u_int nirq = FRR_NIRQ_GET(frr) + 1; 978// const u_int ncpu = FRR_NCPU_GET(frr) + 1; 979 struct intr_source *is; 980 struct e500_intr_info * const ii = &e500_intr_info; 981 982 const uint16_t svr = (mfspr(SPR_SVR) & ~0x80000) >> 16; 983 switch (svr) { 984#ifdef MPC8536 985 case SVR_MPC8536v1 >> 16: 986 *ii = mpc8536_intr_info; 987 break; 988#endif 989#ifdef MPC8544 990 case SVR_MPC8544v1 >> 16: 991 *ii = mpc8544_intr_info; 992 break; 993#endif 994#ifdef MPC8548 995 case SVR_MPC8543v1 >> 16: 996 case SVR_MPC8548v1 >> 16: 997 *ii = mpc8548_intr_info; 998 break; 999#endif 1000#ifdef MPC8555 1001 case SVR_MPC8541v1 >> 16: 1002 case SVR_MPC8555v1 >> 16: 1003 *ii = mpc8555_intr_info; 1004 break; 1005#endif 1006#ifdef MPC8568 1007 case SVR_MPC8568v1 >> 16: 1008 *ii = mpc8568_intr_info; 1009 break; 1010#endif 1011#ifdef MPC8572 1012 case SVR_MPC8572v1 >> 16: 1013 *ii = mpc8572_intr_info; 1014 break; 1015#endif 1016#ifdef P2020 1017 case SVR_P2010v2 >> 16: 1018 case SVR_P2020v2 >> 16: 1019 *ii = p20x0_intr_info; 1020 break; 1021#endif 1022 default: 1023 panic("%s: don't know how to deal with SVR %#lx", 1024 __func__, mfspr(SPR_SVR)); 1025 } 1026 1027 /* 1028 * We need to be in mixed mode. 1029 */ 1030 openpic_write(cpu, OPENPIC_GCR, GCR_M); 1031 1032 /* 1033 * Make we and the openpic both agree about the current SPL level. 1034 */ 1035 e500_splset(ci, ci->ci_cpl); 1036 1037 /* 1038 * Allow the required number of interrupt sources. 1039 */ 1040 is = kmem_zalloc(nirq * sizeof(*is), KM_SLEEP); 1041 KASSERT(is); 1042 e500_intr_sources = is; 1043 e500_intr_last_source = is + nirq; 1044 1045 /* 1046 * Initialize all the external interrupts as active low. 1047 */ 1048 for (u_int irq = 0; irq < e500_intr_info.ii_external_sources; irq++) { 1049 openpic_write(cpu, OPENPIC_EIVPR(irq), 1050 VPR_VECTOR_MAKE(irq) | VPR_LEVEL_LOW); 1051 } 1052} 1053 1054static void 1055e500_idlespin(void) 1056{ 1057 KASSERTMSG(curcpu()->ci_cpl == IPL_NONE, 1058 "%s: cpu%u: ci_cpl (%d) != 0", __func__, cpu_number(), 1059 curcpu()->ci_cpl); 1060 KASSERTMSG(CTPR2IPL(openpic_read(curcpu()->ci_softc, OPENPIC_CTPR)) == IPL_NONE, 1061 "%s: cpu%u: CTPR (%d) != IPL_NONE", __func__, cpu_number(), 1062 CTPR2IPL(openpic_read(curcpu()->ci_softc, OPENPIC_CTPR))); 1063 KASSERT(mfmsr() & PSL_EE); 1064 1065 if (powersave > 0) 1066 mtmsr(mfmsr() | PSL_POW); 1067} 1068 1069static void 1070e500_intr_cpu_attach(struct cpu_info *ci) 1071{ 1072 struct cpu_softc * const cpu = ci->ci_softc; 1073 const char * const xname = device_xname(ci->ci_dev); 1074 1075 const u_int32_t frr = openpic_read(cpu, OPENPIC_FRR); 1076 const u_int nirq = FRR_NIRQ_GET(frr) + 1; 1077// const u_int ncpu = FRR_NCPU_GET(frr) + 1; 1078 1079 const struct e500_intr_info * const info = &e500_intr_info; 1080 1081 cpu->cpu_clock_gtbcr = OPENPIC_GTBCR(ci->ci_cpuid, E500_CLOCK_TIMER); 1082 1083 cpu->cpu_evcnt_intrs = 1084 kmem_zalloc(nirq * sizeof(cpu->cpu_evcnt_intrs[0]), KM_SLEEP); 1085 KASSERT(cpu->cpu_evcnt_intrs); 1086 1087 struct evcnt *evcnt = cpu->cpu_evcnt_intrs; 1088 for (size_t j = 0; j < info->ii_external_sources; j++, evcnt++) { 1089 const char *name = e500_intr_external_name_lookup(j); 1090 evcnt_attach_dynamic(evcnt, EVCNT_TYPE_INTR, NULL, xname, name); 1091 } 1092 KASSERT(evcnt == cpu->cpu_evcnt_intrs + info->ii_ist_vectors[IST_ONCHIP]); 1093 for (size_t j = 0; j < info->ii_onchip_sources; j++, evcnt++) { 1094 if (info->ii_onchip_bitmap[j / 32] & __BIT(j & 31)) { 1095 const char *name = e500_intr_onchip_name_lookup(j); 1096 if (name != NULL) { 1097 evcnt_attach_dynamic(evcnt, EVCNT_TYPE_INTR, 1098 NULL, xname, name); 1099#ifdef DIAGNOSTIC 1100 } else { 1101 printf("%s: missing evcnt for onchip irq %zu\n", 1102 __func__, j); 1103#endif 1104 } 1105 } 1106 } 1107 1108 KASSERT(evcnt == cpu->cpu_evcnt_intrs + info->ii_ist_vectors[IST_MSIGROUP]); 1109 for (size_t j = 0; j < info->ii_msigroup_sources; j++, evcnt++) { 1110 evcnt_attach_dynamic(evcnt, EVCNT_TYPE_INTR, 1111 NULL, xname, e500_msigroup_intr_names[j].in_name); 1112 } 1113 1114 KASSERT(evcnt == cpu->cpu_evcnt_intrs + info->ii_ist_vectors[IST_TIMER]); 1115 evcnt += ci->ci_cpuid * info->ii_percpu_sources; 1116 for (size_t j = 0; j < info->ii_timer_sources; j++, evcnt++) { 1117 evcnt_attach_dynamic(evcnt, EVCNT_TYPE_INTR, 1118 NULL, xname, e500_timer_intr_names[j].in_name); 1119 } 1120 1121 for (size_t j = 0; j < info->ii_ipi_sources; j++, evcnt++) { 1122 evcnt_attach_dynamic(evcnt, EVCNT_TYPE_INTR, 1123 NULL, xname, e500_ipi_intr_names[j].in_name); 1124 } 1125 1126 for (size_t j = 0; j < info->ii_mi_sources; j++, evcnt++) { 1127 evcnt_attach_dynamic(evcnt, EVCNT_TYPE_INTR, 1128 NULL, xname, e500_mi_intr_names[j].in_name); 1129 } 1130 1131 ci->ci_idlespin = e500_idlespin; 1132} 1133 1134static void 1135e500_intr_cpu_send_ipi(cpuid_t target, uint32_t ipimsg) 1136{ 1137 struct cpu_info * const ci = curcpu(); 1138 struct cpu_softc * const cpu = ci->ci_softc; 1139 uint32_t dstmask; 1140 1141 if (target >= CPU_MAXNUM) { 1142 CPU_INFO_ITERATOR cii; 1143 struct cpu_info *dst_ci; 1144 1145 KASSERT(target == IPI_DST_NOTME || target == IPI_DST_ALL); 1146 1147 dstmask = 0; 1148 for (CPU_INFO_FOREACH(cii, dst_ci)) { 1149 if (target == IPI_DST_ALL || ci != dst_ci) { 1150 dstmask |= 1 << cpu_index(ci); 1151 if (ipimsg) 1152 atomic_or_32(&dst_ci->ci_pending_ipis, 1153 ipimsg); 1154 } 1155 } 1156 } else { 1157 struct cpu_info * const dst_ci = cpu_lookup(target); 1158 KASSERT(dst_ci != NULL); 1159 KASSERTMSG(target == cpu_index(dst_ci), 1160 "%s: target (%lu) != cpu_index(cpu%u)", 1161 __func__, target, cpu_index(dst_ci)); 1162 dstmask = (1 << target); 1163 if (ipimsg) 1164 atomic_or_32(&dst_ci->ci_pending_ipis, ipimsg); 1165 } 1166 1167 openpic_write(cpu, OPENPIC_IPIDR(0), dstmask); 1168} 1169 1170typedef void (*ipifunc_t)(void); 1171 1172#ifdef __HAVE_PREEEMPTION 1173static void 1174e500_ipi_kpreempt(void) 1175{ 1176 poowerpc_softint_trigger(1 << IPL_NONE); 1177} 1178#endif 1179 1180static const ipifunc_t e500_ipifuncs[] = { 1181 [ilog2(IPI_XCALL)] = xc_ipi_handler, 1182 [ilog2(IPI_HALT)] = e500_ipi_halt, 1183#ifdef __HAVE_PREEMPTION 1184 [ilog2(IPI_KPREEMPT)] = e500_ipi_kpreempt, 1185#endif 1186 [ilog2(IPI_TLB1SYNC)] = e500_tlb1_sync, 1187}; 1188 1189static int 1190e500_ipi_intr(void *v) 1191{ 1192 struct cpu_info * const ci = curcpu(); 1193 1194 ci->ci_ev_ipi.ev_count++; 1195 1196 uint32_t pending_ipis = atomic_swap_32(&ci->ci_pending_ipis, 0); 1197 for (u_int ipi = 31; pending_ipis != 0; ipi--, pending_ipis <<= 1) { 1198 const u_int bits = __builtin_clz(pending_ipis); 1199 ipi -= bits; 1200 pending_ipis <<= bits; 1201 KASSERT(e500_ipifuncs[ipi] != NULL); 1202 (*e500_ipifuncs[ipi])(); 1203 } 1204 1205 return 1; 1206} 1207 1208static void 1209e500_intr_cpu_hatch(struct cpu_info *ci) 1210{ 1211 /* 1212 * Establish clock interrupt for this CPU. 1213 */ 1214 if (e500_intr_cpu_establish(ci, E500_CLOCK_TIMER, IPL_CLOCK, IST_TIMER, 1215 e500_clock_intr, NULL) == NULL) 1216 panic("%s: failed to establish clock interrupt!", __func__); 1217 1218 /* 1219 * Establish the IPI interrupts for this CPU. 1220 */ 1221 if (e500_intr_cpu_establish(ci, 0, IPL_VM, IST_IPI, e500_ipi_intr, 1222 NULL) == NULL) 1223 panic("%s: failed to establish ipi interrupt!", __func__); 1224 1225 /* 1226 * Enable watchdog interrupts. 1227 */ 1228 uint32_t tcr = mfspr(SPR_TCR); 1229 tcr |= TCR_WIE; 1230 mtspr(SPR_TCR, tcr); 1231} 1232