1/*	$NetBSD: mips_3x30.c,v 1.14 2011/03/10 17:30:12 tsutsui Exp $	*/
2
3/*
4 * Copyright (c) 2000 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Wayne Knowles
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 *    notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 *    notice, this list of conditions and the following disclaimer in the
17 *    documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32#define	__INTR_PRIVATE
33#include <sys/cdefs.h>
34__KERNEL_RCSID(0, "$NetBSD: mips_3x30.c,v 1.14 2011/03/10 17:30:12 tsutsui Exp $");
35
36#include <sys/param.h>
37#include <sys/systm.h>
38#include <sys/device.h>
39#include <sys/proc.h>
40#include <sys/kernel.h>
41#include <sys/cpu.h>
42#include <sys/intr.h>
43
44#include <machine/locore.h>
45#include <machine/trap.h>
46#include <machine/psl.h>
47#include <machine/mainboard.h>
48#include <machine/sysconf.h>
49
50/* Local functions */
51void pizazz_init(void);
52void pizazz_intr(uint32_t, vaddr_t, uint32_t);
53int  pizazz_level0_intr(void *);
54void pizazz_level5_intr(uint32_t, vaddr_t);
55void pizazz_intr_establish (int, int (*)(void *), void *);
56
57#define INT_MASK_FPU MIPS_INT_MASK_3
58
59void
60pizazz_init(void)
61{
62	platform.iobus = "obio";
63	platform.cons_init = NULL;
64	platform.iointr = pizazz_intr;
65	platform.intr_establish = pizazz_intr_establish;
66
67	ipl_sr_map = mipsco_ipl_sr_map;
68
69	pizazz_intr_establish(SYS_INTR_LEVEL0, pizazz_level0_intr, NULL);
70
71	strcpy(cpu_model, "Mips 3230 Magnum (Pizazz)");
72	cpuspeed = 25;
73}
74
75#define	HANDLE_INTR(intr, mask)					\
76	do {							\
77		if (ipending & (mask)) {			\
78			CALL_INTR(intr);			\
79		}						\
80	} while (0)
81
82void
83pizazz_intr(uint32_t status, vaddr_t pc, uint32_t ipending)
84{
85	/* handle clock interrupts ASAP */
86	if (ipending & MIPS_INT_MASK_2) {	        /* Timer Interrupt */
87	        void rambo_clkintr (struct clockframe *);
88	        struct clockframe cf;
89
90		cf.pc = pc;
91		cf.sr = status;
92		cf.intr = (curcpu()->ci_idepth > 1);
93
94		rambo_clkintr(&cf);
95	}
96
97	if (ipending & MIPS_INT_MASK_5)		/* level 5 interrupt */
98		pizazz_level5_intr(status, pc);
99
100	HANDLE_INTR(SYS_INTR_FDC,	MIPS_INT_MASK_4);
101	HANDLE_INTR(SYS_INTR_SCSI,	MIPS_INT_MASK_1);
102	HANDLE_INTR(SYS_INTR_LEVEL0,	MIPS_INT_MASK_0);
103
104#if !defined(NOFPU)
105	/* FPU nofiticaition */
106	if (ipending & INT_MASK_FPU) {
107		if (!USERMODE(status))
108			panic("kernel used FPU: PC %x, SR %x",
109			      pc, status);
110		mips_fpu_intr(pc, curlwp->l_md.md_utf);
111	}
112#endif
113}
114
115/*
116 * Level 0 interrupt handler
117 *
118 * Pizazz shares Lance, SCC, Expansion slot and Keyboard on level 0
119 * A secondary interrupt status register shows the real interrupt source
120 */
121int
122pizazz_level0_intr(void *arg)
123{
124	register int stat;
125
126	/* stat register is active low */
127	stat = ~*(volatile u_char *)INTREG_0;
128
129	if (stat & INT_ExpSlot)
130		CALL_INTR(SYS_INTR_ATBUS);
131
132	if (stat & INT_Lance)
133		CALL_INTR(SYS_INTR_ETHER);
134
135	if (stat & INT_SCC)
136		CALL_INTR(SYS_INTR_SCC0);
137
138	return 0;
139}
140
141/*
142 * Motherboard Parity Error
143 */
144void
145pizazz_level5_intr(uint32_t status, vaddr_t pc)
146{
147	u_int32_t ereg;
148
149	ereg = *(u_int32_t *)RAMBO_ERREG;
150
151	printf("interrupt: pc=%p sr=%x\n", (void *)pc, status);
152	printf("parity error: %p mask: 0x%x\n", (void *)ereg, ereg & 0xf);
153	panic("memory fault");
154}
155
156void
157pizazz_intr_establish(int level, int (*func) (void *), void *arg)
158{
159	if (level < 0 || level >= MAX_INTR_COOKIES)
160		panic("invalid interrupt level");
161
162	if (intrtab[level].ih_fun != NULL)
163		panic("cannot share interrupt %d", level);
164
165	intrtab[level].ih_fun = func;
166	intrtab[level].ih_arg = arg;
167}
168