1/*	$NetBSD: intr.h,v 1.18 2009/04/13 09:37:50 he Exp $	*/
2
3/*
4 * Copyright (c) 1998 Jonathan Stone.  All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 *    must display the following acknowledgement:
16 *	This product includes software developed by Jonathan Stone for
17 *      the NetBSD Project.
18 * 4. The name of the author may not be used to endorse or promote products
19 *    derived from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33#ifndef _MACHINE_INTR_H_
34#define _MACHINE_INTR_H_
35
36#include <mips/intr.h>
37
38#ifdef _KERNEL
39#ifdef __INTR_PRIVATE
40#include <sys/evcnt.h>
41#include <mips/cpuregs.h>
42
43/*
44 * nesting interrupt masks.
45 */
46#define MIPS_INT_MASK_SPL_SOFT0	MIPS_SOFT_INT_MASK_0
47#define MIPS_INT_MASK_SPL_SOFT1	(MIPS_SOFT_INT_MASK_1|MIPS_INT_MASK_SPL_SOFT0)
48#define MIPS_INT_MASK_SPL0	(MIPS_INT_MASK_0|MIPS_INT_MASK_SPL_SOFT1)
49#define MIPS_INT_MASK_SPL1	(MIPS_INT_MASK_1|MIPS_INT_MASK_SPL0)
50#define MIPS_INT_MASK_SPL2	(MIPS_INT_MASK_2|MIPS_INT_MASK_SPL1)
51#define MIPS_INT_MASK_SPL3	(MIPS_INT_MASK_3|MIPS_INT_MASK_SPL2)
52#define MIPS_INT_MASK_SPL4	(MIPS_INT_MASK_4|MIPS_INT_MASK_SPL3)
53#define MIPS_INT_MASK_SPL5	(MIPS_INT_MASK_5|MIPS_INT_MASK_SPL4)
54
55struct mipsco_intrhand {
56	LIST_ENTRY(mipsco_intrhand) ih_q;
57	int	(*ih_fun)(void *);
58	void	 *ih_arg;
59	struct	mipsco_intr *ih_intrhead;
60	int	ih_pending;
61};
62
63struct mipsco_intr {
64	LIST_HEAD(,mipsco_intrhand) intr_q;
65	struct	evcnt ih_evcnt;
66	unsigned long intr_siq;
67};
68
69extern const struct ipl_sr_map mipsco_ipl_sr_map;
70extern struct mipsco_intrhand intrtab[];
71#define	CALL_INTR(lev)	((*intrtab[lev].ih_fun)(intrtab[lev].ih_arg))
72
73#define MAX_INTR_COOKIES 16
74
75#endif /* __INTR_PRIVATE */
76
77#define SYS_INTR_LEVEL0	0
78#define SYS_INTR_LEVEL1	1
79#define SYS_INTR_LEVEL2	2
80#define SYS_INTR_LEVEL3	3
81#define SYS_INTR_LEVEL4	4
82#define SYS_INTR_LEVEL5	5
83#define SYS_INTR_SCSI	6
84#define SYS_INTR_TIMER	7
85#define SYS_INTR_ETHER	8
86#define SYS_INTR_SCC0	9
87#define SYS_INTR_FDC	10
88#define SYS_INTR_ATBUS	11
89
90#endif /* _KERNEL */
91#endif /* _MACHINE_INTR_H_ */
92