1/* $NetBSD: com_aubus_reg.h,v 1.1.2.1 2006/06/15 16:40:43 gdamore Exp $ */ 2 3/* copyright */ 4 5#undef COM_FREQ /* relative to CPU clock speed on Au1X00 */ 6 7/* 8 * Alchemy Semi Au1X00 UART registers 9 */ 10 11#define AUCOM_RXDATA 0x00 /* receive data register (R) */ 12#define AUCOM_TXDATA 0x04 /* transmit data register (W) */ 13#define AUCOM_IER 0x08 /* interrupt enable (R/W) */ 14#define AUCOM_IIR 0x0c /* interrupt identification (R) */ 15#define AUCOM_FIFO 0x10 /* FIFO control (R/W) */ 16#define AUCOM_LCTL 0x14 /* line control register (R/W) */ 17#define AUCOM_CFCR 0x14 /* line control register (R/W) */ 18#define AUCOM_MCR 0x18 /* modem control register (R/W) */ 19#define AUCOM_LSR 0x1c /* line status register (R) */ 20#define AUCOM_MSR 0x20 /* modem status register (R) */ 21#define AUCOM_DLB 0x28 /* divisor latch (16bit) (R/W) */ 22#define AUCOM_MODCTL 0x100 /* module control register (R/W) */ 23 24#define UMC_CE 0x2 /* module clock enable */ 25#define UMC_ME 0x1 /* module enable */ 26 27#define AUCOM_NPORTS 0x104 28