1/* 2 * Copyright (c) 2001, 2002 Greg Hughes. All rights reserved. 3 * Copyright (c) 1999 PocketBSD Project. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27/* 28 * DSIU (debug serial interface unit) register definitions 29 */ 30 31/* Port Change Register */ 32#define DSIUPORT_REG_W 0x00 33#define DSIUPORT_CDDIN (1 << 3) 34#define DSIUPORT_CDDOUT (1 << 2) 35#define DSIUPORT_CDRTS (1 << 1) 36#define DSIUPORT_CDCTS (1 << 0) 37 38/* Modem Control Register */ 39#define DSIUMODEM_REG_W 0x02 40#define DSIUMODEM_DRTS (1 << 1) 41#define DSIUMODEM_DCTS (1 << 0) 42 43/* Asynchronous Mode 0 Register */ 44#define DSIUASIM00_REG_W 0x04 45#define DSIUASIM00_RXE0 (1 << 6) 46#define DSIUASIM00_PS0_MASK (3 << 4) 47#define DSIUASIM00_PS00 (1 << 4) 48#define DSIUASIM00_PS01 (1 << 5) 49#define DSIUASIM00_CL0 (1 << 3) 50#define DSIUASIM00_SL0 (1 << 2) 51 52/* Asynchronous Mode 1 Register */ 53#define DSIUASIM01_REG_W 0x06 54#define DSIUASIM01_EBS0 (1 << 0) 55 56/* Recceive Buffer Register (Extended) */ 57#define DSIURXB0R_REG_W 0x08 58#define DSIURXB0R_RXB0_MASK (0x1FF << 0) 59 60/* Receive Buffer Register */ 61#define DSIURXB0L_REG_W 0x0A 62#define DSIURXB0L_RXB0L_MASK (0xFF << 0) 63 64/* Transmit Data Register (Extended) */ 65#define DSIUTXS0R_REG_W 0x0C 66#define DSIUTXS0R_TXS0_MASK (0x1FF << 0) 67 68/* Transmit Data Register */ 69#define DSIUTXS0L_REG_W 0x0E 70#define DSIUTXS0L_TXS0L_MASK (0xFF << 0) 71 72/* Status Register */ 73#define DSIUASIS0_REG_W 0x10 74#define DSIUASIS0_SOT0 (1 << 7) 75#define DSIUASIS0_PE0 (1 << 2) 76#define DSIUASIS0_FE0 (1 << 1) 77#define DSIUASIS0_OVE0 (1 << 0) 78 79/* Debug SIU Interrupt Register */ 80#define DSIUINTR0_REG_W 0x12 81#define DSIUINTR0_INTDCD (1 << 3) 82#define DSIUINTR0_INTSER0 (1 << 2) 83#define DSIUINTR0_INTSR0 (1 << 1) 84#define DSIUINTR0_INTST0 (1 << 0) 85 86/* Baud rate Generator Prescaler Mode Register */ 87#define DSIUBPRM0_REG_W 0x16 88#define DSIUBPRM0_BRCE0 (1 << 7) 89#define DSIUBPRM0_BPR0_MASK (7 << 0) 90#define DSIUBPRM0_BPR00 (1 << 0) 91#define DSIUBPRM0_BPR01 (1 << 1) 92#define DSIUBPRM0_BPR02 (1 << 2) 93 94/* Debug SIU Reset Register */ 95#define DSIURESET_REG_W 0x18 96#define DSIURESET_DSIURST (1 << 0) 97