1/* $NetBSD: interrupt.c,v 1.17 2010/12/20 00:25:34 matt Exp $ */ 2 3/*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32#include <sys/cdefs.h> 33__KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.17 2010/12/20 00:25:34 matt Exp $"); 34 35#include "opt_vr41xx.h" 36#include "opt_tx39xx.h" 37 38#define __INTR_PRIVATE 39 40#include <sys/param.h> 41#include <sys/malloc.h> 42#include <sys/intr.h> 43 44#include <machine/sysconf.h> 45 46void 47intr_init(void) 48{ 49 50 ipl_sr_map = CPUISMIPS3 ? __ipl_sr_map_vr : __ipl_sr_map_tx; 51} 52 53#if defined(VR41XX) && defined(TX39XX) 54/* 55 * cpu_intr: 56 * 57 * handle MIPS CPU interrupt. 58 * if VR41XX only or TX39XX only kernel, directly jump to each handler 59 * (tx/tx39icu.c, vr/vr.c), don't use this dispather. 60 * 61 */ 62void 63cpu_intr(int ppl, vaddr_t pc, uint32_t status) 64{ 65 66 (*platform.cpu_intr)(ppl, pc, status); 67} 68#endif /* VR41XX && TX39XX */ 69