1/* $NetBSD: ipaq_pcic.c,v 1.20 2011/07/19 15:37:38 dyoung Exp $ */ 2 3/*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Ichiro FUKUHARA (ichiro@ichiro.org). 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32#include <sys/cdefs.h> 33__KERNEL_RCSID(0, "$NetBSD: ipaq_pcic.c,v 1.20 2011/07/19 15:37:38 dyoung Exp $"); 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/types.h> 38#include <sys/conf.h> 39#include <sys/file.h> 40#include <sys/device.h> 41#include <sys/kernel.h> 42#include <sys/kthread.h> 43#include <sys/malloc.h> 44#include <sys/bus.h> 45 46#include <dev/pcmcia/pcmciachip.h> 47#include <dev/pcmcia/pcmciavar.h> 48 49#include <hpcarm/dev/ipaq_saipvar.h> 50#include <hpcarm/dev/ipaq_pcicreg.h> 51#include <hpcarm/dev/ipaq_gpioreg.h> 52 53#include <arm/sa11x0/sa11x0_gpioreg.h> 54#include <arm/sa11x0/sa11x0_var.h> 55#include <arm/sa11x0/sa11xx_pcicvar.h> 56 57#include "ipaqpcic.h" 58 59static int ipaqpcic_match(device_t, cfdata_t, void *); 60static void ipaqpcic_attach(device_t, device_t, void *); 61static int ipaqpcic_print(void *, const char *); 62 63static int ipaqpcic_read(struct sapcic_socket *, int); 64static void ipaqpcic_write(struct sapcic_socket *, int, int); 65static void ipaqpcic_set_power(struct sapcic_socket *, int); 66static void ipaqpcic_clear_intr(int); 67static void *ipaqpcic_intr_establish(struct sapcic_socket *, int, 68 int (*)(void *), void *); 69static void ipaqpcic_intr_disestablish(struct sapcic_socket *, void *); 70 71struct ipaqpcic_softc { 72 struct sapcic_softc sc_pc; 73 bus_space_handle_t sc_ioh; 74 struct ipaq_softc *sc_parent; 75 struct sapcic_socket sc_socket[2]; 76}; 77 78static void ipaqpcic_init(struct ipaqpcic_softc *); 79 80static struct sapcic_tag ipaqpcic_functions = { 81 ipaqpcic_read, 82 ipaqpcic_write, 83 ipaqpcic_set_power, 84 ipaqpcic_clear_intr, 85 ipaqpcic_intr_establish, 86 ipaqpcic_intr_disestablish 87}; 88 89CFATTACH_DECL_NEW(ipaqpcic, sizeof(struct ipaqpcic_softc), 90 ipaqpcic_match, ipaqpcic_attach, NULL, NULL); 91 92static int 93ipaqpcic_match(device_t parent, cfdata_t cf, void *aux) 94{ 95 return (1); 96} 97 98static void 99ipaqpcic_attach(device_t parent, device_t self, void *aux) 100{ 101 int i; 102 struct pcmciabus_attach_args paa; 103 struct ipaqpcic_softc *sc = device_private(self); 104 struct ipaq_softc *psc = device_private(parent); 105 106 aprint_normal("\n"); 107 108 sc->sc_pc.sc_dev = self; 109 sc->sc_pc.sc_iot = psc->sc_iot; 110 sc->sc_ioh = psc->sc_ioh; 111 sc->sc_parent = psc; 112 113 ipaqpcic_init(sc); 114 115 for(i = 0; i < 2; i++) { 116 sc->sc_socket[i].sc = (struct sapcic_softc *)sc; 117 sc->sc_socket[i].socket = i; 118 sc->sc_socket[i].pcictag_cookie = psc; 119 sc->sc_socket[i].pcictag = &ipaqpcic_functions; 120 sc->sc_socket[i].event_thread = NULL; 121 sc->sc_socket[i].event = 0; 122 sc->sc_socket[i].laststatus = SAPCIC_CARD_INVALID; 123 sc->sc_socket[i].shutdown = 0; 124 125 paa.paa_busname = "pcmcia"; 126 paa.pct = (pcmcia_chipset_tag_t)&sa11x0_pcmcia_functions; 127 paa.pch = (pcmcia_chipset_handle_t)&sc->sc_socket[i]; 128 129 sc->sc_socket[i].pcmcia = 130 config_found_ia(sc->sc_pc.sc_dev, "pcmciabus", 131 &paa, ipaqpcic_print); 132 133 sa11x0_intr_establish((sa11x0_chipset_tag_t)psc, 134 i ? IRQ_CD1 : IRQ_CD0, 135 1, IPL_BIO, sapcic_intr, 136 &sc->sc_socket[i]); 137 138 /* schedule kthread creation */ 139 sapcic_kthread_create(&sc->sc_socket[i]); 140 141#if 0 /* XXX */ 142 /* establish_intr should be after creating the kthread */ 143 config_interrupt(&sc->sc_socket[i], ipaqpcic_config_intr); 144#endif 145 } 146} 147 148static int 149ipaqpcic_print(void *aux, const char *name) 150{ 151 return (UNCONF); 152} 153 154static void 155ipaqpcic_init(struct ipaqpcic_softc *sc) 156{ 157 int cr; 158 159 /* All those are inputs */ 160 cr = bus_space_read_4(sc->sc_pc.sc_iot, sc->sc_parent->sc_gpioh, SAGPIO_PDR); 161 cr &= ~(GPIO_H3600_PCMCIA_CD0 | GPIO_H3600_PCMCIA_CD1 | GPIO_H3600_PCMCIA_IRQ0 | 162 GPIO_H3600_PCMCIA_IRQ1); 163 bus_space_write_4(sc->sc_pc.sc_iot, sc->sc_parent->sc_gpioh, SAGPIO_PDR, cr); 164 165 sc->sc_parent->ipaq_egpio |= 166 EGPIO_H3600_OPT_NVRAM_ON | EGPIO_H3600_OPT_ON ; 167 sc->sc_parent->ipaq_egpio &= 168 ~(EGPIO_H3600_CARD_RESET | EGPIO_H3600_OPT_RESET); 169 bus_space_write_2(sc->sc_pc.sc_iot, sc->sc_parent->sc_egpioh, 170 0, sc->sc_parent->ipaq_egpio); 171} 172 173static int 174ipaqpcic_read(struct sapcic_socket *so, int reg) 175{ 176 int cr, bit; 177 struct ipaqpcic_softc *sc = (struct ipaqpcic_softc *)so->sc; 178 179 cr = bus_space_read_4(sc->sc_pc.sc_iot, sc->sc_parent->sc_gpioh, SAGPIO_PLR); 180 181 switch (reg) { 182 case SAPCIC_STATUS_CARD: 183 bit = (so->socket ? GPIO_H3600_PCMCIA_CD0 : 184 GPIO_H3600_PCMCIA_CD1) & cr; 185 if (!bit) 186 return SAPCIC_CARD_INVALID; 187 else 188 return SAPCIC_CARD_VALID; 189 case SAPCIC_STATUS_VS1: 190 case SAPCIC_STATUS_VS2: 191 case SAPCIC_STATUS_READY: 192 bit = (so->socket ? GPIO_H3600_PCMCIA_IRQ0: 193 GPIO_H3600_PCMCIA_IRQ1); 194 return (bit & cr); 195 default: 196 panic("ipaqpcic_read: bogus register"); 197 } 198} 199 200static void 201ipaqpcic_write(struct sapcic_socket *so, int reg, int arg) 202{ 203 int s; 204 struct ipaqpcic_softc *sc = (struct ipaqpcic_softc *)so->sc; 205 206 s = splhigh(); 207 switch (reg) { 208 case SAPCIC_CONTROL_RESET: 209 sc->sc_parent->ipaq_egpio |= EGPIO_H3600_CARD_RESET; 210 break; 211 case SAPCIC_CONTROL_LINEENABLE: 212 case SAPCIC_CONTROL_WAITENABLE: 213 case SAPCIC_CONTROL_POWERSELECT: 214 break; 215 216 default: 217 splx(s); 218 panic("ipaqpcic_write: bogus register"); 219 } 220 bus_space_write_2(sc->sc_pc.sc_iot, sc->sc_parent->sc_egpioh, 0, 221 sc->sc_parent->ipaq_egpio); 222 splx(s); 223} 224 225static void 226ipaqpcic_set_power(struct sapcic_socket *so, int arg) 227{ 228 int s; 229 struct ipaqpcic_softc *sc = (struct ipaqpcic_softc *)so->sc; 230 231 s = splbio(); 232 switch (arg) { 233 case SAPCIC_POWER_OFF: 234 sc->sc_parent->ipaq_egpio &= 235 ~(EGPIO_H3600_OPT_NVRAM_ON | EGPIO_H3600_OPT_ON); 236 break; 237 case SAPCIC_POWER_3V: 238 case SAPCIC_POWER_5V: 239 sc->sc_parent->ipaq_egpio |= 240 EGPIO_H3600_OPT_NVRAM_ON | EGPIO_H3600_OPT_ON; 241 break; 242 default: 243 panic("ipaqpcic_set_power: bogus arg"); 244 } 245 bus_space_write_2(sc->sc_pc.sc_iot, sc->sc_parent->sc_egpioh, 246 0, sc->sc_parent->ipaq_egpio); 247 splx(s); 248} 249 250static void 251ipaqpcic_clear_intr(int arg) 252{ 253} 254 255static void * 256ipaqpcic_intr_establish(struct sapcic_socket *so, int level, 257 int (*ih_fun)(void *), void *ih_arg) 258{ 259 int irq; 260 261 irq = so->socket ? IRQ_IRQ0 : IRQ_IRQ1; 262 return (sa11x0_intr_establish((sa11x0_chipset_tag_t)so->pcictag_cookie, 263 irq-16, 1, level, ih_fun, ih_arg)); 264} 265 266static void 267ipaqpcic_intr_disestablish(struct sapcic_socket *so, void *ih) 268{ 269 sa11x0_intr_disestablish((sa11x0_chipset_tag_t)so->pcictag_cookie, ih); 270} 271