1/* $NetBSD: pdc.h,v 1.19 2011/06/30 20:09:30 wiz Exp $ */ 2 3/* $OpenBSD: pdc.h,v 1.35 2007/07/15 20:03:48 kettenis Exp $ */ 4 5/* 6 * Copyright (c) 1990 mt Xinu, Inc. All rights reserved. 7 * Copyright (c) 1990,1991,1992,1994 University of Utah. All rights reserved. 8 * 9 * Permission to use, copy, modify and distribute this software is hereby 10 * granted provided that (1) source code retains these copyright, permission, 11 * and disclaimer notices, and (2) redistributions including binaries 12 * reproduce the notices in supporting documentation, and (3) all advertising 13 * materials mentioning features or use of this software display the following 14 * acknowledgement: ``This product includes software developed by the 15 * Computer Systems Laboratory at the University of Utah.'' 16 * 17 * Copyright (c) 1990 mt Xinu, Inc. 18 * This file may be freely distributed in any form as long as 19 * this copyright notice is included. 20 * MTXINU, THE UNIVERSITY OF UTAH, AND CSL PROVIDE THIS SOFTWARE ``AS 21 * IS'' AND WITHOUT ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, 22 * WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND 23 * FITNESS FOR A PARTICULAR PURPOSE. 24 * 25 * CSL requests users of this software to return to csl-dist@cs.utah.edu any 26 * improvements that they make and grant CSL redistribution rights. 27 * 28 * Utah $Hdr: pdc.h 1.12 94/12/14$ 29 * Author: Jeff Forys (CSS), Dave Slattengren (mtXinu) 30 */ 31 32#ifndef _MACHINE_PDC_H_ 33#define _MACHINE_PDC_H_ 34 35/* 36 * Definitions for interaction with "Processor Dependent Code", 37 * which is a set of ROM routines used to provide information to the OS. 38 * Also includes definitions for the layout of "Page Zero" memory when 39 * boot code is invoked. 40 * 41 * Glossary: 42 * PDC: Processor Dependent Code (ROM or copy of ROM). 43 * IODC: I/O Dependent Code (module-type dependent code). 44 * IPL: Boot program (loaded into memory from boot device). 45 * HPA: Hard Physical Address (hardwired address). 46 * SPA: Soft Physical Address (reconfigurable address). 47 * 48 * 49 * 50 * 51 * Definitions for talking to IODC (I/O Dependent Code). 52 * 53 * The PDC is used to load I/O Dependent Code from a particular module. 54 * I/O Dependent Code is module-type dependent software which provides 55 * a uniform way to identify, initialize, and access a module (and in 56 * some cases, their devices). 57 */ 58 59/* 60 * Our Initial Memory Module is laid out as follows. 61 * 62 * 0x000 +--------------------+ 63 * | Page Zero (iomod.h)| 64 * 0x800 +--------------------+ 65 * | | 66 * | | 67 * | PDC | 68 * | | 69 * | | 70 * MEM_FREE +--------------------+ 71 * | | 72 * | Console IODC | 73 * | | 74 * MEM_FREE+64k +--------------------+ 75 * | | 76 * | Boot Device IODC | 77 * | | 78 * IPL_START +--------------------+ 79 * | | 80 * | IPL Code or Kernel | 81 * | | 82 * +--------------------+ 83 * 84 * Restrictions: 85 * MEM_FREE (pagezero.mem_free) can be no greater than 32K. 86 * The PDC may use up to MEM_FREE + 32K (for Console & Boot IODC). 87 * IPL_START must be less than or equal to 64K. 88 * 89 * The IPL (boot) Code is immediately relocated to RELOC (check 90 * "../stand/Makefile") to make way for the Kernel. 91 */ 92 93#define IODC_MAXSIZE (64 * 1024) /* maximum size of IODC */ 94#define IODC_MINIOSIZ 64 /* minimum buffer size for IODC call */ 95#define IODC_MAXIOSIZ (64 * 1024) /* maximum buffer size for IODC call */ 96 97#define PDC_ALIGNMENT __attribute__ ((__aligned__(64))) 98#define PDC_STACKSIZE (2*NBPG) /* PDC spec says 7K. */ 99 100 101/* 102 * The PDC Entry Points and their arguments... 103 */ 104 105#define PDC_POW_FAIL 1 /* prepare for power failure */ 106#define PDC_POW_FAIL_DFLT 0 107 108#define PDC_CHASSIS 2 /* update chassis display (see below) */ 109#define PDC_CHASSIS_DISP 0 /* update display */ 110#define PDC_CHASSIS_WARN 1 /* return warnings */ 111#define PDC_CHASSIS_ALL 2 /* update display & return warnings */ 112#define PDC_CHASSIS_INFO 128 /* return led/lcd info */ 113 114#define PDC_PIM 3 /* access Processor Internal Memory */ 115#define PDC_PIM_HPMC 0 /* read High Pri Mach Chk data */ 116#define PDC_PIM_SIZE 1 /* return size */ 117#define PDC_PIM_LPMC 2 /* read Low Pri Mach Chk data */ 118#define PDC_PIM_SBD 3 /* read soft boot data */ 119#define PDC_PIM_TOC 4 /* read TOC data (used to use HPMC) */ 120 121#define PDC_MODEL 4 /* processor model number info */ 122#define PDC_MODEL_INFO 0 /* processor model number info */ 123#define PDC_MODEL_BOOTID 1 /* set BOOT_ID of processor */ 124#define PDC_MODEL_COMP 2 /* return component version numbers */ 125#define PDC_MODEL_MODEL 3 /* return system model information */ 126#define PDC_MODEL_ENSPEC 4 /* enable product-specific instrs */ 127#define PDC_MODEL_DISPEC 5 /* disable product-specific instrs */ 128#define PDC_MODEL_CPUID 6 /* return CPU versions */ 129#define PDC_MODEL_CAPABILITIES 7 /* return capabilities */ 130#define PDC_MODEL_GETBOOTSTOPTS 8 /* return boot test options */ 131#define PDC_MODEL_SETBOOTSTOPTS 9 /* set boot test options */ 132 133#define PDC_CACHE 5 /* return cache and TLB params */ 134#define PDC_CACHE_DFLT 0 /* return parameters */ 135#define PDC_CACHE_SETCS 1 /* set coherence state */ 136#define PDC_CACHE_GETSPIDB 2 /* get space-id bits */ 137 138#define PDC_HPA 6 /* return HPA of processor */ 139#define PDC_HPA_DFLT 0 140#define PDC_HPA_MODULES 1 141 142#define PDC_COPROC 7 /* return co-processor configuration */ 143#define PDC_COPROC_DFLT 0 144 145#define PDC_IODC 8 /* talk to IODC */ 146#define PDC_IODC_READ 0 /* read IODC entry point */ 147#define IODC_DATA 0 /* get first 16 bytes from mod IODC */ 148#define IODC_INIT 3 /* initialize (see options below) */ 149#define IODC_INIT_FIRST 2 /* find first device on module */ 150#define IODC_INIT_NEXT 3 /* find subsequent devices on module */ 151#define IODC_INIT_ALL 4 /* initialize module and device */ 152#define IODC_INIT_DEV 5 /* initialize device */ 153#define IODC_INIT_MOD 6 /* initialize module */ 154#define IODC_INIT_MSG 9 /* return error message(s) */ 155#define IODC_INIT_STR 20 /* find device w/ spec in string */ 156#define IODC_IO 4 /* perform I/O (see options below) */ 157#define IODC_IO_READ 0 /* read from boot device */ 158#define IODC_IO_WRITE 1 /* write to boot device */ 159#define IODC_IO_CONSIN 2 /* read from console */ 160#define IODC_IO_CONSOUT 3 /* write to conosle */ 161#define IODC_IO_CLOSE 4 /* close device */ 162#define IODC_IO_MSG 9 /* return error message(s) */ 163#define IODC_SPA 5 /* get extended SPA information */ 164#define IODC_SPA_DFLT 0 /* return SPA information */ 165#define IODC_TEST 8 /* perform self tests */ 166#define IODC_TEST_INFO 0 /* return test information */ 167#define IODC_TEST_STEP 1 /* execute a particular test */ 168#define IODC_TEST_TEST 2 /* describe a test section */ 169#define IODC_TEST_MSG 9 /* return error message(s) */ 170#define PDC_IODC_NINIT 2 /* non-destructive init */ 171#define PDC_IODC_DINIT 3 /* destructive init */ 172#define PDC_IODC_MEMERR 4 /* check for memory errors */ 173#define PDC_IODC_IMEMMASTER 5 /* interlieved memory master ID */ 174 175#define PDC_TOD 9 /* access time-of-day clock */ 176#define PDC_TOD_READ 0 /* read TOD clock */ 177#define PDC_TOD_WRITE 1 /* write TOD clock */ 178#define PDC_TOD_ITIMER 2 /* calibrate Interval Timer (CR16) */ 179 180#define PDC_STABLE 10 /* access Stable Storage (SS) */ 181#define PDC_STABLE_READ 0 /* read SS */ 182#define PDC_STABLE_WRITE 1 /* write SS */ 183#define PDC_STABLE_SIZE 2 /* return size of SS */ 184#define PDC_STABLE_VRFY 3 /* verify contents of SS */ 185#define PDC_STABLE_INIT 4 /* initialize SS */ 186 187#define PDC_NVM 11 /* access Non-Volatile Memory (NVM) */ 188#define PDC_NVM_READ 0 /* read NVM */ 189#define PDC_NVM_WRITE 1 /* write NVM */ 190#define PDC_NVM_SIZE 2 /* return size of NVM */ 191#define PDC_NVM_VRFY 3 /* verify contents of NVM */ 192#define PDC_NVM_INIT 4 /* initialize NVM */ 193 194#define PDC_ADD_VALID 12 /* check address for validity */ 195#define PDC_ADD_VALID_DFLT 0 196 197#define PDC_BUS_BAD 13 /* verify Error Detection Circuitry (EDC) */ 198#define PDC_BUS_BAD_DLFT 0 199 200#define PDC_DEBUG 14 /* return address of PDC debugger */ 201#define PDC_DEBUG_DFLT 0 202 203#define PDC_INSTR 15 /* return instr that invokes PDCE_CHECK */ 204#define PDC_INSTR_DFLT 0 205 206#define PDC_PROC 16 /* stop currently executing processor */ 207#define PDC_PROC_STOP 0 208#define PDC_PROC_RENDEZVOUS 1 209 210#define PDC_CONF 17 /* (de)configure a module */ 211#define PDC_CONF_DECONF 0 /* deconfigure module */ 212#define PDC_CONF_RECONF 1 /* reconfigure module */ 213#define PDC_CONF_INFO 2 /* get config informaion */ 214 215#define PDC_BLOCK_TLB 18 /* Manage Block TLB entries (BTLB) */ 216#define PDC_BTLB_DEFAULT 0 /* Return BTLB configuration info */ 217#define PDC_BTLB_INSERT 1 /* Insert a BTLB entry */ 218#define PDC_BTLB_PURGE 2 /* Purge a BTLB entry */ 219#define PDC_BTLB_PURGE_ALL 3 /* Purge all BTLB entries */ 220 221#define PDC_TLB 19 /* Manage Hardware TLB handling */ 222#define PDC_TLB_INFO 0 /* Return HW-TLB configuration info */ 223#define PDC_TLB_CONFIG 1 /* Set HW-TLB pdir base and size */ 224 225#define PDC_TLB_CURRPDE 1 /* cr28 points to current pde on miss */ 226#define PDC_TLB_RESERVD 3 /* reserved */ 227#define PDC_TLB_NEXTPDE 5 /* cr28 points to next pde on miss */ 228#define PDC_TLB_WORD3 7 /* cr28 is word 3 of 16 byte pde */ 229 230#define PDC_PSW 21 /* manage default values of configurable psw bits */ 231#define PDC_PSW_GETMASK 0 /* get mask */ 232#define PDC_PSW_DEFAULTS 1 /* get default bits values */ 233#define PDC_PSW_SETDEFAULTS 2 /* set default bits values */ 234 235#define PDC_SYSTEM_MAP 22 /* map system modules */ 236#define PDC_SYSTEM_MAP_FIND_MOD 0 /* find module by index */ 237#define PDC_SYSTEM_MAP_FIND_ADDR 1 /* fetch list of addresses */ 238#define PDC_SYSTEM_MAP_TRANS_PATH 2 /* get hpa from devpath */ 239 240#define PDC_SOFT_POWER 23 /* support for soft power switch */ 241#define PDC_SOFT_POWER_INFO 0 /* get info about soft power switch */ 242#define PDC_SOFT_POWER_ENABLE 1 /* enable/disable soft power switch */ 243 244#define PDC_PAT_CELL 64 /* cell operations */ 245#define PDC_PAT_CELL_GETID 0 /* get cell id number */ 246#define PDC_PAT_CELL_GETINFO 1 /* get cell info */ 247#define PDC_PAT_CELL_MODULE 2 /* get module info */ 248#define PDC_PAT_IOVIEW 0 249#define PDC_PAT_PAVIEW 1 250 251#define PDC_PAT_CHASSIS 65 /* chassis log ops */ 252#define PDC_PAT_CHASSIS_WRITE 0 253#define PDC_PAT_CHASSIS_READ 1 254 255#define PDC_PAT_CPU 67 256 257#define PDC_PAT_EVENT 68 258 259#define PDC_PAT_HPMC 70 260 261#define PDC_PAT_IO 71 /* online services for IO modules */ 262#define PDC_PAT_IO_GET_PCI_RTSZ 15 263#define PDC_PAT_IO_GET_PCI_RT 16 264 265#define PDC_PAT_MEM 72 266 267#define PDC_PAT_NVRAM 73 268 269#define PDC_PAT_PROTDOM 74 270 271#define PDC_MEMMAP 128 /* hp700: return page information */ 272#define PDC_MEMMAP_HPA 0 /* map module # to HPA */ 273 274#define PDC_EEPROM 129 /* Hversion dependent */ 275#define PDC_EEPROM_READ_WORD 0 276#define PDC_EEPROM_WRITE_WORD 1 277#define PDC_EEPROM_READ_BYTE 2 278#define PDC_EEPROM_WRITE_BYTE 3 279 280#define PDC_IO 135 281#define PDC_IO_READ_AND_CLEAR_ERRORS 0 282#define PDC_IO_RESET 1 283#define PDC_IO_RESET_DEVICES 2 284 285#define PDC_BROADCAST_RESET 136 286#define PDC_DO_RESET 0 287#define PDC_DO_FIRM_TEST_RESET 1 288#define PDC_BR_RECONFIGURATION 2 289 290#define PDC_LAN_STATION_ID 138 /* Hversion dependent mechanism for */ 291#define PDC_LAN_STATION_ID_READ 0 /* getting the lan station address */ 292 293#define PDC_PCI_INDEX 147 /* PCI rt access */ 294#define PDC_PCI_GET_INT_TBL_SZ 13 295#define PDC_PCI_GET_INT_TBL 14 296 297#define PDC_ERR_OK 0 /* operation complete */ 298#define PDC_ERR_WARNING 3 /* OK, but warning */ 299#define PDC_ERR_NOPROC -1 /* no such procedure */ 300#define PDC_ERR_NOPT -2 /* no such option */ 301#define PDC_ERR_COMPL -3 /* unable to complete w/o error */ 302#define PDC_ERR_NMOD -5 /* module not found */ 303#define PDC_ERR_EOD -9 /* end of device list */ 304#define PDC_ERR_INVAL -10 /* invalid argument */ 305#define PDC_ERR_PFAIL -12 /* aborted by powerfail */ 306 307#if !defined(_LOCORE) 308 309struct iomod; 310 311typedef int (*pdcio_t)(int, int, ...); 312typedef int (*iodcio_t)(struct iomod *, int, ...); 313 314/* 315 * Commonly used PDC calls and the structures they return. 316 */ 317 318/* 319 * Device path specifications used by PDC. 320 */ 321struct device_path { 322 u_char dp_flags; /* see bit definitions below */ 323#define PZF_AUTOBOOT 0x80 /* These two are PDC flags for how to locate */ 324#define PZF_AUTOSEARCH 0x40 /* the "boot device" */ 325#define PZF_TIMER 0x0f /* power of 2 # secs "boot timer" (0 == dflt) */ 326#define PZF_BITS "\020\010autoboot\07autosearch" 327 328 char dp_bc[6]; /* Bus Converter routing info to a specific */ 329 /* I/O adaptor (< 0 means none, > 63 resvd) */ 330 char dp_mod; /* fixed field of specified module */ 331 int dp_layers[6]; /* device-specific info (ctlr #, unit # ...) */ 332#define PZL_BITS(l) (((l) & 0x03) + 5) 333#define PZL_PARITY(l) (((l) & 0x18) >> 3) 334#define PZL_SPEED(l) (((l) & 0x3c0) >> 6) 335#define PZL_ENCODE(bits, parity, speed) \ 336 (((bits) - 5) & 0x03) | (((parity) & 0x3) << 3) | \ 337 (((speed) & 0x0f) << 6) 338}; 339 340struct pdc_result { /* general result buffer */ 341 u_int result[32]; 342}; 343 344struct pdc_pim { /* PDC_PIM */ 345 u_int count; /* actual (HPMC, LPMC) or total (SIZE) count */ 346 u_int archsize; /* size of architected regions (see "pim.h") */ 347}; 348 349struct pdc_model { /* PDC_MODEL */ 350 u_int res1 : 16; /* reserved */ 351 u_int hwmodel : 12; /* hardware model. */ 352 u_int hv : 4; 353 u_int rev : 4; /* zero for all native processors */ 354 u_int model : 20; /* 4 for all native processors */ 355 u_int sh : 1; /* shadow registers are present */ 356 u_int reserved : 2; /* reserved */ 357 u_int mc : 1; /* module category (A - 0, B - 1) */ 358 u_int reserved1 : 2; /* reserved */ 359 u_int pa_lvl : 2; /* PA-RISC level */ 360 u_int hw_id; /* unique processor hardware identifier */ 361 u_int boot_id; /* same as hw_id */ 362 u_int sw_id; /* software security and licensing */ 363 u_int sw_cap; /* OS capabilities of processor */ 364 u_int arch_rev; /* architecture revision */ 365 u_int pot_key; /* potential key */ 366 u_int curr_key; /* current key */ 367}; 368 369struct pdc_cpuid { /* PDC_MODEL, PDC_CPUID */ 370 u_int reserved : 20; 371 u_int version : 7; /* CPU version */ 372 u_int revision : 5; /* CPU revision */ 373}; 374 375struct pdc_getbootopts { /* PDC_MODEL_GETBOOTOPTS */ 376 u_int cur_test; /* current enabled tests */ 377 u_int sup_test; /* supported tests */ 378 u_int def_test; /* default enabled tests */ 379}; 380 381struct cache_cf { /* PDC_CACHE (for "struct pdc_cache") */ 382 u_int cc_alias: 4, /* virtual address aliasing boundary */ 383 cc_block: 4, /* used to determine most efficient stride */ 384 cc_line : 3, /* max data written by store (16-byte mults) */ 385 cc_resv1: 2, /* (reserved) */ 386 cc_wt : 1, /* D-cache: write-to = 0, write-through = 1 */ 387 cc_sh : 2, /* separate I and D = 0, shared I and D = 1 */ 388 cc_cst : 3, /* D-cache: incoherent = 0, coherent = 1 */ 389 cc_resv2:11, /* (reserved) */ 390 cc_hvers: 2; /* H-VERSION dependent */ 391}; 392 393struct itlb_cf { /* PDC_CACHE (for "struct pdc_cache") */ 394 u_int tc_resv1:12, /* (reserved) */ 395 tc_sh : 2, /* separate I and D = 0, shared I and D = 1 */ 396 tc_hvers: 1, /* H-VERSION dependent */ 397 tc_page : 1, /* 2K page size = 0, 4k page size = 1 */ 398 tc_cst : 3, /* incoherent = 0, coherent = 1 */ 399 tc_aid : 5, /* access id width = 15 + aid */ 400 tc_sr : 6, /* space id width */ 401 tc_hv2 : 2; /* H-VERSION dependent */ 402}; 403 404struct dtlb_cf { /* PDC_CACHE (for "struct pdc_cache") */ 405 u_int tc_resv1:12, /* (reserved) */ 406 tc_sh : 2, /* separate I and D = 0, shared I and D = 1 */ 407 tc_hvers: 1, /* H-VERSION dependent */ 408 tc_u : 1, /* TLB U bit implemented */ 409 tc_cst : 3, /* incoherent = 0, coherent = 1 */ 410 tc_resv2: 11, /* (reserved) */ 411 tc_hv2 : 2; /* H-VERSION dependent */ 412}; 413 414struct pdc_cache { /* PDC_CACHE */ 415/* Instruction cache */ 416 u_int ic_size; /* size of I-cache (in bytes) */ 417 struct cache_cf ic_conf;/* cache configuration (see above) */ 418 u_int ic_base; /* start addr of I-cache (for FICE flush) */ 419 u_int ic_stride; /* addr incr per i_count iteration (flush) */ 420 u_int ic_count; /* number of i_loop iterations (flush) */ 421 u_int ic_loop; /* number of FICE's per addr stride (flush) */ 422/* Data cache */ 423 u_int dc_size; /* size of D-cache (in bytes) */ 424 struct cache_cf dc_conf;/* cache configuration (see above) */ 425 u_int dc_base; /* start addr of D-cache (for FDCE flush) */ 426 u_int dc_stride; /* addr incr per d_count iteration (flush) */ 427 u_int dc_count; /* number of d_loop iterations (flush) */ 428 u_int dc_loop; /* number of FDCE's per addr stride (flush) */ 429/* Instruction TLB */ 430 u_int it_size; /* number of entries in I-TLB */ 431 struct itlb_cf it_conf; /* I-TLB configuration (see above) */ 432 u_int it_sp_base; /* start space of I-TLB (for PITLBE flush) */ 433 u_int it_sp_stride; /* space incr per sp_count iteration (flush) */ 434 u_int it_sp_count; /* number of off_count iterations (flush) */ 435 u_int it_off_base; /* start offset of I-TLB (for PITLBE flush) */ 436 u_int it_off_stride; /* offset incr per off_count iteration (flush)*/ 437 u_int it_off_count; /* number of it_loop iterations/space (flush) */ 438 u_int it_loop; /* number of PITLBE's per off_stride (flush) */ 439/* Data TLB */ 440 u_int dt_size; /* number of entries in D-TLB */ 441 struct dtlb_cf dt_conf; /* D-TLB configuration (see above) */ 442 u_int dt_sp_base; /* start space of D-TLB (for PDTLBE flush) */ 443 u_int dt_sp_stride; /* space incr per sp_count iteration (flush) */ 444 u_int dt_sp_count; /* number of off_count iterations (flush) */ 445 u_int dt_off_base; /* start offset of D-TLB (for PDTLBE flush) */ 446 u_int dt_off_stride; /* offset incr per off_count iteration (flush)*/ 447 u_int dt_off_count; /* number of dt_loop iterations/space (flush) */ 448 u_int dt_loop; /* number of PDTLBE's per off_stride (flush) */ 449}; 450 451struct pdc_spidb { /* PDC_CACHE, PDC_CACHE_GETSPIDB */ 452 u_int spidR1 : 4; 453 u_int spidbits : 12; 454 u_int spidR2 : 16; 455}; 456 457struct pdc_cst { 458 u_int cstR1 : 16; 459 u_int cst : 3; 460 u_int cstR2 : 13; 461}; 462 463struct pdc_coherence { /* PDC_CACHE, PDC_CACHE_SETCS */ 464 struct pdc_cst ia; 465#define ia_cst ia.cst 466 struct pdc_cst da; 467#define da_cst da.cst 468 struct pdc_cst ita; 469#define ita_cst ita.cst 470 struct pdc_cst dta; 471#define dta_cst dta.cst 472}; 473 474struct pdc_hpa { /* PDC_HPA */ 475 hppa_hpa_t hpa; /* HPA of processor */ 476}; 477 478struct pdc_coproc { /* PDC_COPROC */ 479 u_int ccr_enable; /* same format as CCR (CR 10) */ 480 u_int ccr_present; /* which co-proc's are present (bitset) */ 481 u_int pad[15]; 482 u_int fpu_revision; 483 u_int fpu_model; 484}; 485 486struct pdc_tod { /* PDC_TOD, PDC_TOD_READ */ 487 u_int sec; /* elapsed time since 00:00:00 GMT, 1/1/70 */ 488 u_int usec; /* accurate to microseconds */ 489}; 490 491struct pdc_itimer { /* PDC_TOD_ITIMER */ 492 u_int calib0; /* double giving itmr freq */ 493 u_int calib1; 494 u_int tod_acc; /* TOD accuracy in 1e-9 part */ 495 u_int cr_acc; /* itmr accuracy in 1e-9 parts */ 496}; 497 498struct pdc_nvm { /* PDC_NVM */ 499 u_int hv[9]; /* 0x00: HV dependent */ 500 struct device_path bootpath; /* 0x24: boot path */ 501 u_int isl_ver; /* 0x44: ISL revision */ 502 u_int timestamp; /* 0x48: timestamp */ 503 u_int lif_ue[12]; /* 0x4c: LIF utility entries */ 504 u_int eptr; /* 0x7c: entry pointer */ 505 u_int os_panic[32]; /* 0x80: OS panic info */ 506}; 507 508struct pdc_instr { /* PDC_INSTR */ 509 u_int instr; /* instruction that invokes PDC mchk entry pt */ 510}; 511 512struct pdc_iodc_read { /* PDC_IODC, PDC_IODC_READ */ 513 int size; /* number of bytes in selected entry point */ 514 int filler1; 515 u_int filler2[30]; 516}; 517 518struct pdc_iodc_minit { /* PDC_IODC, PDC_IODC_NINIT or PDC_IODC_DINIT */ 519 u_int stat; /* HPA.io_status style error returns */ 520 u_int max_spa; /* size of SPA (in bytes) > max_mem+map_mem */ 521 u_int max_mem; /* size of "implemented" memory (in bytes) */ 522 u_int map_mem; /* size of "mappable-only" memory (in bytes) */ 523}; 524 525struct btlb_info { /* for "struct pdc_btlb" (PDC_BTLB) */ 526 u_int resv0: 8, /* (reserved) */ 527 num_i: 8, /* Number of instruction slots */ 528 num_d: 8, /* Number of data slots */ 529 num_c: 8; /* Number of combined slots */ 530}; 531 532struct pdc_btlb { /* PDC_BLOCK_TLB */ 533 u_int min_size; /* Min size in pages */ 534 u_int max_size; /* Max size in pages */ 535 struct btlb_info finfo; /* Fixed range info */ 536 struct btlb_info vinfo; /* Variable range info */ 537}; 538 539struct pdc_hwtlb { /* PDC_TLB */ 540 u_int min_size; /* What do these mean? */ 541 u_int max_size; 542}; 543 544struct pdc_power_info { /* PDC_SOFT_POWER_INFO */ 545 u_int addr; /* power register address */ 546}; 547 548struct pdc_pat_cell_id { /* PDC_PAT_CELL_GETID */ 549 u_long id; /* cell id */ 550 u_long loc; /* cell location */ 551}; 552 553struct pdc_pat_cell_module { /* PDC_PAT_CELL_MODULE */ 554 u_long chpa; /* config space HPA */ 555 u_long info; /* module info */ 556#define PDC_PAT_CELL_MODTYPE(t) (((t) >> 56) & 0xff) 557#define PDC_PAT_CELL_MODDVI(t) (((t) >> 48) & 0xff) 558#define PDC_PAT_CELL_MODIOC(t) (((t) >> 40) & 0xff) 559#define PDC_PAT_CELL_MODSIZE(t) (((t) & 0xffffff) << PAGE_SHIFT) 560 u_long loc; /* module location */ 561 struct device_path dp; /* module path */ 562 u_long pad[508]; /* cell module gedoens */ 563}; 564 565struct pdc_pat_io_num { /* PDC_PAT_IO */ 566 u_int num; 567}; 568 569struct pdc_pat_pci_rt { /* PDC_PAT_IO_GET_PCI_RT */ 570 uint8_t type; /* 0x8b */ 571 uint8_t len; 572 uint8_t itype; /* 0 -- vectored int */ 573 uint8_t trigger; /* polarity/level */ 574 uint8_t pin; /* PCI pin number */ 575 uint8_t bus; 576 uint8_t seg; /* reserved */ 577 uint8_t line; 578 uint64_t addr; /* io sapic address */ 579}; 580 581struct pdc_memmap { /* PDC_MEMMAP */ 582 u_int hpa; /* HPA for module */ 583 u_int morepages; /* additional IO pages */ 584}; 585 586struct pdc_system_map_find_mod { /* PDC_SYSTEM_MAP_FIND_MOD */ 587 u_int hpa; 588 u_int size; /* pages */ 589 u_int naddrs; 590 u_int mod_index; 591}; 592 593struct pdc_system_map_find_addr { /* PDC_SYSTEM_MAP_FIND_ADDR */ 594 u_int hpa; 595 u_int size; /* pages */ 596}; 597 598struct pdc_lan_station_id { /* PDC_LAN_STATION_ID */ 599 uint8_t addr[6]; 600}; 601 602/* 603 * The PDC_CHASSIS is a strange bird. The format for updating the display 604 * is as follows: 605 * 606 * 0 11 12 14 15 16 19 20 23 24 27 28 31 607 * +-------+----------+-------+--------+--------+--------+--------+ 608 * | R | OS State | Blank | Hex1 | Hex2 | Hex3 | Hex4 | 609 * +-------+----------+-------+--------+--------+--------+--------+ 610 * 611 * Unfortunately, someone forgot to tell the hardware designers that 612 * there was supposed to be a hex display somewhere. The result is, 613 * you can only toggle 5 LED's and the fault light. 614 * 615 * Interesting values for Hex1-Hex4 and the resulting LED displays: 616 * 617 * FnFF CnFF: 618 * 0 - - - - - Counts in binary from 0x0 - 0xF 619 * 2 o - - - - for corresponding values of `n'. 620 * 4 o o - - - 621 * 6 o o o - - 622 * 8 o o o o - 623 * A o o o o o 624 * 625 * If the "Blank" bit is set, the display should be made blank. 626 * The values for "OS State" are defined below. 627 */ 628 629#define PDC_CHASSIS_BAR 0xF0FF /* create a bar graph with LEDs */ 630#define PDC_CHASSIS_CNT 0xC0FF /* count with LEDs */ 631 632#define PDC_OSTAT(os) (((os) & 0x7) << 17) 633#define PDC_OSTAT_OFF 0x0 /* all off */ 634#define PDC_OSTAT_FAULT 0x1 /* the red LED of death */ 635#define PDC_OSTAT_TEST 0x2 /* self test */ 636#define PDC_OSTAT_BOOT 0x3 /* boot program running */ 637#define PDC_OSTAT_SHUT 0x4 /* shutdown in progress */ 638#define PDC_OSTAT_WARN 0x5 /* battery dying, etc */ 639#define PDC_OSTAT_RUN 0x6 /* OS running */ 640#define PDC_OSTAT_ON 0x7 /* all on */ 641 642struct pdc_chassis_info { 643 u_int size; 644 u_int max_size; 645}; 646 647struct pdc_chassis_lcd { 648 u_int model : 16, 649 width : 16; 650 u_int cmd_addr; 651 u_int data_addr; 652 u_int delay; 653 uint8_t line[2]; 654 uint8_t enabled; 655 uint8_t heartbeat[3]; 656 uint8_t disk[3]; 657}; 658 659/* 660 * A processors Stable Storage is accessed through the PDC. There are 661 * at least 96 bytes of stable storage (the device path information may 662 * or may not exist). However, as far as I know, processors provide at 663 * least 192 bytes of stable storage. 664 */ 665struct stable_storage { 666 struct device_path ss_pri_boot; /* (see above) */ 667 char ss_filenames[32]; 668 u_short ss_os_version; /* 0 == none, 1 == HP-UX, 2 == MPE-XL */ 669 char ss_os[22]; /* OS-dependent information */ 670 char ss_pdc[7]; /* reserved */ 671 char ss_fast_size; /* how much memory to test. 0xf == all, or */ 672 /* else it's (256KB << ss_fast_size) */ 673 struct device_path ss_console; 674 struct device_path ss_alt_boot; 675 struct device_path ss_keyboard; 676}; 677 678/* 679 * Recoverable error indications provided to boot code by the PDC. 680 * Any non-zero value indicates error. 681 */ 682struct boot_err { 683 u_int be_resv : 10, /* (reserved) */ 684 be_fixed : 6, /* module that produced error */ 685 be_chas : 16; /* error code (interpret as 4 hex digits) */ 686}; 687 688#define HPBE_HBOOT_CORRECTABLE 0 /* hard-boot corrctable error */ 689#define HPBE_HBOOT_UNCORRECTBL 1 /* hard-boot uncorrectable error */ 690#define HPBE_SBOOT_CORRECTABLE 2 /* soft-boot correctable error */ 691#define HPBE_SBOOT_UNCORRECTBL 3 /* soft-boot uncorrectable error */ 692#define HPBE_ETEST_MODUNUSABLE 4 /* ENTRY_TEST err: module's unusable */ 693#define HPBE_ETEST_MODDEGRADED 5 /* ENTRY_TEST err: module in degraded mode */ 694 695 696/* 697 * The PDC uses the following structure to completely define an I/O 698 * module and the interface to its IODC. 699 */ 700typedef 701struct pz_device { 702 struct device_path pz_dp; 703#define pz_flags pz_dp.dp_flags 704#define pz_bc pz_dp.dp_bc 705#define pz_mod pz_dp.dp_mod 706#define pz_layers pz_dp.dp_layers 707 struct iomod *pz_hpa; /* HPA base address of device */ 708 void * pz_spa; /* SPA base address (zero if no SPA exists) */ 709 iodcio_t pz_iodc_io; /* entry point of device's driver routines */ 710 short pz_resv; /* (reserved) */ 711 u_short pz_class; /* (see below) */ 712} pz_device_t; 713 714/* pz_class */ 715#define PCL_NULL 0 /* illegal */ 716#define PCL_RANDOM 1 /* random access (disk) */ 717#define PCL_SEQU 2 /* sequential access (tape) */ 718#define PCL_DUPLEX 7 /* full-duplex point-to-point (RS-232, Net) */ 719#define PCL_KEYBD 8 /* half-duplex input (HIL Keyboard) */ 720#define PCL_DISPL 9 /* half-duplex ouptput (display) */ 721#define PCL_FC 10 /* fibre channel access media */ 722#define PCL_CLASS_MASK 0xf /* XXX class mask */ 723#define PCL_NET_MASK 0x1000 /* mask for bootp/tftp device */ 724 725/* 726 * The following structure defines what a particular IODC returns when 727 * given the IODC_DATA argument. 728 */ 729struct iodc_data { 730 u_int iodc_model: 8, /* hardware model number */ 731 iodc_revision:8, /* software revision */ 732 iodc_spa_io: 1, /* 0:memory, 1:device */ 733 iodc_spa_pack:1, /* 1:packed multiplexor */ 734 iodc_spa_enb:1, /* 1:has an spa */ 735 iodc_spa_shift:5, /* power of two # bytes in SPA space */ 736 iodc_more: 1, /* iodc_data is: 0:8-byte, 1:16-byte */ 737 iodc_word: 1, /* iodc_data is: 0:byte, 1:word */ 738 iodc_pf: 1, /* 1:supports powerfail */ 739 iodc_type: 5; /* see below */ 740 u_int iodc_sv_rev: 4, /* software version revision number */ 741 iodc_sv_model:20, /* software interface model # */ 742 iodc_sv_opt: 8; /* type-specific options */ 743 u_char iodc_rev; /* revision number of IODC code */ 744 u_char iodc_dep; /* module-dependent information */ 745 u_char iodc_rsv[2]; /* reserved */ 746 u_short iodc_cksum; /* 16-bit checksum of whole IODC */ 747 u_short iodc_length; /* number of entry points in IODC */ 748 /* IODC entry points follow... */ 749}; 750 751extern pdcio_t pdc; 752 753#ifdef _KERNEL 754struct consdev; 755 756extern int kernelmapped; 757 758enum pdc_type { 759 PDC_TYPE_UNKNOWN, 760 PDC_TYPE_SNAKE 761}; 762 763void pdc_init(void); 764void pdc_settype(int); 765enum pdc_type pdc_gettype(void); 766 767int pdc_call(iodcio_t, int, ...); 768 769void pdccnprobe(struct consdev *); 770void pdccninit(struct consdev *); 771int pdccngetc(dev_t); 772void pdccnputc(dev_t, int); 773void pdccnpollc(dev_t, int); 774 775int pdcproc_chassis_display(unsigned long); 776int pdcproc_chassis_info(struct pdc_chassis_info *, struct pdc_chassis_lcd *); 777 778int pdcproc_pim(int, struct pdc_pim *, void **, size_t *); 779 780int pdcproc_model_info(struct pdc_model *); 781int pdcproc_model_cpuid(struct pdc_cpuid *); 782 783int pdcproc_cache(struct pdc_cache *); 784int pdcproc_cache_coherence(struct pdc_coherence *); 785int pdcproc_cache_spidbits(struct pdc_spidb *); 786 787int pdcproc_hpa_processor(hppa_hpa_t *); 788 789int pdcproc_coproc(struct pdc_coproc *); 790 791int pdcproc_iodc_read(hppa_hpa_t, int, int *, struct pdc_iodc_read *, size_t, 792 struct iodc_data *, size_t); 793int pdcproc_iodc_ninit(struct pdc_iodc_minit *, hppa_hpa_t, int); 794 795int pdcproc_instr(unsigned int *); 796 797int pdcproc_block_tlb(struct pdc_btlb *); 798int pdcproc_btlb_insert(pa_space_t, vaddr_t, paddr_t, vsize_t, u_int, int); 799int pdcproc_btlb_purge(pa_space_t, vaddr_t, paddr_t, vsize_t); 800int pdcproc_btlb_purgeall(void); 801 802int pdcproc_tlb_info(struct pdc_hwtlb *); 803int pdcproc_tlb_config(struct pdc_hwtlb *, vaddr_t, vsize_t, unsigned long); 804 805int pdcproc_system_map_find_mod(struct pdc_system_map_find_mod *, 806 struct device_path *, int); 807int pdcproc_system_map_find_addr(struct pdc_system_map_find_addr *, int, int); 808int pdcproc_system_map_trans_path(struct pdc_memmap *, struct device_path *); 809 810int pdcproc_soft_power_enable(int); 811int pdcproc_soft_power_info(struct pdc_power_info *); 812 813int pdcproc_memmap(struct pdc_memmap *, struct device_path *); 814 815int pdcproc_ioclrerrors(void); 816int pdcproc_ioreset(void); 817 818int pdcproc_doreset(void); 819 820int pdcproc_lan_station_id(char *, size_t, hppa_hpa_t); 821 822int pdcproc_pci_inttblsz(int *); 823int pdcproc_pci_gettable(int, size_t, void *); 824 825#endif 826 827#endif /* !(_LOCORE) */ 828 829#endif /* _MACHINE_PDC_H_ */ 830